View source for DRV11-B Direct Memory Access Interface

The '''DRV11-B Direct Memory Access Interface''' is a [[parallel interface]] [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data.

It is effectively a [[half-duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.

It was a [[DEC card form factor|quad]] format card (M7950); connection to the user's device is via a pair of 40-[[pin]] [[Berg connector]]s.

==Registers==

The device has five control and [[buffer]] registers, which can be configured to any group of four sequential [[word]] locations in the I/O page; the first DRV11-B is normally configured to addresses 772410-72416. The two buffer registers share an address, responding to read or write cycles as the case might be.

{| border=1
! Register !! Abbreviation !! Address
|-
|Word Count Register || DRWCR || 767770
|-
|Bus Address Register || DRBAR || 767772
|-
|Control and Status Register || DRCSR || 767774
|-
|Input Data Buffer Register || DRINBUF || 767776 (read)
|-
|Output Data Buffer Register || DROUTBUF || 767776 (write)
|}

In the register contents (below), bits which are read/write are shown in normal font, those which are read-only are in ''italics'', and write-only in '''bold'''.

===Word Count Register (DRWCR)===
{{16bit-header}}
| colspan=16 | WC15 <-> WC0
{{16bit-bitout}}

===Bus Address Register (DRBAR)===
{{16bit-header}}
| colspan=15 | BA15 <-> BA1 || 0
{{16bit-bitout}}

===Status Register (DRCSR)===
{{16bit-header}}
| ''ERR'' || ''NEX'' || ''ATTN'' || MAINT || colspan=3 | ''STATUS'' || CYCLE || ''RDY'' || IE || colspan=2 | XAD || colspan=3 | FNCT || '''GO'''
{{16bit-bitout}}

* ERR - Error; set by NEX or ATTN
* NEX - Nonexistent Memory; also write-to-zero
* ATTN - Attention; signal from user's hardware which can be tested, or cause an [[interrupt]] (below) 
* MAINT - Maintenance
* STATUS - Signals from user hardware
* CYCLE - DMA cycle requested
* RDY - DRV11-B is able to accept a new command; set by ERR or WCR overflow, cleared by GO
* IE - Interrupt Enable - When set, allows setting RDY to cause an interrupt 
* XAD - Extended Address; extension of BAR
* FNCT - Signals to user's hardware
* GO - Enables DMA, sent to user's hardware

===Output Buffer Register (DROUTBUF)===
{{16bit-header}}
| colspan=16 | OUT15 <-> OUT0
{{16bit-bitout}}

===Input Buffer Register (INBUF)===
{{16bit-header}}
| colspan=16 | ''IN15 <-> IN0''
{{16bit-bitout}}

[[Category: QBUS Parallel Interfaces]]