UNIBUS Initialization

The is an exact transcription of the "Initialization Section" section (pp. 52-56) of the "pdp11 bus handbook" (DEC, 1979).

Initialization Section

The Initialization section of the UNIBUS controls initializing or resetting, and the power-up and power-down sequences of all bus devices. Three UNIBUS signals are used: INIT, AC LO, and DC LO.

Initialization (INIT)

INIT is caused by some console operations, the RESET instruction, and DC LO. Only a processor, or the arbitrator, may assert INIT.

Processor Requirements

A processor must become bus master, then wait for 5 μseconds before it may assert INIT. No bus cycles may be executed during these 5 μseconds. This delay ensures that all memory cycles in progress are complete before asserting INIT.

However, if a processor tries to assert INIT but cannot obtain the use of the data section of the bus after 100 μseconds, it may then assert INIT without becoming bus master.

A processor, as bus master through a grant sequence, may not negate SACK until after it asserts INIT. This ensures that the arbitrator receives the assertion of INIT before the negation of SACK. This prevents the arbitrator from starting arbitration until it receives the negation of INIT.

Any processor, after negating INIT, must wait 75 nseconds before asserting any signal, except AC LO, DC LO, or INIT. This ensures that the negation of INIT reaches all bus devices before the processor asserts any signal on the data section of the bus.

Arbitrator Response

Upon receipt of the assertion of INIT, the arbitrator negates all grants and may not issue any for events that occurred before INIT. No grant may be issued while INIT is asserted.

Master/Slave Device Response

When a master/slave device receives the assertion of INIT, it responds as follows.

1. It completes any bus cycle in process. If the device is bus master, then it negates BBSY. If the bus cycle in progress is a DATIP, the master completes the DATO/B. The memory must be capable of completing the DATO/B, or it must restore itself and treat any following DATO/B as a new transaction.
2. It negates any of the following signals that it may be asserting: SACK, NPR, BR4, BR5, BR6, BR7; and it passes all grants.
3. It clears the Interrupt Enable bit. It may assert AC LO, DC LO, and any signal required by step 1 above. It may not assert NPR, BR, SACK, or BBSY.

After receipt of the negation of INIT, a device must be reset for normal programming. If the device is not ready, it may set a busy bit until its internal initialization sequence is finished. The device may have an error condition set. Some of the device registers may contain new or old values. The contents of these registers after receipt of the negation of INIT should be defined in the device specification. Devices should retain as much status information as possible in order to make error analysis easier.

A device is not required to buffer commands received during its internal initialization sequence, provided it sets a bit indicating that it is not ready to accept commands (busy bit).

Power-up and Power-down Sequences

The purpose of the power-up and power-down sequences is to guarantee time to store (on power-down) and retrieve (on power-up) the program parameters required for continued operation.

A DC power failure, as used here, means that DC power has dropped below its minimum operating level.

1. When power is off in any UNIBUS device, AC LO and DC LO are asserted and all other UNIBUS signals are undefined.
2. When the DC voltage to the processor rises to a level at which the logic elements operate, DC LO initializes the processor with BBSY and INIT asserted.
3. (Power-up) DC Lo is negated by the power supply 5 μseconds after DC power is within specifications.
4. INIT remains asserted for a minimum of 10 mseconds after receipt of the negation of DC LO. This provides time for initialization of most bus devices.
5. The processor waits a minimum of 70 mseconds after the negation of DC LO to allow all bus devices to complete their internal initialization operations.
6. Before or at the end of this 70 msecond delay, INIT is negated. The processor then tests AC LO. When it senses the negation AC LO, the processor starts its power-up sequenc; and the arbitrator is enabled. AC LO must not be negated by the power supply for less than 1 μsecond.

NOTE: While AC LO is negated, DC power is guaranteed to be within   specifications for a minimum of 5 mseconds + 5 μseconds.

7. The processor waits a minimum of 2 mseconds before testing AC LO again. These 2 mseconds are used by the processor for its power-up sequence.
8. Having completed its power-up sequence, the processor continuously monitors AC LO.
9. (Power-down) Upon receipt of the assertion of AC LO, a processor starts it power-down routine. (AC LO must not be asserted by the power supply for less than 1 μsecond.) The processor does not test AC LO again until its next power-up sequence.
10. For a minimum of 2 mseconds, and a maximum of 3 mseconds, the processor asserts BBSY and does not use the data section of the bus. It stops execution of programs.
11. A minimum of 5 μseconds later, the processor asserts DC LO for at least 1 μsecond. This, in turn, asserts INIT for same time period.
12. The subsequent negation of DC LO by the processor is the beginning of a power-up sequence, as in step 3 above. DC LO may be held asserted by a power-supply or by another bus device.
13. DC LO must not be asserted by the power supply for a minimum of 5 mseconds after it asserts AC LO. The ensures enough time is available for a complete power-up and power-down cycle.
14. DC power must be within specification for a minimum of 5 μseconds after the assertion of DC LO by the power supply.

NOTE: The power-up sequence starts at the negation of AC LO 70 mseconds after negation of DC LO. AC LO is not tested during the 2 mseconds allotted to the power-up sequence. It follows that if AC LO is re-asserted before the end of the power-up sequence (2 mseconds), the power-down sequence (2-3 mseconds) must be performed immediately following the power-up sequence. This requires a 5 msecond minimum of guaranteed DC power at the negation of AC LO. This also implies that 5 mseconds of guaranteed DC power is available at any time while AC LO is negated.

A brown-out occurs when AC LO is asserted, but DC power is within specifications. (DC LO is negated). In this case, the processor waits for the negation of AC LO as in step 6 above.