Difference between revisions of "Emitter-coupled logic"
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| − | '''Emitter-coupled logic''' (almost always used as an acronym, '''ECL''') was, for several decades, the fastest logic family, reaching peak | + | '''Emitter-coupled logic''' (almost always used as an acronym, '''ECL''') was, for several decades, the fastest logic family, reaching peak speeds of less than 1 nsec delay. |
| − | The basic concept in ECL is that in each [[gate]], there are two paths through | + | The basic concept in ECL is that in each [[gate]]'s output stage, there are two paths through it with a constant [[current]], to two different outputs. As the gate operates, the current is switched between one output and the other; the pair thus form complementary outputs. |
The availability of complementary outputs has a number of advantages: individual [[inverter]]s are almost never needed, reducing the total number of gate delays; the outputs can also be fed directly into a [[differential pair]]. | The availability of complementary outputs has a number of advantages: individual [[inverter]]s are almost never needed, reducing the total number of gate delays; the outputs can also be fed directly into a [[differential pair]]. | ||
| − | Since there is always a constant current flowing, ECL gates do not create spikes on the power supply line when they switch; however, they use a lot of power. | + | Since there is always a constant current flowing, ECL gates do not create spikes on the power supply line when they switch; however, they use a lot of power (constantly). |
==Internals== | ==Internals== | ||
Revision as of 03:37, 30 March 2018
Emitter-coupled logic (almost always used as an acronym, ECL) was, for several decades, the fastest logic family, reaching peak speeds of less than 1 nsec delay.
The basic concept in ECL is that in each gate's output stage, there are two paths through it with a constant current, to two different outputs. As the gate operates, the current is switched between one output and the other; the pair thus form complementary outputs.
The availability of complementary outputs has a number of advantages: individual inverters are almost never needed, reducing the total number of gate delays; the outputs can also be fed directly into a differential pair.
Since there is always a constant current flowing, ECL gates do not create spikes on the power supply line when they switch; however, they use a lot of power (constantly).
Internals
An ECL gate output uses a pair of transistors, with both their emitters connected to the low voltage in the system (often ground) - hence the name ECL. The collectors on both, which are the outputs, are connected to the supply (high) voltage through small resistors.
The base of one transistor is connected to a reference voltage, roughly half-way between the high and low supply voltages. The base of the other transistor is the input. When it is slightly above the reference voltage, all the current flows through that transistor; when slightly below, all the current flows through the other.
