Difference between revisions of "Bus grant"
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| − | + | A '''bus grant''' is when the [[Central Processing Unit|CPU]] (or '''bus arbiter''', in machines in which the two are separate) turns over a [[bus]] to a [[device controller]] so that the device can either start an [[interrupt]], or do [[Direct Memory Access|DMA]] transfer(s) to [[main memory]]. | |
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| + | This obviously requires the computer to have a bus on which the devices can do more than simply respond to read and write requests from the CPU. Most do, although in some computers (e.g. some [[mainframe]]s, and now high-performance [[personal computer]]s), devices may have a private bus to main memory, which is [[multi-port memory]], so in those systems, DMA cycles will not need a bus grant. | ||
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| + | ==See also== | ||
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| + | * [[Bus grant line]] | ||
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| + | {{semi-stub}} | ||
Revision as of 15:27, 18 September 2018
A bus grant is when the CPU (or bus arbiter, in machines in which the two are separate) turns over a bus to a device controller so that the device can either start an interrupt, or do DMA transfer(s) to main memory.
This obviously requires the computer to have a bus on which the devices can do more than simply respond to read and write requests from the CPU. Most do, although in some computers (e.g. some mainframes, and now high-performance personal computers), devices may have a private bus to main memory, which is multi-port memory, so in those systems, DMA cycles will not need a bus grant.
