Difference between revisions of "Chaosnet interface"

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m (Jnc moved page QBCHNI to Chaosnet interface: QBUS and UNIBUS interfaces are very similar, will cover on the same page)
(A start; will add register defs later)
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The '''QBCHNI''' is a [[QBUS]] card with a [[CHAOSnet]] interface.
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[[Image:CH11-board.png|thumb|right|250px|CH11 Unibus board]]
  
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== External Links ==
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The '''Chaosnet UNIBUS interface''' (also called the '''CHAOS-11''', '''CH11''', '''QUAD''' and '''QAD'''; there was no generally-used name) and '''QBCHNI''' are [[Chaosnet]] [[network interface]]s, for the [[UNIBUS]] and [[QBUS]] respectively. (The two [[device controller]]s are identical in [[program]]ming terms, so they are both covered in this single article.)
  
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* [https://github.com/hanshuebner/cadr2/blob/master/mit/chaos/quad.setup "how to setup ... QBCHNI Chaosnet Interfaces (the LSI-11 Q-Bus version)"]
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They use [[programmed I/O]] to transfer data to and from [[buffer]]s in [[main memory]]. They have on-board buffers (one each for inbound and outbound) which can hold one [[packet]] of data.
  
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{{stub}}
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They are both a single [[DEC card form factor|quad]] [[wire-wrap]]ped card. <!-- They therefore take up two slots; a [[grant continuity card]] is required, to plug into the second slot, to carry the QBUS' [[bus grant line]]s through the second slot, if there are any devices down-bus from them.
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I am not certain of this; I think cards with pins on the back did this, which is why they made card with pins on the package side. -->
  
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Their [[bus]] [[address]] <!-- and [[interrupt vector]]s --> can be set via [[Dual Inline Package|DIP]] switches; <!-- to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. --> the default is 0764140<!-- and 0340 - looks like there are enough DIPs for the vector too, but no docs -->. The [[network address]] is also set via a DIP switch.
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==Device registers==
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They have 7 [[register]]s:
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{| border=1
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! Register !! Abbreviation !! Address
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|-
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|Command and Status Register      || CAICSR || 764140
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|-
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|My address (read only)            || CAIMYN || 764142
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|-
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|Write buffer (write only)        || CAIWBF || 764142
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|-
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|Read buffer                      || CAIRBF || 764144
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|-
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|Read bit counter                  || CAIRBC || 764146
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|-
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|Unused                            || &nbsp; || 764150
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|-
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|Initiate transmission            || CAIXMT || 764152
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|-
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|Unused                            || &nbsp; || 764154
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|-
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|Unused                            || &nbsp; || 764156
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|-
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|Load interval timer (write only)  || CAITIM || 764160
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|}
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In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics'', and those which are write-only are shown in '''bold'''.
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<!-- ===764000: Control Status Register (CSR)===
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{{16bit-header}}
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| colspan=2 | '''XM''' || colspan=6 | '''FUNC''' || ''CDN'' || CIE || ''RDN'' || RIE || colspan=4 | ''STAT''
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{{16bitoctal-bitout}}
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Bits are:
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{| class="wikitable"
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! Bits !! Use
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|-
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| XM || Extended address bits A17 and A16
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|-
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| FUNC || Command Function Code
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|-
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| CDN || Command Done
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|-
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| CIE || Command Done Interrupt Enable
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|-
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| RDN || Receive DMA Done
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|-
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| RIE || Receive DMA Done Interrupt Enable
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|-
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| STAT || Command Status Code
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|}
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#define CH_TBSY 01              /* Transmitter busy */
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#define CH_LPBK 02              /* Loop back in interface */
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#define CH_SPY  04              /* Spy - accept any messages */
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#define CH_REN  010            /* Receive enable */
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#define CH_RIEN 020            /* Receive interrupt enable */
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#define CH_TIEN 040            /* Transmit interrupt enable */
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#define CH_ABRT 0100            /* Transmit aborted by conflict */
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#define CH_TDN  0200            /* Transmission done */
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#define CH_TCLR 0400            /* Transmitter clear */
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#define CH_LC1  01000          /* Count of messages lost */
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#define CH_LC2  02000
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#define CH_LC3  04000
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#define CH_LC4  010000
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#define CH_LC  (CH_LC1 | CH_LC2 | CH_LC3 | CH_LC4)
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#define CH_RST  020000          /* I/O reset for interface */
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#define CH_CRC  040000          /* CRC error */
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#define CH_RDN  0100000        /* Input done */
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===764002: Bus Address Register (BAR)===
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{{16bit-header}}
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| colspan=16 | '''BA15 <--- BA00'''
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{{16bitoctal-bitout}}
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Write-only register.
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===764004: Byte Count Register (BCR)===
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{{16bit-header}}
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| colspan=16 | '''BC15 <--- BC0'''
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{{16bitoctal-bitout}}
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Write-only register. -->
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==External links ==
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<!-- * [https://github.com/hanshuebner/cadr2/blob/master/mit/chaos/quad.setup "how to setup ... QBCHNI Chaosnet Interfaces (the LSI-11 Q-Bus version)"]  dup of one below -->
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* [https://github.com/PDP-10/its-vault/tree/master/files/chaos CHAOS;] - includes drawings and documentation
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** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/chs.defs CHS DEFS] - register declarations
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** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/%24quad.log $QUAD LOG] - "Log of ChaosNet Interface Boards (quad-high, PDP-11 version)"
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** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/quad.setup QUAD SETUP] - "how to setup .. Chaosnet Interfaces"
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** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/quad.eco QUAD ECO] - "ECO to .. Change cable speed to 4 MHz"
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** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/qadchs.note QADCHS NOTE] - random jottings
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[[Category: UNIBUS Network Interfaces]]
 
[[Category: QBUS Network Interfaces]]
 
[[Category: QBUS Network Interfaces]]

Revision as of 19:26, 15 September 2023

CH11 Unibus board

The Chaosnet UNIBUS interface (also called the CHAOS-11, CH11, QUAD and QAD; there was no generally-used name) and QBCHNI are Chaosnet network interfaces, for the UNIBUS and QBUS respectively. (The two device controllers are identical in programming terms, so they are both covered in this single article.)

They use programmed I/O to transfer data to and from buffers in main memory. They have on-board buffers (one each for inbound and outbound) which can hold one packet of data.

They are both a single quad wire-wrapped card.

Their bus address can be set via DIP switches; the default is 0764140. The network address is also set via a DIP switch.

Device registers

They have 7 registers:

Register Abbreviation Address
Command and Status Register CAICSR 764140
My address (read only) CAIMYN 764142
Write buffer (write only) CAIWBF 764142
Read buffer CAIRBF 764144
Read bit counter CAIRBC 764146
Unused   764150
Initiate transmission CAIXMT 764152
Unused   764154
Unused   764156
Load interval timer (write only) CAITIM 764160


In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in italics, and those which are write-only are shown in bold.

External links

  • CHAOS; - includes drawings and documentation
    • CHS DEFS - register declarations
    • $QUAD LOG - "Log of ChaosNet Interface Boards (quad-high, PDP-11 version)"
    • QUAD SETUP - "how to setup .. Chaosnet Interfaces"
    • QUAD ECO - "ECO to .. Change cable speed to 4 MHz"
    • QADCHS NOTE - random jottings
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