Difference between revisions of "Chaosnet interface"

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(→‎External links: Converted SUDS drawings.)
(Add Load Interval Timer Register)
 
(2 intermediate revisions by the same user not shown)
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I am not certain of this; I think cards with pins on the back did this, which is why they made card with pins on the package side. -->
 
I am not certain of this; I think cards with pins on the back did this, which is why they made card with pins on the package side. -->
  
−
Their [[bus]] [[address]] <!-- and [[interrupt vector]]s --> can be set via [[Dual Inline Package|DIP]] switches; <!-- to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. --> the default is 0764140<!-- and 0340 - looks like there are enough DIPs for the vector too, but no docs -->. The [[network address]] is also set via a DIP switch.
+
Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package|DIP]] switches; <!-- to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. --> the defaults are 0764140 and 0270. The [[network address]] is also set via a DIP switch.
  
 
==Device registers==
 
==Device registers==
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In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics'', and those which are write-only are shown in '''bold'''.  
 
In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics'', and those which are write-only are shown in '''bold'''.  
−
<!-- ===764000: Control Status Register (CSR)===
+
 
 +
===764140: Control Status Register (CSR)===
 
{{16bit-header}}
 
{{16bit-header}}
−
| colspan=2 | '''XM''' || colspan=6 | '''FUNC''' || ''CDN'' || CIE || ''RDN'' || RIE || colspan=4 | ''STAT''
+
| RDN || ''ERR'' || '''RST''' || colspan=4 | ''LSTCN'' || '''TCL''' || TDN || ''TAB'' || TEN || REN || '''RCL''' || SPY || LPBK || TIE
 
{{16bitoctal-bitout}}
 
{{16bitoctal-bitout}}
  
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! Bits !! Use
 
! Bits !! Use
 
|-
 
|-
−
| XM || Extended address bits A17 and A16
+
| RDN || Receive done
 +
|-
 +
| ERR || [[Cyclic redundancy check|CRC]] error
 +
|-
 +
| RST || I/O reset for interface
 +
|-
 +
| LSTCN || Count of messages lost
 
|-
 
|-
−
| FUNC || Command Function Code
+
| TCL || Receiver clear
 
|-
 
|-
−
| CDN || Command Done
+
| TDN || Transmitter done
 
|-
 
|-
−
| CIE || Command Done Interrupt Enable
+
| TAB || Transmit aborted by conflict
 
|-
 
|-
−
| RDN || Receive DMA Done
+
| TEN || Transmit interrupt enable
 
|-
 
|-
−
| RIE || Receive DMA Done Interrupt Enable
+
| REN || Receive interrupt enable
 
|-
 
|-
−
| STAT || Command Status Code
+
| RCL || Receiver clear
 +
|-
 +
| SPY || Accept all messages
 +
|-
 +
| LPBK || Loop back in interface
 +
|-
 +
| TIE || Timer interrupt enable<br>(was Transmitter busy)
 
|}
 
|}
  
−
#define CH_TBSY 01              /* Transmitter busy */
+
===764142: My Address Register (MYN)===
 +
{{16bit-header}}
 +
| colspan=8 | ''Subnet7 <---> Subnet0'' || colspan=8 | ''Host7 <---> Host0''
 +
{{16bitoctal-bitout}}
 +
 
 +
Read-only register.
 +
 
 +
===764142: Write Buffer Register (WBF)===
 +
{{16bit-header}}
 +
| colspan=16 | '''OutData15 <---> OutData00'''
 +
{{16bitoctal-bitout}}
  
−
#define CH_LPBK 02              /* Loop back in interface */
+
Write-only register.
−
#define CH_SPY  04              /* Spy - accept any messages */
 
  
−
#define CH_REN  010            /* Receive enable */
+
===764144: Read Buffer Register (RBF)===
  
−
#define CH_RIEN 020            /* Receive interrupt enable */
+
{{16bit-header}}
−
#define CH_TIEN 040            /* Transmit interrupt enable */
+
| colspan=16 | ''InData15 <---> InData0''
 +
{{16bitoctal-bitout}}
  
−
#define CH_ABRT 0100            /* Transmit aborted by conflict */
+
Read-only register.
  
−
#define CH_TDN  0200            /* Transmission done */
+
===764146: Read Bit Counter Register (RBC)===
  
−
#define CH_TCLR 0400            /* Transmitter clear */
+
{{16bit-header}}
 +
| colspan=4 | Unused || colspan=12 | ''BitCount11 <---> BitCount0''
 +
{{16bitoctal-bitout}}
  
−
#define CH_LC1  01000          /* Count of messages lost */
+
On the Chaosnet UNIBUS interface, a read-only register.
−
#define CH_LC2  02000
 
−
#define CH_LC3  04000
 
−
#define CH_LC4  010000
 
−
#define CH_LC  (CH_LC1 | CH_LC2 | CH_LC3 | CH_LC4)
 
  
−
#define CH_RST  020000          /* I/O reset for interface */
+
On the QBCHNI, ''writing'' the interface's network address into this register initiates transmission of a packet.
−
#define CH_CRC  040000          /* CRC error */
 
−
#define CH_RDN  0100000        /* Input done */
 
  
−
===764002: Bus Address Register (BAR)===
+
===764152: Initiate Transmission Register (XMT)===
 
{{16bit-header}}
 
{{16bit-header}}
−
| colspan=16 | '''BA15 <--- BA00'''
+
| colspan=8 | ''Subnet7 <---> Subnet0'' || colspan=8 | ''Host7 <---> Host0''
 
{{16bitoctal-bitout}}
 
{{16bitoctal-bitout}}
  
−
Write-only register.
+
On the Chaosnet UNIBUS interface, a read-only register; ''reading'' it initiates transmission of a packet. (The data returned is the interface's network address.)
−
 
 
−
===764004: Byte Count Register (BCR)===
 
  
 +
===764160: Load Interval Timer Register (TIM)===
 
{{16bit-header}}
 
{{16bit-header}}
−
| colspan=16 | '''BC15 <--- BC0'''
+
| colspan=16 | '''Timer15 <---> Timer00'''
 
{{16bitoctal-bitout}}
 
{{16bitoctal-bitout}}
  
−
Write-only register. -->
+
Write-only register.
 +
 
 
==External links ==
 
==External links ==
  

Latest revision as of 18:28, 17 September 2023

CH11 Unibus board

The Chaosnet UNIBUS interface (also called the CHAOS-11, CH11, QUAD and QAD; there was no generally-used name) and QBCHNI are Chaosnet network interfaces, for the UNIBUS and QBUS respectively. (The two device controllers are identical in programming terms, so they are both covered in this single article.)

They use programmed I/O to transfer data to and from buffers in main memory. They have on-board buffers (one each for inbound and outbound) which can hold one packet of data.

They are both a single quad wire-wrapped card.

Their bus address and interrupt vectors can be set via DIP switches; the defaults are 0764140 and 0270. The network address is also set via a DIP switch.

Device registers

They have 7 registers:

Register Abbreviation Address
Command and Status Register CAICSR 764140
My address (read only) CAIMYN 764142
Write buffer (write only) CAIWBF 764142
Read buffer CAIRBF 764144
Read bit counter CAIRBC 764146
Unused   764150
Initiate transmission CAIXMT 764152
Unused   764154
Unused   764156
Load interval timer (write only) CAITIM 764160


In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in italics, and those which are write-only are shown in bold.

764140: Control Status Register (CSR)

RDN ERR RST LSTCN TCL TDN TAB TEN REN RCL SPY LPBK TIE
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Bits are:

Bits Use
RDN Receive done
ERR CRC error
RST I/O reset for interface
LSTCN Count of messages lost
TCL Receiver clear
TDN Transmitter done
TAB Transmit aborted by conflict
TEN Transmit interrupt enable
REN Receive interrupt enable
RCL Receiver clear
SPY Accept all messages
LPBK Loop back in interface
TIE Timer interrupt enable
(was Transmitter busy)

764142: My Address Register (MYN)

Subnet7 <---> Subnet0 Host7 <---> Host0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Read-only register.

764142: Write Buffer Register (WBF)

OutData15 <---> OutData00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Write-only register.

764144: Read Buffer Register (RBF)

InData15 <---> InData0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Read-only register.

764146: Read Bit Counter Register (RBC)

Unused BitCount11 <---> BitCount0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

On the Chaosnet UNIBUS interface, a read-only register.

On the QBCHNI, writing the interface's network address into this register initiates transmission of a packet.

764152: Initiate Transmission Register (XMT)

Subnet7 <---> Subnet0 Host7 <---> Host0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

On the Chaosnet UNIBUS interface, a read-only register; reading it initiates transmission of a packet. (The data returned is the interface's network address.)

764160: Load Interval Timer Register (TIM)

Timer15 <---> Timer00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Write-only register.

External links

Retrieved from "https://gunkies.org/w/index.php?title=Chaosnet_interface&oldid=31632"