Flip-flop

A flip-flop or latch (historically, the terms were somewhat interchangeable, but in contemporary usage they refer to disjoint sets of devices) is an extremely common element in digital logic; it is a store for one bit of state.

Unlike gates, which are necessarily made out of transistors, they can be made out of gates. All involve feedback from the outputs to some of the inputs of the gates used to create them; they are thus subject to meta-stability issues.

They usually have one data or two control inputs, two data outputs (the data and its inversion, usually denoted 'Q' and 'Q-bar'), and optionally a clock input, which tells it when to store the current state of the input(s).

There are many different varieties; the chief distinction is between so-called 'transparent', and 'edge-triggered'. The former passes the input data through immediately whenever the clock input is asserted, so that the output can move up and down during that period; the latter only changes the output once, at either the rising or falling edge of the clock.

In modern terminology, the term 'flip-flop' is usually reserved for the latter, and 'latch' is used for everything else.

S-R latch

The simplest is the S-R latch (called a 'S-R flip-flop' in the early period), which consists of just two NAND or NOR gates. The output of each gate, in addition to being an output from the latch, is also connected to one of the inputs of the other gate.

With NOR gates, the other two inputs (asserted high) are 'reset' (on the gate with the Q output) and 'set' (on the other). With NAND gates, the two inputs are asserted low, not high, and the 'set' is on the gate providing the Q output.

The more complicated flip-flops are often made up of several S-R latches, along with other gates.

Latch

A latch has a single data input, and a clock input. As long as the clock is asserted, the input data is passed through to the output(s). When the clock stops being asserted, it continues to output the data that was present at that time, and the input is ignored.

D flip-flop

A D flop-flop has a single data input, and a clock input. It samples the input on either the rising or falling edge of the clock (depending on the variety). Most D flip-flops also have 'preset' and 'clear' inputs, which force the output to 1 or 0.

It is made out of pair of S-R latches, one behind the other, along with some additional gates.

J-K flip flop

A J-K flop-flop has two data/control inputs, and a clock input. It samples the inputs on either the rising or falling edge of the clock; again, most also have preset and clear inputs.

When the clock happens, with both data/control inputs low, it holds its previous state; with only J high, it sets; with only K high, it clears; with both high, it inverts its previous state.

External links

• Computer Architectures - Digital Circuits - Latches and flip-flops