Difference between revisions of "Flip-flop"
(A start - still need to add all the other types) |
m (+cat) |
||
| (9 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
| − | A '''flip-flop''' or '''latch''' is an extremely common element in digital logic; it is a store for one bit of state | + | A '''flip-flop''' or '''latch''' (historically, the terms were somewhat interchangeably, but in contemporary usage they usually refer to disjoint sets of devices) is an extremely common element in digital logic; it is a store for one bit of state. |
| − | + | Unlike [[gate]]s, which are necessarily made out of [[transistor]]s, all forms of flip-flop and latch (there are quite a few) can be made out of gates. All involve feedback, from the outputs, to some of the inputs of the gates used to create them; they are thus subject to [[meta-stability]] issues. | |
| − | + | There are many different versions, but they usually have one data or two control inputs, two data outputs (the data and its inversion, usually denoted 'Q' and 'Q-bar'), and optionally a [[clock]] input, which tells it when to store the current state of the input(s). More complex versions of most devices also have 'preset' and/or 'clear' inputs, which force the output to 1 or 0. | |
| − | + | ==Attributes== | |
| − | + | Within each of the basic types (below), there are many subtle variants, based around three main characteristics: | |
| − | + | * ''When'' does the device listen to its input - at a clock edge (and if so, which one); or during a longer period? | |
| + | * For devices which listen during an extended period, ''how'' does it do so - does it track changes in the input; or will it catch, and retain, short spikes? | ||
| + | * When does the ''output'' change - at a clock edge; when the input changes (after a [[propagation delay]], of course); etc. | ||
| − | + | Of the many different varieties, the chief grouping is 'edge-triggered', which only sample the input once, at either the rising or falling edge of the clock. In modern terminology, the term 'flip-flop' is usually reserved for this group; 'latch' is used for everything else. Edge-triggered devices are preferred in [[clocked logic]] systems. | |
| + | |||
| + | ==Types== | ||
| + | |||
| + | Names exist for several of the most common forms of flip-flop; these are mostly due to Montgomery Phister, from his book "Logical Design of Digital Computers" (John Wiley & Sons, New York, 1958). | ||
| + | |||
| + | ===S-R latch=== | ||
| + | |||
| + | The simplest is the S-R latch (called a 'S-R flip-flop' in the early period), which has only two control inputs, 'set' and 'reset' (as implied by the name). One should assert ''either'' the set or reset inputs; asserting both can drive it into a metastable state (depending on the exact timing of the de-assertion). | ||
| + | |||
| + | It usually consists of just two NAND or NOR gates. The output of each gate, in addition to being an output from the latch, is also connected to one of the inputs of the other gate. | ||
| + | |||
| + | When constructed with NOR gates, the other two inputs (asserted high) are 'reset' (on the gate with the Q output), and 'set' (on the other). With NAND gates, the two inputs are asserted low, and the 'set' is on the gate providing the Q output. | ||
| + | |||
| + | The more complicated flip-flops are often made up of several S-R latches, along with other gates. | ||
| + | |||
| + | ===Latch=== | ||
| + | |||
| + | A latch has a single data input, and a clock input. As long as the clock is asserted, the input data is passed through to the output(s); i.e. it is what is called a 'transparent' device, so that the output can move up and down during the period when the clock input is asserted. | ||
| + | |||
| + | When the clock stops being asserted, it continues to output the data that was present at the falling edge of the clock, and the input is thereafter ignored. | ||
| + | |||
| + | ===D flip-flop=== | ||
| + | |||
| + | A D flop-flop has a single data input, and a clock input. It samples the input on either the rising or falling edge of the clock depending on the variety). | ||
| + | |||
| + | It is usually constructed out of pair of S-R latches, one after the other, along with some additional gates. | ||
| + | |||
| + | ===J-K flip flop=== | ||
| + | |||
| + | A J-K flop-flop has two data/control inputs, and a clock input. When the clock is asserted, with both data/control inputs low, it holds its previous state; with only J high, it sets; with only K high, it clears; with both high, it inverts its previous state. | ||
| + | |||
| + | Several varieties exist: the earliest versions in [[74 series]] [[transistor-transistor logic|TTL]] [[integrated circuit|SSI]] listened to their inputs during the period in which the clock was asserted. Later ones, 'rising-edge triggered' and 'falling-edge triggered', sample their inputs on either the rising or falling edge of the clock. | ||
| + | |||
| + | ==External links== | ||
| + | |||
| + | * [http://www.electronicsteacher.com/computer-architectures/digital-circuits/flip-flops.php Computer Architectures - Digital Circuits - Latches and flip-flops] | ||
| + | |||
| + | [[Category: Hardware Basics]] | ||
Revision as of 06:09, 16 December 2018
A flip-flop or latch (historically, the terms were somewhat interchangeably, but in contemporary usage they usually refer to disjoint sets of devices) is an extremely common element in digital logic; it is a store for one bit of state.
Unlike gates, which are necessarily made out of transistors, all forms of flip-flop and latch (there are quite a few) can be made out of gates. All involve feedback, from the outputs, to some of the inputs of the gates used to create them; they are thus subject to meta-stability issues.
There are many different versions, but they usually have one data or two control inputs, two data outputs (the data and its inversion, usually denoted 'Q' and 'Q-bar'), and optionally a clock input, which tells it when to store the current state of the input(s). More complex versions of most devices also have 'preset' and/or 'clear' inputs, which force the output to 1 or 0.
Contents
Attributes
Within each of the basic types (below), there are many subtle variants, based around three main characteristics:
- When does the device listen to its input - at a clock edge (and if so, which one); or during a longer period?
- For devices which listen during an extended period, how does it do so - does it track changes in the input; or will it catch, and retain, short spikes?
- When does the output change - at a clock edge; when the input changes (after a propagation delay, of course); etc.
Of the many different varieties, the chief grouping is 'edge-triggered', which only sample the input once, at either the rising or falling edge of the clock. In modern terminology, the term 'flip-flop' is usually reserved for this group; 'latch' is used for everything else. Edge-triggered devices are preferred in clocked logic systems.
Types
Names exist for several of the most common forms of flip-flop; these are mostly due to Montgomery Phister, from his book "Logical Design of Digital Computers" (John Wiley & Sons, New York, 1958).
S-R latch
The simplest is the S-R latch (called a 'S-R flip-flop' in the early period), which has only two control inputs, 'set' and 'reset' (as implied by the name). One should assert either the set or reset inputs; asserting both can drive it into a metastable state (depending on the exact timing of the de-assertion).
It usually consists of just two NAND or NOR gates. The output of each gate, in addition to being an output from the latch, is also connected to one of the inputs of the other gate.
When constructed with NOR gates, the other two inputs (asserted high) are 'reset' (on the gate with the Q output), and 'set' (on the other). With NAND gates, the two inputs are asserted low, and the 'set' is on the gate providing the Q output.
The more complicated flip-flops are often made up of several S-R latches, along with other gates.
Latch
A latch has a single data input, and a clock input. As long as the clock is asserted, the input data is passed through to the output(s); i.e. it is what is called a 'transparent' device, so that the output can move up and down during the period when the clock input is asserted.
When the clock stops being asserted, it continues to output the data that was present at the falling edge of the clock, and the input is thereafter ignored.
D flip-flop
A D flop-flop has a single data input, and a clock input. It samples the input on either the rising or falling edge of the clock depending on the variety).
It is usually constructed out of pair of S-R latches, one after the other, along with some additional gates.
J-K flip flop
A J-K flop-flop has two data/control inputs, and a clock input. When the clock is asserted, with both data/control inputs low, it holds its previous state; with only J high, it sets; with only K high, it clears; with both high, it inverts its previous state.
Several varieties exist: the earliest versions in 74 series TTL SSI listened to their inputs during the period in which the clock was asserted. Later ones, 'rising-edge triggered' and 'falling-edge triggered', sample their inputs on either the rising or falling edge of the clock.
