Difference between revisions of "Honeywell 6000 series"

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The [[architecture]] of the GE and Honeywell series was the same: a [[tightly-coupled]] [[multi-processor]], with all the [[CPU]]s sharing access to a collection of [[multi-port memory]] units. All used 36-bit words, and almost identical [[instruction set]]s.
 
The [[architecture]] of the GE and Honeywell series was the same: a [[tightly-coupled]] [[multi-processor]], with all the [[CPU]]s sharing access to a collection of [[multi-port memory]] units. All used 36-bit words, and almost identical [[instruction set]]s.
  
Most 6000 series machines ran [[GECOS]] (General Electric Comprehensive Operating Supervisor); later GCOS - General Comprehensive Operating System).
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Most 6000 series machines ran [[GCOS]] (General Comprehensive Operating System), an evolution of the earlier GECOS (General Electric Comprehensive Operating Supervisor).  
  
Some models in the line had the additional hardware - the 'Appending Unit' (APU) - needed to implement the [[single-level memory]] used by [[Multics]], which ran only on some models of the GE 600 and Honeywell 6000 series lines.
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Some models in the line had the additional hardware - the 'Appending Unit' (APU) - needed to implement the [[single-level memory]] used by Multics, which ran only on some models of the GE 600 and Honeywell 6000 series lines.
  
 
==System organization==
 
==System organization==
  
Systems were constructed of 3 main kinds of units: CPUs, memories (System Control Units, or SCUs), and I/O controllers. CPUs were connected to SCUs (with a separate cable from each CPU to each SCU); I/O controllers were alo conencted to SCUs (again, a separate cable for each pairing).
+
Systems were constructed of 3 main kinds of units: CPUs, memories (technically, System Control Units, or SCUs), and I/O controllers. CPUs were connected to SCUs (with a separate cable from each CPU to each SCU); I/O controllers were alo conencted to SCUs (again, a separate cable for each pairing), and could interrupt the CPUs via the SCUs.
  
 
The memories were an integral part of the SCU. The first-generation SCUs, with [[core memory]], had a maximum capacity of 256KW; later ones, with [[DRAM]], could hold considerably more.
 
The memories were an integral part of the SCU. The first-generation SCUs, with [[core memory]], had a maximum capacity of 256KW; later ones, with [[DRAM]], could hold considerably more.
  
The first generation of I/O controllers was the IOM (Input/Output Multiplexer); these were later replaced by the IMU (Information Multiplexer Unit), which was programmable. All [[disk]] drives, tape drives, etc were connected to the I/O controllers. Serial lines, etc, were connected to a Front End Processor ('FNP', in Multics jargon), which were connected to I/O conrollers.
+
The first generation of I/O controllers was the IOM (Input/Output Multiplexer); these were later replaced by the IMU (Information Multiplexer Unit), which was programmable. All [[disk]] drives, tape drives, etc were connected to the I/O controllers.
  
The maximum numbers of CPUs, etc which could be connected to one system varied from generation to generation (below), but 6-CPU systems did exist. (The practical limit was caused by most SCUs having a maximum of 8 ports; each CPU used one port, as did each I/O controller.)
+
Serial lines, etc, were connected to a Front End Processor ('FNP', in Multics jargon), which were connected to I/O conrollers; 'unit record' devices such as card readers, etc, were attached to a 'unit record proceasor', likewise attached to an I/I controller.
 +
 
 +
The maximum numbers of CPUs, etc which could be connected to one system varied from generation to generation (below), but 6-CPU Multics systems did exist. (The practical limit was caused by most SCUs having a maximum of 8 ports; each CPU used one port, as did each I/O controller.)
  
 
==Generations==
 
==Generations==
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===Level 66/DPS and Level 68/DPS===
 
===Level 66/DPS and Level 68/DPS===
  
A 1977 re-naming of the line (no hardware changes); the Level 66's were GCOS, and the Level 68's were Multics. The names DPS-68 (and presumably DPS-60, to match) were also used.
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A 1977 re-naming of the line (no hardware changes); the Level 66's were GCOS, and the Level 68's were Multics. The names DPS-68 (and presumably DPS-66, to match) were also used.
  
 
===DPS-8===
 
===DPS-8===
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A lightly re-engineered version (about 1/3 of the boards were idenical; 1/3, or slightly more, were lightly modified; the rest were totally different) released in 1979. The extensive 'lights and switches' control panels of the earlier machine were replaced with a console terminal, driven by a [[micro-computer]], the 'maintenance processor'.
 
A lightly re-engineered version (about 1/3 of the boards were idenical; 1/3, or slightly more, were lightly modified; the rest were totally different) released in 1979. The extensive 'lights and switches' control panels of the earlier machine were replaced with a console terminal, driven by a [[micro-computer]], the 'maintenance processor'.
  
The low-end GCOS models - the DPS8/20 and DPS8/44 - used [[micro-code]].
+
DPS-8 systems supported a maximum of 4 SCU's, although each SCU could provide up to 16 Mbytes of memory, for 64 Mbytes total. A maximum of two I/O Controllers (albeit each considerably more powerful than earlier versions) were supported.
 +
 
 +
The low-end GCOS models - the DPS8/20 and DPS8/44 - used [[micro-code]], instead of being hard-wired (as all the other 6000 series processors were).
  
 
The Multics units were the DPS-8/M models - the DPS8/52M, DPS8/62M and DPS-8/70M. Apparently all three used the same hardware, but the two lower-performance one has delays inserted into their clocks. The /70M came with an 8KW [[cache]]; later, an optional 32KW cache was introduced. The performance with the 8KW cache was about 1.68 times that of the 6180; with the 32KW cache, about 1.85.
 
The Multics units were the DPS-8/M models - the DPS8/52M, DPS8/62M and DPS-8/70M. Apparently all three used the same hardware, but the two lower-performance one has delays inserted into their clocks. The /70M came with an 8KW [[cache]]; later, an optional 32KW cache was introduced. The performance with the 8KW cache was about 1.68 times that of the 6180; with the 32KW cache, about 1.85.

Revision as of 17:48, 17 September 2017

The Honeywell 6000 series was a long-lived family of mainframes, in production from 1970 to 1989. They are probably best-known now for being the machines that Multics ran on for most of its life, after the initial stages.

They were descendants of the GE 600 series family; after GE's computer business was sold to Honeywell in 1966, the 6000 series were Honeywell's replacements. They used integrated circuits and larger printed circuit boards, unlike the older (and obsolescent) discrete transistor GE machines.

The architecture of the GE and Honeywell series was the same: a tightly-coupled multi-processor, with all the CPUs sharing access to a collection of multi-port memory units. All used 36-bit words, and almost identical instruction sets.

Most 6000 series machines ran GCOS (General Comprehensive Operating System), an evolution of the earlier GECOS (General Electric Comprehensive Operating Supervisor).

Some models in the line had the additional hardware - the 'Appending Unit' (APU) - needed to implement the single-level memory used by Multics, which ran only on some models of the GE 600 and Honeywell 6000 series lines.

System organization

Systems were constructed of 3 main kinds of units: CPUs, memories (technically, System Control Units, or SCUs), and I/O controllers. CPUs were connected to SCUs (with a separate cable from each CPU to each SCU); I/O controllers were alo conencted to SCUs (again, a separate cable for each pairing), and could interrupt the CPUs via the SCUs.

The memories were an integral part of the SCU. The first-generation SCUs, with core memory, had a maximum capacity of 256KW; later ones, with DRAM, could hold considerably more.

The first generation of I/O controllers was the IOM (Input/Output Multiplexer); these were later replaced by the IMU (Information Multiplexer Unit), which was programmable. All disk drives, tape drives, etc were connected to the I/O controllers.

Serial lines, etc, were connected to a Front End Processor ('FNP', in Multics jargon), which were connected to I/O conrollers; 'unit record' devices such as card readers, etc, were attached to a 'unit record proceasor', likewise attached to an I/I controller.

The maximum numbers of CPUs, etc which could be connected to one system varied from generation to generation (below), but 6-CPU Multics systems did exist. (The practical limit was caused by most SCUs having a maximum of 8 ports; each CPU used one port, as did each I/O controller.)

Generations

There were several generations of 6000 series machines, although many of the different names were more marketing gloss than significant changes. Performance improvements between the various generations were minimal.

6000 Series

The first incarnation; the CPU speed was about 1 MIPS. The GCOS machines were the models 6030, 6060, 6050, 6060, and 6070. (Mention is made in one place of a 6090.) In 1973 the model 6180, which supported Multics, was added.

Series 60, Level 66 and Level 68

These were re-badged versions of the 6000 series, in slightly lower cabinets, introduced in 1975; they did, however, offer larger memory units. The incandescent light bulbs in the control panels were replaced by LEDs.

The Level 66 machines were GCOS, and Level 68 were Multics; the specific Multics models were the 68/60 and 68/80, which were identical except that in the former, the cache was disabled.

Level 66/DPS and Level 68/DPS

A 1977 re-naming of the line (no hardware changes); the Level 66's were GCOS, and the Level 68's were Multics. The names DPS-68 (and presumably DPS-66, to match) were also used.

DPS-8

A lightly re-engineered version (about 1/3 of the boards were idenical; 1/3, or slightly more, were lightly modified; the rest were totally different) released in 1979. The extensive 'lights and switches' control panels of the earlier machine were replaced with a console terminal, driven by a micro-computer, the 'maintenance processor'.

DPS-8 systems supported a maximum of 4 SCU's, although each SCU could provide up to 16 Mbytes of memory, for 64 Mbytes total. A maximum of two I/O Controllers (albeit each considerably more powerful than earlier versions) were supported.

The low-end GCOS models - the DPS8/20 and DPS8/44 - used micro-code, instead of being hard-wired (as all the other 6000 series processors were).

The Multics units were the DPS-8/M models - the DPS8/52M, DPS8/62M and DPS-8/70M. Apparently all three used the same hardware, but the two lower-performance one has delays inserted into their clocks. The /70M came with an 8KW cache; later, an optional 32KW cache was introduced. The performance with the 8KW cache was about 1.68 times that of the 6180; with the 32KW cache, about 1.85.