Interlan NI1010A/NI2010A Ethernet interface
The Interlan NI1010A and NI2010A are Ethernet network interfaces for the UNIBUS and QBUS respectively. (The two device controllers are very similar in programming terms, so they are covered in this single article.)
They use DMA to transfer data to and from buffers in main memory. They have an on-board FIFO buffer which can hold up to 13.5K bytes of inbound data; the host can pre-queue up to 16 input buffer DMA requests.
The NI1010A is a single hex board. The NI2010A is a quad board, with a large daughter card; they take two slots, but only the mother card has edge fingers to plug in. A grant continuity card is supplied, to plug into the second slot, to carry the QBUS' bus grant lines through the slot.
There are two interrupt vectors; 0xx0 for 'Receive DMA done' and 0xx4 for 'Command done'.
The NI1010A controller includes 3 registers, and the NI2010A 4 (the optional extra register is needed because of the larger address space on the QBUS):
|Control Status Register||CSR||764000|
|Bus Address Register||BAR||764002|
|Byte Count Register||BCR||764004|
|Bus Address Extension Register
The Bus Address Extension Register was enabled by a switch; i.e. the NI2010A could be set to be identical, programmatically, to the NI1010A, at the cost of not being able to use more than 256KB of main memory.
In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in italics, and those which are write-only are shown in bold.
764000: Control Status Register (CSR)
|XM||Extended address bits A17 and A16|
|FUNC||Command Function Code|
|CIE||Command Done Interrupt Enable|
|RDN||Receive DMA Done|
|RIE||Receive DMA Done Interrupt Enable|
|STAT||Command Status Code|
Reading the CSR clears the two 'done' bits. The extended address bits are disabled on the NI2010A when the BER is enabled.
Command function codes are:
|02||Set internal loopback|
|04||Set promiscuous receive|
|05||Clear promiscuous receive|
|15||Set insert source address|
|16||Clear insert source address|
|17||Set network address to default|
|20||Set receive all multicast|
|21||Clear receive all multicast|
|22||Perform loopback test|
|23||Perform collision detection test|
|30||Report and clear stats|
|31||Report collision delay times|
|40||Supply receive buffer|
|50||Load transmit data|
|51||Load transmit data and send|
|52||Load group address(es)|
|53||Delete group address(es)|
|54||Load physical network address|
|60||Flush input buffer queue|
Command status codes are:
|01||Success with retries|
|05||Buffer size exceeded|
|06||Frame too small|
|12||Buffer alignment error|
|13||No heartbeat detected|
|14||No CRC error occurred|
|15||Inappropriate CRC error|
|16||Last data byte not received|
764002: Bus Address Register (BAR)
|BA15 <---> BA00|
764004: Byte Count Register (BCR)
|BC15 <---> BC0|
7764006: Bus Address Extension Register (BER)
|Unused||BA21 <---> BA16|
Note: This register is present in the NI2010A only.