Difference between revisions of "KA10"
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| + | [[Image:KA10 mod end.jpg|150px|thumb|right|B-series FLIP CHIP used in the KA10 [[CPU]]]] | ||
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The '''KA10''' was the first generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of discrete transistors, on [[DEC card form factor|short single]] [[FLIP CHIP]] cards. | The '''KA10''' was the first generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of discrete transistors, on [[DEC card form factor|short single]] [[FLIP CHIP]] cards. | ||
It was used in the first [[DECsystem-10]] models, running [[TOPS-10]]. It was also the machine on which the [[ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[paging]] (the KA10 normally only provided 'base and bounds' memory management hardware). | It was used in the first [[DECsystem-10]] models, running [[TOPS-10]]. It was also the machine on which the [[ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[paging]] (the KA10 normally only provided 'base and bounds' memory management hardware). | ||
Revision as of 21:38, 29 July 2017
B-series FLIP CHIP used in the KA10 CPU
The KA10 was the first generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was built out of discrete transistors, on short single FLIP CHIP cards.
It was used in the first DECsystem-10 models, running TOPS-10. It was also the machine on which the ITS and TENEX operating systems were developed, after the machines were modified to provide paging (the KA10 normally only provided 'base and bounds' memory management hardware).
