Difference between revisions of "KB11-A CPU"

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which comprise the KT11-C.
 
which comprise the KT11-C.
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==Parity==
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An apparent 'tombstone' from an early specification of the KB11-A can be found in the ''pdp-11/45 processsor handbook'' (1972 and 1973 editions) where a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". One bit in each register is 'Halt Enable': "[when] set, the machine will execute a [[halt]] if a parity error occurs". (When clear, the machine will [[trap]] to 4!) They also provided [[UNIBUS parity#Second_version|detailed parity control]].
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It is not known whether these registers were actually implemented in an early version of the KB11-A, and if so, exactly what functionality was included. A slightly later very early version, which actually made it into the field, does not have these registers, but does halt the CPU on a parity error.
  
 
== Documentation ==
 
== Documentation ==

Revision as of 21:46, 22 January 2019

The KB11-A CPU is the earlier CPU for the PDP-11/45. The optional FP11-B Floating-Point Processor and KT11-C Memory Management Unit of the PDP-11/45 plugged into the CPU's backplane.

In addition to main memory on the UNIBUS, the KB11-A could also use the special high-speed MS11 Semiconductor Memory System, specific to the PDP-11/45, which plugged into a special bus, the Fastbus, which was also part of the CPU's backplane.

The KB11-A was the first of a series of PDP-11 CPUs which were modified versions of this design.

Boards

The KB11-A board set included:

  • M8100 Data and Address Paths
  • M8101 General Register and Control
  • M8102 Instruction Register and Decode
  • M8103 ROM and ROM Control
  • M8104 Processor Data and UNIBUS Registers
  • M8105 Timing and Miscellaneous Control
  • M8106 UNIBUS and Console Control
  • M8109 Timing Generator

In addition, the CPU includes either:

  • M8116 Segmentation Jumper Board

used when the KT11-C Memory Management Unit is not present, or:

  • M8107 Segmentation Address Paths
  • M8108 Segmentation Status Registers

which comprise the KT11-C.

Parity

An apparent 'tombstone' from an early specification of the KB11-A can be found in the pdp-11/45 processsor handbook (1972 and 1973 editions) where a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". One bit in each register is 'Halt Enable': "[when] set, the machine will execute a halt if a parity error occurs". (When clear, the machine will trap to 4!) They also provided detailed parity control.

It is not known whether these registers were actually implemented in an early version of the KB11-A, and if so, exactly what functionality was included. A slightly later very early version, which actually made it into the field, does not have these registers, but does halt the CPU on a parity error.

Documentation

See also