Difference between revisions of "KL10"

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| memory speed = 1.0 μsec (initial [[core memory]]), 500 nsec (later [[MOS]] [[main memory]])   
 
| memory speed = 1.0 μsec (initial [[core memory]]), 500 nsec (later [[MOS]] [[main memory]])   
 
| memory mgmt = [[paging]], 512-word pages
 
| memory mgmt = [[paging]], 512-word pages
| operating system = [[TOPS-10]], [[TOPS-20]], [[ITS]], [[TENEX]]
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| operating system = [[TOPS-10]], [[TOPS-20]], [[ITS]], [[WAITS]], [[TENEX]]
 
| predecessor = [[KI10]]
 
| predecessor = [[KI10]]
 
| successor = none
 
| successor = none
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}}
 
}}
  
The '''KL10''' was the third generation of [[PDP-10]] processors. It was built out of [[ECL]], on [[DEC card form factor|hex]] cards.
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The '''KL10''' was the third generation of [[PDP-10]] processors. It was built out of [[ECL]], on [[DEC card form factor|hex]] cards. It was the first [[Microcode|microprogrammed]] PDP-10 processor; the design was inspired by [[Foonly]]'s F-1
  
 
It was used in the [[DECsystem-10]] models 1080 and 1090 systems (with an external memory bus, compatible with the earlier [[KA10]] and [[KI10]]), and the [[DECSYSTEM-20]] 20xx systems (with an internal memory bus).
 
It was used in the [[DECsystem-10]] models 1080 and 1090 systems (with an external memory bus, compatible with the earlier [[KA10]] and [[KI10]]), and the [[DECSYSTEM-20]] 20xx systems (with an internal memory bus).
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Like its predecessor, the KI10, it was initially released in a single-[[processor]] version; a two-CPU version was released later.
 
Like its predecessor, the KI10, it was initially released in a single-[[processor]] version; a two-CPU version was released later.
  
There was a single KL10 [[ITS]] machine, MIT-MC.  It was later renamed to MX and was shut down in 1988.
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There was a single KL10 [[ITS]] machine, MIT-MC.  It was later renamed to MX and was shut down in 1988.  There was also a KL10 in the Stanford [[WAITS]] system.
  
 
==External Links==
 
==External Links==

Revision as of 07:26, 15 December 2017


KL10
Manufacturer: Digital Equipment Corporation
Architecture: PDP-10
Year Design Started: January, 1972
Year First Shipped: June, 1975
Form Factor: mainframe
Word Size: 36 bits
Logic Type: ECL ICs
Design Type: clocked synchronous, microcoded
Microword Width: 80
Microcode Length: 1280 (Model A)
2K (Model B)
Clock Speed: 500 nsec
Cache Size: 2K words
Memory Speed: 1.0 μsec (initial core memory), 500 nsec (later MOS main memory)
Physical Address Size: 22 bits
Virtual Address Size: 18 bits (Model A and B)
23 bits (Model E)
Memory Management: paging, 512-word pages
Operating System: TOPS-10, TOPS-20, ITS, WAITS, TENEX
Predecessor(s): KI10
Successor(s): none
Price: US$250K (CPU), US$600K-1.2M (system)


The KL10 was the third generation of PDP-10 processors. It was built out of ECL, on hex cards. It was the first microprogrammed PDP-10 processor; the design was inspired by Foonly's F-1

It was used in the DECsystem-10 models 1080 and 1090 systems (with an external memory bus, compatible with the earlier KA10 and KI10), and the DECSYSTEM-20 20xx systems (with an internal memory bus).

Like its predecessor, the KI10, it was initially released in a single-processor version; a two-CPU version was released later.

There was a single KL10 ITS machine, MIT-MC. It was later renamed to MX and was shut down in 1988. There was also a KL10 in the Stanford WAITS system.

External Links