Difference between revisions of "LSI-11 chip set"

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The '''LSI-11 chip set''' [[Central Processing Unit|CPU]] [[integrated circuit|chip]] set is used in the [[LSI-11 CPUs]] - the original [[LSI-11]], and the later [[LSI-11/2]]. It is the Western Digital WD16/CP1600 (alternative designations); Western Digital later turned this into a product which was used in other systems.
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The '''LSI-11 chip set''' [[Central Processing Unit|CPU]] [[integrated circuit|chip]] set is used in the [[LSI-11 CPUs]] - the original [[LSI-11]], and the later [[LSI-11/2]].
  
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==ODT==
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It is the Western Digital WD16/CP1600 (alternative designations); Western Digital later turned this into a product which was used in other systems.
  
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The LSI-11's were the first PDP-11 models to not have a [[front panel]] to control them; instead, as a cost-reduction measure, the main [[asynchronous serial line|serial line]] is used as a operating console, using the [[QBUS CPU ODT|ODT functionality]].
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==Chips==
 +
 
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The chip set consists of a [[data path]] chip, a control chip, and two or three [[microcode]] [[Read-only memory|ROMs]] (each holding 512 microwords, which are 22 bits wide). (The microcode is thus more 'vertical' than 'horizontal'.)
 +
 
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The data path chip contains data paths, [[register]]s, and logic to perform [[micro-instruction]]s. The control chip contains micro-instruction sequencing, and control for the QBUS.
  
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Note that ODT will not function correctly in the LSI-11s unless there is [[main memory]] on the [[QBUS]]. The reason for this restriction is unknown: the [[KDF11 CPUs]] and [[KDJ11 CPUs]], which also use ODT, do not have this limitation; e.g. a system consisting only of a [[KDF11-A CPU]] and a serial console will run ODT.
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The uROMs all have the same pinout, and are wired in parallel, so they can be placed in any of the three uROM positions. The first two uROMs contain the basic [[PDP-11]] [[instruction set]]; the third uROM is optional, and a number of different choices are available.
  
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==Chips==
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One is the [[KEV11-A floating point|KEV11-A]], for the [[PDP-11 Extended Instruction Set|EIS]]/[[FIS floating point|FIS]] [[instruction]]s; the [[KEV11-B Extended Instruction Set|KEV11-B]] provides EIS without FIS; the [[KEV11-C Commercial Instruction Set‎|KEV11-C]] provides a subset of the PDP-11 [[PDP-11 Commercial Instruction Set|CIS]] (it also apparently includes the EIS, but not the FIS).
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Some versions of the CPU boards also support the optional [[KUV11 Writeable Control Store]].
  
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The chip set consists of a [[data path]] chip, a control chip, and two or three [[microcode]] [[Read-only memory|ROMs]] (each holding 512 words which are 22 bits wide). (The microcode is thus more 'vertical' than 'horizontal'.)
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===Internal details===
  
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The data path chip contains data paths, [[register]]s, and logic to perform [[micro-instruction]]s; it includes a register file, the [[Arithmetic logic unit|ALU]], condition flags logic, and a data port which gives access to the [[QBUS]]' data/[[address]] lines.
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The data path chip includes a [[register file]] and the [[Arithmetic logic unit|ALU]]; all are 8 bits wide (so PDP-11 word operations two [[microcycle]]s). The register file contains 26 entries (paired into 16-bit composites).
  
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The control chip contains micro-instruction sequencing, and control for the data port; it includes a 'programmable translation array', which decodes [[macro-instruction]]s to produce microcode addresses, the 'location counter' (micro-[[program counter]]), the 'return register' (microcode [[subroutine]] return), and [[interrupt]] logic.
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5 pairs are directly addressable from the microcode, 6 pairs an only be addressed indirectly (via a 3-bit internal register, loadable from the [[PDP-11 architecture#Operands|register fields]] ), and 2 pairs support both:
  
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The uROMs all have the same pinout, and are wired in parallel, so they can be placed in any of the three uROM positions. The first two uROMs contain the basic [[PDP-11]] [[instruction set]]; the third uROM is optional, and a number of different choices are available.
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{| class="wikitable"
 +
! Registers !! Directly !! Indirectly !! Use
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|-
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| 0-1 ||   || x || R0
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|-
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| 2-3 ||   || x || R1
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|-
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| 4-5 ||   || x || R2
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|-
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| 6-7 ||   || x || R3
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|-
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| 10-11 ||   || x || R4
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|-
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| 12-13 ||   || x || R5
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|-
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| 14-15 || x || x || R6 ([[Stack Pointer|SP]])
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|-
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| 16-17 || x || x || R7 ([[Program Counter|PC]])
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|-
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| 20-21 || x ||   || [[Instruction Register|IR]]
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|-
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| 22-23 || x ||   || [[Bus Address Register|BAR]]
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|-
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| 24-25 || x ||   || Source
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|-
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| 26-27 || x ||   || Destination
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|-
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| 30-31 || x ||   || [[Processor Status Word|PS]]
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|}
  
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One is the [[KEV11-A floating point|KEV11-A]], for the [[PDP-11 Extended Instruction Set|EIS]]/[[FIS floating point|FIS]] instructions; the [[KEV11-B Extended Instruction Set|KEV11-B]] provides EIS without FIS; the [[KEV11-C Commercial Instruction Set‎|KEV11-C]] provides a subset of the PDP-11 [[PDP-11 Commercial Instruction Set|CIS]] (it also apparently includes the EIS, but not the FIS).
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The chip also contains [[condition codes]] logic, and a data port which gives access to the [[QBUS]]' data/[[address]] lines.
  
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Some verions of the CPU boards also support the optional [[KUV11 Writeable Control Store]].
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The control chip contains control for the data port; it includes a 'programmable translation array', which decodes [[macro-instruction]]s to produce microcode [[address]]es, the 11-bit 'location counter' (micro-program counter), the 'return register' (microcode [[subroutine]] return), and [[interrupt]] logic.
  
 
==Chip variants==
 
==Chip variants==
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There are a number of variants of all the various uROM chips in the base set; it is not known if all variants are completely inter-operable (i.e. any revision of any chip can be replaced with any other, and have the machine still work), so combinations will be listed.
 
There are a number of variants of all the various uROM chips in the base set; it is not known if all variants are completely inter-operable (i.e. any revision of any chip can be replaced with any other, and have the machine still work), so combinations will be listed.
  
−
Chip numbers of the form 23-xxxxx-rr, etc are DEC part numbers (where 'rr' seems to represent a revision number - 0, if not given); the corresponding Western Digital numbers are xxxxy, etc (where the 'x's are digits, and the 'y' a letter).
+
Chip numbers of the form 23-xxxxx-rr, etc are [[DEC part number]]s (where 'rr' seems to represent a revision number - 0, if not given); the corresponding Western Digital numbers are xxxxy, etc (where the 'x's are digits, and the 'y' a letter).
  
 
The Data Path chip is a 1611H (various DEC part numbers), and the Control chip is a 2007C (ditto); the uROM chips are all 30xxy.
 
The Data Path chip is a 1611H (various DEC part numbers), and the Control chip is a 2007C (ditto); the uROM chips are all 30xxy.
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The 3010D contains uROM addresses 0x000-0x1ff, and the 3007D 23-002B5 contains 0x200-0x3ff.
 
The 3010D contains uROM addresses 0x000-0x1ff, and the 3007D 23-002B5 contains 0x200-0x3ff.
  
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==Links==
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==External links==
  
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* Mark J. Sebern, [http://gordonbell.azurewebsites.net/Computer_Engineering/00000125.htm A Minicomputer-Compatible Microcomputer System: The DEC LSI-11], in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design'', Digital Press, Bedford, 1978
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* [http://www.bitsavers.org/pdf/dec/pdp11/1103/Titelbaum_LSI-11_1975.pdf The LSI-11 - A System Microcomputer]
 +
* [http://www.bitsavers.org/pdf/dec/pdp11/1103/EK-LSI11-TM-002.pdf LSI-11, PDP-11/03 user's manual] (EK-LSI11-TM-002)
 +
* [http://web.frainresearch.org:8080/projects/pdp-11/lsi-11.php LSI-11 Processors]
 
* [https://github.com/brouhaha/cp16dis Microcode disassembler]
 
* [https://github.com/brouhaha/cp16dis Microcode disassembler]
 
* [https://en.wikichip.org/wiki/dec/lsi-11 WikiChip LSI-11]
 
* [https://en.wikichip.org/wiki/dec/lsi-11 WikiChip LSI-11]
 +
* [https://www.cpushack.com/2017/11/22/cpu-of-the-day-dec-lsi-11-chipset/ CPU of the Day: DEC LSI-11 Chipset]
 
* [http://www.brouhaha.com/~eric/retrocomputing/wd/microengine/microcode/ Western Digital WD9000 Pascal Microengine Microcode]
 
* [http://www.brouhaha.com/~eric/retrocomputing/wd/microengine/microcode/ Western Digital WD9000 Pascal Microengine Microcode]
  
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[[Category: PDP-11 Processors]]
 
[[Category: PDP-11 Processors]]
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[[Category: QBUS Processors]]
 

Latest revision as of 22:42, 20 December 2023

The LSI-11 chip set CPU chip set is used in the LSI-11 CPUs - the original LSI-11, and the later LSI-11/2.

It is the Western Digital WD16/CP1600 (alternative designations); Western Digital later turned this into a product which was used in other systems.

Chips

The chip set consists of a data path chip, a control chip, and two or three microcode ROMs (each holding 512 microwords, which are 22 bits wide). (The microcode is thus more 'vertical' than 'horizontal'.)

The data path chip contains data paths, registers, and logic to perform micro-instructions. The control chip contains micro-instruction sequencing, and control for the QBUS.

The uROMs all have the same pinout, and are wired in parallel, so they can be placed in any of the three uROM positions. The first two uROMs contain the basic PDP-11 instruction set; the third uROM is optional, and a number of different choices are available.

One is the KEV11-A, for the EIS/FIS instructions; the KEV11-B provides EIS without FIS; the KEV11-C provides a subset of the PDP-11 CIS (it also apparently includes the EIS, but not the FIS).

Some versions of the CPU boards also support the optional KUV11 Writeable Control Store.

Internal details

The data path chip includes a register file and the ALU; all are 8 bits wide (so PDP-11 word operations two microcycles). The register file contains 26 entries (paired into 16-bit composites).

5 pairs are directly addressable from the microcode, 6 pairs an only be addressed indirectly (via a 3-bit internal register, loadable from the register fields ), and 2 pairs support both:

Registers Directly Indirectly Use
0-1   x R0
2-3   x R1
4-5   x R2
6-7   x R3
10-11   x R4
12-13   x R5
14-15 x x R6 (SP)
16-17 x x R7 (PC)
20-21 x   IR
22-23 x   BAR
24-25 x   Source
26-27 x   Destination
30-31 x   PS

The chip also contains condition codes logic, and a data port which gives access to the QBUS' data/address lines.

The control chip contains control for the data port; it includes a 'programmable translation array', which decodes macro-instructions to produce microcode addresses, the 11-bit 'location counter' (micro-program counter), the 'return register' (microcode subroutine return), and interrupt logic.

Chip variants

There are a number of variants of all the various uROM chips in the base set; it is not known if all variants are completely inter-operable (i.e. any revision of any chip can be replaced with any other, and have the machine still work), so combinations will be listed.

Chip numbers of the form 23-xxxxx-rr, etc are DEC part numbers (where 'rr' seems to represent a revision number - 0, if not given); the corresponding Western Digital numbers are xxxxy, etc (where the 'x's are digits, and the 'y' a letter).

The Data Path chip is a 1611H (various DEC part numbers), and the Control chip is a 2007C (ditto); the uROM chips are all 30xxy.

The following sets (Data, Control, uROMs) have been observed (the first three on LSI-11/2 cards):

  • 1611H 21-11549-01, 2007C 23-002C4, 3010A 23-001B5, 3007D 23-002B5
  • 1611H 21-16890, 2007C 23-002C4, 3010D 23-001B5, 3007D 23-007B5
  • 1611H 21-16890, 2007C 23-003C4, 3010D 23-008B5, 3007D 23-007B5
  • unknown, unknown, 3010D 23-001B5, 3007D 23-002B5

The 3010D contains uROM addresses 0x000-0x1ff, and the 3007D 23-002B5 contains 0x200-0x3ff.

External links


v • d • e PDP-11 Computers and Peripherals
UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70
PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94

QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93

QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E

Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI

Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management

UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U

Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11

Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11

CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B

Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store

Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P

More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS

PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150   CTI PDP-11s - PRO-325 • PRO-350 • PRO-380

Clones: CM 1420 • SM 1420

Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences

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