Difference between revisions of "LSI-11 chip set"

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The LSI-11's were the first PDP-11 models to not have a [[front panel]] to control them; instead, as a cost-reduction measure, when the CPU is [[halt]]ed, specialized [[microcode]] used the main [[asynchronous serial line|serial line]] as a operating console. The command set is named '''Octal Debugging Technique (ODT)'''; there are commands to read and write [[main memory]], start the CPU, etc.
 
The LSI-11's were the first PDP-11 models to not have a [[front panel]] to control them; instead, as a cost-reduction measure, when the CPU is [[halt]]ed, specialized [[microcode]] used the main [[asynchronous serial line|serial line]] as a operating console. The command set is named '''Octal Debugging Technique (ODT)'''; there are commands to read and write [[main memory]], start the CPU, etc.
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Note that ODT will not function correctly unless there is [[main memory]] on the [[QBUS]]. The reason for this restriction is unknown: the [[KDF11 CPUs]], such as the [[KDF11-A CPU]], which also use ODT do not have this limitation; a system consisting only of a KDF11-A and a serial console will run ODT.
  
 
The main serial interface is normally configured so that when the CPU is running, sending a [[asynchronous serial line|break]] on the console serial line halts the CPU.
 
The main serial interface is normally configured so that when the CPU is running, sending a [[asynchronous serial line|break]] on the console serial line halts the CPU.

Latest revision as of 02:54, 8 June 2019

The LSI-11 chip set CPU chip set is used in both LSI-11 models - the original LSI-11, and the later LSI-11/2. It is the Western Digital WD16/CP1600 (alternative designations); Western Digital later turned this into a product which was used in other systems.

ODT

The LSI-11's were the first PDP-11 models to not have a front panel to control them; instead, as a cost-reduction measure, when the CPU is halted, specialized microcode used the main serial line as a operating console. The command set is named Octal Debugging Technique (ODT); there are commands to read and write main memory, start the CPU, etc.

Note that ODT will not function correctly unless there is main memory on the QBUS. The reason for this restriction is unknown: the KDF11 CPUs, such as the KDF11-A CPU, which also use ODT do not have this limitation; a system consisting only of a KDF11-A and a serial console will run ODT.

The main serial interface is normally configured so that when the CPU is running, sending a break on the console serial line halts the CPU.

Chips

The chip set consists of a data path chip, a control chip, and two or three microcode ROMs (each holding 512 words which are 22 bits wide). (The microcode is thus more 'vertical' than 'horizontal'.)

The data path chip contains data paths, registers, and logic to perform micro-instructions; it includes a register file, the ALU, condition flags logic, and a data port which gives access to the QBUS' data/address lines.

The control chip contains micro-instruction sequencing, and control for the data port; it includes a 'programmable translation array', which decodes macro-instructions to produce microcode addresses, the 'location counter' (micro-program counter), the 'return register' (microcode subroutine return), and interrupt logic.

The uROMs all have the same pinout, and are wired in parallel, so they can be placed in any of the three uROM positions. The first two uROMs contain the basic PDP-11 instruction set; the third uROM is optional, and a number of different choices are available.

One is the KEV11-A, for the EIS/FIS instructions; the KEV11-B provides EIS without FIS; the KEV11-C provides a subset of the PDP-11 CIS (it also apparently includes the EIS, but not the FIS).

Some verions of the CPU boards also support the optional KUV11 Writeable Control Store.

Chip variants

There are a number of variants of all the various uROM chips in the base set; it is not known if all variants are completely inter-operable (i.e. any revision of any chip can be replaced with any other, and have the machine still work), so combinations will be listed.

Chip numbers of the form 23-xxxxx-rr, etc are DEC part numbers (where 'rr' seems to represent a revision number - 0, if not given); the corresponding Western Digital numbers are xxxxy, etc (where the 'x's are digits, and the 'y' a letter).

The Data Path chip is a 1611H (various DEC part numbers), and the Control chip is a 2007C (ditto); the uROM chips are all 30xxy.

The following sets (Data, Control, uROMs) have been observed (the first three on LSI-11/2 cards):

  • 1611H 21-11549-01, 2007C 23-002C4, 3010A 23-001B5, 3007D 23-002B5
  • 1611H 21-16890, 2007C 23-002C4, 3010D 23-001B5, 3007D 23-007B5
  • 1611H 21-16890, 2007C 23-003C4, 3010D 23-008B5, 3007D 23-007B5
  • unknown, unknown, 3010D 23-001B5, 3007D 23-002B5

The 3010D contains uROM addresses 0x000-0x1ff, and the 3007D 23-002B5 contains 0x200-0x3ff.

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