Difference between revisions of "MG20 MOS memory"
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| − | The '''MG20''' was a [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] [[main memory]] system for the later [[PDP-10]]s, principally the final [[KL10]]s (models KL10-E and KL10-R). An MG20 contained up to | + | The '''MG20''' was a [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] [[main memory]] system for the later [[PDP-10]]s, principally the final [[KL10]]s (models KL10-E and KL10-R). An MG20 contained up to three storage groups, each with 1MW, for a maximum of 3MW; up to 2 MG20's could be connected to a single system, for a total of up to 4M (the limit is in software). |
The MG20 was basically an [[MF20 MOS memory|MF20]] with 64Kx1 [[integrated circuit|chips]], instead of the 16Kx1 chips of the MF20. It appears that it was possible to upgrade an MF20 to an MG20 by replacing the four M8579 MOS Memory cards of each storage group of the MF20 with the M8570 MOS Memory cards of the MG20, and upgrading the [[power supply]]; the four control cards of the MF20: | The MG20 was basically an [[MF20 MOS memory|MF20]] with 64Kx1 [[integrated circuit|chips]], instead of the 16Kx1 chips of the MF20. It appears that it was possible to upgrade an MF20 to an MG20 by replacing the four M8579 MOS Memory cards of each storage group of the MF20 with the M8570 MOS Memory cards of the MG20, and upgrading the [[power supply]]; the four control cards of the MF20: | ||
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<!-- The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). --> | <!-- The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). --> | ||
| − | [[Error-correcting code|ECC]] is provided to protect the memory contents | + | [[Error-correcting code|ECC]] is provided to protect the memory contents; the MG20 almost certainly shared the MF20's 44-[[bit]] word, which contained 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MG20 could almost certainly be similarly configured to switch the spare bit in to temporarily replace a failing bit, until the latter could be replaced. |
| − | [[Category: PDP-10 | + | The MG20 also connected to the KL10's upgraded internal memory bus, the [[PDP-10 Memory Bus|X-Bus]]. The MG20 was [[multi-port memory|single-port memory]], and could not be used in a [[multi-processor]] system, or with external [[channel]]s. |
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| + | ==See also== | ||
| + | |||
| + | * [[MF20 MOS memory]] | ||
| + | |||
| + | ==External links== | ||
| + | |||
| + | * [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MF20_TechMan.pdf MOS Memory Subsystem Technical Manual] (EK-0MF20-TM) - Contains much MG20-specific content (Chapter 9) | ||
| + | * [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MP01904_MG20_Jun84.pdf MG20 Field Maintenance Print Set] (MP01904) | ||
| + | |||
| + | [[Category: PDP-10 Memories]] | ||
Latest revision as of 15:49, 24 October 2022
The MG20 was a MOS DRAM main memory system for the later PDP-10s, principally the final KL10s (models KL10-E and KL10-R). An MG20 contained up to three storage groups, each with 1MW, for a maximum of 3MW; up to 2 MG20's could be connected to a single system, for a total of up to 4M (the limit is in software).
The MG20 was basically an MF20 with 64Kx1 chips, instead of the 16Kx1 chips of the MF20. It appears that it was possible to upgrade an MF20 to an MG20 by replacing the four M8579 MOS Memory cards of each storage group of the MF20 with the M8570 MOS Memory cards of the MG20, and upgrading the power supply; the four control cards of the MF20:
- M8574 Write Path
- M8575 Syndrome
- M8576 Control and Timing
- M8577 Address and Timing
remained unchanged.
ECC is provided to protect the memory contents; the MG20 almost certainly shared the MF20's 44-bit word, which contained 36 data bits, 6 ECC bits, 1 bit of ECC parity, and 1 spare bit. The MG20 could almost certainly be similarly configured to switch the spare bit in to temporarily replace a failing bit, until the latter could be replaced.
The MG20 also connected to the KL10's upgraded internal memory bus, the X-Bus. The MG20 was single-port memory, and could not be used in a multi-processor system, or with external channels.
See also
External links
- MOS Memory Subsystem Technical Manual (EK-0MF20-TM) - Contains much MG20-specific content (Chapter 9)
- MG20 Field Maintenance Print Set (MP01904)
