MH10 core memory

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The MH10 was a core main memory system for the PDP-10s, principally the early KL10. An MG10 could contain up to four 64KW memory banks, for a maximum of 256KW (only 1, 2 or 4 bank operation is supported, however). The access time is .74 µseconds, and the cycle time is 1.18 µseconds; parity is provided to protect the memory contents. An MH10 contains a pair of 'controllers', with the controller used for any particular cycle selected by address bit 20.

It was a multi-port memory, with 8 ports per memory system: the CPU uses one port (in a multi-processor system, one per CPU); the others are used by channels (such as a DF10) for mass storage such as disks.

It connected to the so-called external memory bus of the 18-or 22-bit address form. Each port on each module could be independently set to use 18- or 22-bit addresses, or to be disabled. The base address of an MH10 is switch-selectable; that address is used on all the ports, unlike the earlier PDP-10 memories.

The MH10 supports two-way interleaving internally to an MH10, and four-way interleaving between a pair of MH10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 20 and 35 are exchanged, so that all even addresses are handled by controller 0, and odd by controller 1.