Difference between revisions of "MM11-L core memory"

From Computer History Wiki
Jump to: navigation, search
(Parity backplane info)
(More parity details)
Line 6: Line 6:
  
 
The MM11-L required a custom [[backplane]], although some [[Central Processing Unit|CPU]]'s (e.g. the [[PDP-11/05]]) had processor backplanes wired to hold one or more MM11-L sets, as well as the CPU.
 
The MM11-L required a custom [[backplane]], although some [[Central Processing Unit|CPU]]'s (e.g. the [[PDP-11/05]]) had processor backplanes wired to hold one or more MM11-L sets, as well as the CPU.
 +
 +
The '''MM11-S''' was a four-slot backplane plus a single MM11-L board set. The '''MF11-L''' was a nine-slot backplane plus a single MM11-L board set; the backplane has room for two more MM11-L board sets. The '''ME11-L''' was an MF11-L in a 5-1/4" rack-mount box, with [[power supply]] (the -LA was wired for 115V supply, the -LB for 230V).
 +
 +
==Parity==
  
 
There was also a [[parity]] variant, the '''MM11-LP''', which added an M7259 dual-width parity controller, and substituted an H215 (with two more bits per word) for the H214, and a G109 for the G110. Enabling parity increased the [[access time]] from 400 nsec to 525 nsec.
 
There was also a [[parity]] variant, the '''MM11-LP''', which added an M7259 dual-width parity controller, and substituted an H215 (with two more bits per word) for the H214, and a G109 for the G110. Enabling parity increased the [[access time]] from 400 nsec to 525 nsec.
  
The '''MM11-S''' was a four-slot backplane plus a single MM11-L board set. The '''MF11-L''' was a nine-slot backplane plus a single MM11-L board set; the backplane has room for two more MM11-L board sets. The '''ME11-L''' was an MF11-L in a 5-1/4" rack-mount box, with [[power supply]] (the -LA was wired for 115V supply, the -LB for 230V).
+
Parity versions (with a 'P' suffix) were available for all of the above. The manual indicates that an 'MF11-LP backplane' was required, but it is not stated if this version had a different [[printed circuit board|PCB]], or if the non-parity version simply had a [[jumper]], like the [[MM11-U core memory]].
 +
 
 +
The explanation appears to be that there are two versions of the backplane, the early one (part #5409959) which cannot run parity, and a later one (part #5410331) which can. An example of the later backplane had the same jumper as that called for for the MM11-U, from pin B1U1 to B2U1, which appears to confirm this analysis. This jumper should not be present for parity memory.
  
Parity versions (with a 'P' suffix) were available for all of the above. The manual indicates that an 'MF11-LP backplane' was required, but it is not stated if this version had a different [[printed circuit board|PCB]], or if the non-parity version simply had a [[jumper]], like the [[MM11-U core memory]].
+
(The parity controller is not in that slot; the backplane wires together all the BU1 SSYN pins on the interior slots, and the jumper connects together that line, and the main UNIBUS SSYN. Thus apparently the G109 module does not drive that SSYN pin, but the G110 does - hence the need to install the jumper for non-parity memory. It is not clear how the parity controller drives SSYN.The fact that that trace is wired to all the interior slots may indicate that the parity controller can be placed in any empty slot.)
  
The explanation appears to be that there are two versions of the backplane, the early one (part #5409959) which cannot run parity, and a later one (part #5410331) which can. An example of the later backplane had the same jumper as that called for for the MM11-U, from pin B1U1 to B2U1, which appears to confirm this analysis.
+
Note that therefore parity and non-parity memory cannot be mixed on the same backplane. There is also no provision for use of the M7259 parity controller in the PDP-11/05 backplanes which support the MM11-L.
  
This jumper should not be present for parity memory. Note that therefore parity and non-parity memory cannot be mixed on the same backplane. There is also no provision for use of the M7259 parity controller in the PDP-11/05 backplanes which support the MM11-L.
+
==Module chart==
  
 
The board organization in the MM11-L backplanes is not given in the manual; that for the MF11-L is:
 
The board organization in the MM11-L backplanes is not given in the manual; that for the MF11-L is:

Revision as of 19:04, 19 July 2019

The MM11-L core memory was a popular, and common, 16 Kbyte core main memory unit for the early PDP-11 UNIBUS machines. An MM11-L was composed of a three board set:

  • G110 - hex-width memory control logic and data channels
  • G231 - hex-width memory driver logic
  • H214 - quad-width core stack

The MM11-L required a custom backplane, although some CPU's (e.g. the PDP-11/05) had processor backplanes wired to hold one or more MM11-L sets, as well as the CPU.

The MM11-S was a four-slot backplane plus a single MM11-L board set. The MF11-L was a nine-slot backplane plus a single MM11-L board set; the backplane has room for two more MM11-L board sets. The ME11-L was an MF11-L in a 5-1/4" rack-mount box, with power supply (the -LA was wired for 115V supply, the -LB for 230V).

Parity

There was also a parity variant, the MM11-LP, which added an M7259 dual-width parity controller, and substituted an H215 (with two more bits per word) for the H214, and a G109 for the G110. Enabling parity increased the access time from 400 nsec to 525 nsec.

Parity versions (with a 'P' suffix) were available for all of the above. The manual indicates that an 'MF11-LP backplane' was required, but it is not stated if this version had a different PCB, or if the non-parity version simply had a jumper, like the MM11-U core memory.

The explanation appears to be that there are two versions of the backplane, the early one (part #5409959) which cannot run parity, and a later one (part #5410331) which can. An example of the later backplane had the same jumper as that called for for the MM11-U, from pin B1U1 to B2U1, which appears to confirm this analysis. This jumper should not be present for parity memory.

(The parity controller is not in that slot; the backplane wires together all the BU1 SSYN pins on the interior slots, and the jumper connects together that line, and the main UNIBUS SSYN. Thus apparently the G109 module does not drive that SSYN pin, but the G110 does - hence the need to install the jumper for non-parity memory. It is not clear how the parity controller drives SSYN.The fact that that trace is wired to all the interior slots may indicate that the parity controller can be placed in any empty slot.)

Note that therefore parity and non-parity memory cannot be mixed on the same backplane. There is also no provision for use of the M7259 parity controller in the PDP-11/05 backplanes which support the MM11-L.

Module chart

The board organization in the MM11-L backplanes is not given in the manual; that for the MF11-L is:

Connector
Slot A B C D E F
1 UNIBUS In H213/H214 Core stack
2 G231 Memory Driver
3 G110 Memory Control
4 G231 Memory Driver
5 G110 Memory Control
6 M7259 Parity Controller H213/H214 Core stack
7 G231 Memory Driver
8 G110 Memory Control
9 UNIBUS Out H213/H214 Core stack

The first MM11-L set goes in slots 1/2/3; as MM11-L sets were added, they were installed in slot numerical order. The location of the parity controller has yet to be definitively documented, but there is only one open dual slot in a full MF11-L.