Difference between revisions of "PDP-11 architecture"
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The PDP-11 is a family of 16-bit minicomputer designed by DEC, in production from 1970-1990. Although the basic address space was 16 bits, most models could hold more memory than that, although only a limited subset was visible to the program at any time.
It had 8 general purpose registers; the operand coding, which was applied regularly across essentially the entire instruction set, allowed it to provide a two-address instruction architecture, not simple load-store architecture like its predecessor, the 12-bit PDP-8.
One of the registers was dedicated to be the Program Counter, and one was more or less dedicated to be the Stack Pointer. (Other registers can be used as stack pointers, but the hardware uses this one for subroutine call and return, interrupts, etc.)
These registers, along with a variety of register-based addressing modes, allowed it to provide a variety of additional operand types, such as immediate (literal) data, absolute and relative addresses, and stack operations; very impressive on a machine which had only 16-bit words (and thus instructions).
The regular application of the operand coding across essentially the entire instruction set allowed these additional operand types to be widely available; this, and the power of the large range of operand modes, substantially reduced the code size.
This was an important consideration both in the PDP-11's early life, when small and expensive core memory was the standard main memory; and in its later life, when the 16-bit address space became a severe limit.
Most instructions come in both byte and word forms; an exception is ADD and SUB, which exist in only word forms (probably because there was not enough room in the instruction set to have them both in both forms).
Later machines tended to include the former group - although on some early mid-range machines such as the PDP-11/40 and PDP-11/03, they were only an option. Floating point was also added to the later machines (although only as an option, until relatively late in the line).
Late in the PDP-11 family's lifetime, a PDP-11 Commercial Instruction Set was defined, and made available as an option in some of the later machines.
Two forms of floating point were added: a simplified form, FIS floating point, with only the 4 basic operations, using 32-bit variables, in a few early machines; and full-blown floating point (32-bit and 64-bit formats, many operations), FP11 floating point.
The former was available as an option in the PDP-11/40, and later in the PDP-11/03. The latter was available as an option in the PDP-11/45 and variants thereof (the PDP-11/50 and PDP-11/55), the PDP-11/70, PDP-11/34, PDP-11/44 and PDP-11/23; it was standard in the KDJ11-B and KDJ11-E (although in all these machines an optional FPJ11 floating point accelerator greatly improved the floating point throughput).
After a few disparate custom add-on units to provide memory management in the PDP-11/20, memory management became standardized with the PDP-11/45 (in which it was an option); most later machines supported it. A simplified version was supported in the -11/40 and -11/23 (as an option), and in the -11/34 (standard).
The PDP-11 supported both single- and double-operand instructions. The operands are mostly the most flexible form, in which a 6-bit field holds three bits of register number, and three bits of mode. (Which is why PDP-11 object code is usually displayed in octal, as it is the optimal base for that, since each operand field will be in one octal 'digit'.)
As noted above, this operand form provided a large variety of operand types, including stack push and pop, literals, etc. This provides the basic instruction group with great flexibility, especially the double-operand instructions (MOV, ADD, etc).
A few instructions (mostly those which were added to the instruction repertoire later, e.g. MUL, DIV, XOR, etc) only provide a register number for one operand (i.e. if not already in a register, that operand must be pre-loaded into one by another instruction).
The mode field is further subdivided into a 'Deferred' (indirect) bit, and a two bit field which selects among direct register, auto-increment, auto-decrement, and indexed modes. The indirect bit is the low bit, so odd values of the mode 'digit' are indirect.
The 'regular' modes are:
|0||Register||R||(R) is the operand|
|2||Auto-increment||(R)+||(R) is the address; (R) is incremented by 1 or 2, in case of byte or word instructions.|
|4||Auto-decrement||(R)-||(R) is decremented by 1 or 2, in case of byte or word instructions; R is address.|
|6||Index||X(R)||(R) + X is the address.|
and the indirect modes are:
|1||Register deferred||@R or (R)||(R) contains address of operand|
|3||Auto-increment deferred||@(R)+||(R) is the address of the address; (R) is incremented by 2|
|5||Auto-decrement deferred||@(R)-||(R) is decremented by two; (R) is the address of the address.|
|7||Index deferred||@X(R)||(R) + X is the address of the address|
As mentioned, auto-increment and auto-decrement allow any register to be used as a stack pointer, but the hardware enforces the use of R6 as the SP, so it is un-common for another register to be used for this.
The use of auto-increment mode with the PC provides literal operands (both immediate, and absolute addresses); indexed modes with the PC can be used for location-independent code.
The instruction set provided a number of double-operand instructions:
- BIT (bit test)
- BIS (bit set)
- BIC (bit clear)
(as noted, ADD and SUB are only available in word mode), and many single-operand instructions:
- TST (compare with 0)
- COM (complement)
- ASR (arithmetic shift right)
- ROR (rotate right)
- SWAB (swap bytes)
- ADC (add carry)
Condition codes and conditional branches
The instruction set provided a plethora of branches, although all branches are limited to a range of 127 words before or after the current instruction; a limit which is not onerous in practise. All the conditional branches depend on a prior instruction to set 4 condition codes (stored in the Processor Status Word):
- Z - Zero
- N - Negative (i.e. high bit set)
- C - Carry
- V - Overflow
- BR (un-conditional)
- BNE (non-zero)
- BEQ (zero)
- BMI (negative)
- BPL (positive)
- BVC (overflow clear)
- BVS (overflow)
- BCS (carry)
- BCC (no carry)
- BGE (greater than or equal to 0)
- BHIS (higher than, or the same)
Other flow of control instructions (both JMP and JSR) can transfer to any location in the address space):
- JSR - subroutine call
- RTS - subroutine return
The PDP-11/45 added a few miscellaneous instructions:
- SOB (decrement and conditionally branch)
- XOR (word only, and also only provides a register number for one operand)
- SXT (sign extend, word only)
- MARK (subroutine argument setup)
- RTT (return from interrupt while inhibiting 'trace' trap)
- SPL (set CPU priority level)
All of these, with the exception of SPL, appeared in all later models (except the -11/05 and -11/04).
Various later models added various instructions for Processor Status Word access, maintenance, etc.
The PDP-11 is impossible to virtualize, since there are a number instructions used by operating systems which do not trap when executed by a program running in user mode. HALT and SPL do trap, but not others, including:
Of these, in user mode RESET is a no-op, RT[IT] cannot change the current and previous modes, MFPI acts like MPFD in user mode when the previous mode is also user (to prevent 'theft' of proprietary code), and MTPS can only set the condition codes.
|v • d • e PDP-11 Computers and Peripherals|
| Unibus PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 • PDP-11/05 • PDP-11/10 • PDP-11/34 • PDP-11/04 • PDP-11/44 • PDP-11/60 • PDP-11/24 • PDP-11/84 • PDP-11/94
Clones: CM 1420