Difference between revisions of "PDP-8/S"

From Computer History Wiki
Jump to: navigation, search
(see "Computer Structures: Readings and Examples", page 120: "A PDP-S/S is one-fifteenth of a PDP-8 at one-half the cost. ...even though the same 2-megahertz logic clock is used in both cases.")
(Secondary source wrong - see Talk page)
Line 12: Line 12:
 
| virtual address = 4k words
 
| virtual address = 4k words
 
| design type = [[clock]]ed random [[logic]]  
 
| design type = [[clock]]ed random [[logic]]  
| clock speed = 2 MHz
+
| clock speed = 1.333Mhz (bit) / 95kHz (word)
 
| memory speed = 8 μseconds
 
| memory speed = 8 μseconds
 
| memory mgmt = bank select
 
| memory mgmt = bank select
Line 30: Line 30:
 
}}
 
}}
  
The '''PDP-8/S''' was [[Digital Equipment Corporation|DEC]]'s attempt to produce a 'cheaper' [[PDP-8]]. It was a [[serial computer|serial]] implementation, which reduced the part count somewhat, but resulted in an incredibly slow machine, compared to the rest of the line. It was soon discontinued.
+
The '''PDP-8/S''' was [[Digital Equipment Corporation|DEC]]'s attempt to produce a 'cheaper' [[PDP-8 family|PDP-8]]. It was a [[serial computer|serial]] implementation, which reduced the part count somewhat, but resulted in an incredibly slow machine, compared to the rest of the line. It was soon discontinued.
  
 
The PDP-8 was constructed with discrete [[transistor]]s, packaged into DEC's [[FLIP CHIP]] technology. It could perform an addition to the [[accumulator]] in 64 μseconds. It had [[parity]] on the [[main memory]] as standard, not optional.
 
The PDP-8 was constructed with discrete [[transistor]]s, packaged into DEC's [[FLIP CHIP]] technology. It could perform an addition to the [[accumulator]] in 64 μseconds. It had [[parity]] on the [[main memory]] as standard, not optional.

Revision as of 14:40, 19 August 2019


PDP-8/S
PDP-8-SFrontPanel.jpg
PDP-8/S front panel inlay
Manufacturer: DEC
Architecture: PDP-8
Year Introduced: 1967
Year Discontinued: 1970
Form Factor: minicomputer
Word Size: 12 bits
Logic Type: DTL
Design Type: clocked random logic
Clock Speed: 1.333Mhz (bit) / 95kHz (word)
Memory Speed: 8 μseconds
Physical Address Size: 32k words (requires optional MC8S)
Virtual Address Size: 4k words
Memory Management: bank select
Bus Architecture: Negative I/O Bus
Predecessor(s): PDP-8
Successor(s): PDP-8/L


The PDP-8/S was DEC's attempt to produce a 'cheaper' PDP-8. It was a serial implementation, which reduced the part count somewhat, but resulted in an incredibly slow machine, compared to the rest of the line. It was soon discontinued.

The PDP-8 was constructed with discrete transistors, packaged into DEC's FLIP CHIP technology. It could perform an addition to the accumulator in 64 μseconds. It had parity on the main memory as standard, not optional.

Options

Options included:

  • DB8S Data Break, needed for data break on the I/O bus
  • MC8S Memory Extension Control, which was needed to support more than 4k words of memory
  • MM8S Memory Module
  • ME8S Memory Extension, holds two MM8S