Difference between revisions of "Pipeline"
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| − | A '''pipeline''' is a way of arranging the internal [[logic]] in a [[Central Processing Unit|CPU]] to increase the processing capacity of that CPU. It organizes the processing of an [[instruction]] into several discrete stages, and then allows each stage to be occupied simultaneously by different instructions. | + | A '''pipeline''' is a way of arranging the internal [[logic]] in a [[Central Processing Unit|CPU]] to increase the processing capacity of that CPU. It organizes the processing of an [[instruction]] into several discrete sequential stages, and then allows each stage to be occupied simultaneously by different instructions. |
Thus, while the time to execute a ''particular'' instruction, from beginning to end, is the basic [[clock]] rate times the number of pipeline stages, each clock tick will generally see the completion of the [[execute|execution]] of ''an'' instruction. (The caveat is because in complex CPUs, execution of an instruction is sometimes 'stalled' for various reasons.) | Thus, while the time to execute a ''particular'' instruction, from beginning to end, is the basic [[clock]] rate times the number of pipeline stages, each clock tick will generally see the completion of the [[execute|execution]] of ''an'' instruction. (The caveat is because in complex CPUs, execution of an instruction is sometimes 'stalled' for various reasons.) | ||
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| + | [[Category: Hardware Basics]] | ||
Revision as of 05:09, 13 December 2018
A pipeline is a way of arranging the internal logic in a CPU to increase the processing capacity of that CPU. It organizes the processing of an instruction into several discrete sequential stages, and then allows each stage to be occupied simultaneously by different instructions.
Thus, while the time to execute a particular instruction, from beginning to end, is the basic clock rate times the number of pipeline stages, each clock tick will generally see the completion of the execution of an instruction. (The caveat is because in complex CPUs, execution of an instruction is sometimes 'stalled' for various reasons.)
