Difference between revisions of "RH11 MASSBUS controller"

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(Link to unibus parity article)
(Add backplane layout)
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The '''RH11 MASSBUS controller''' allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to systems with a [[UNIBUS]], primarily [[PDP-11]]'s.
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The '''RH11 MASSBUS controller''' (technically, the '''RH11-AB''') allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to systems with a [[UNIBUS]], primarily on [[PDP-11]]'s.
  
The RH11 has the capability to operate in [[UNIBUS parity#18-bit width|18-bit mode]]; in this mode, the PA and PB UNIBUS lines are used for data bits 16 and 17. The [[KS10]] made use of this capability.
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The RH11 has the capability to operate in [[UNIBUS parity#18-bit width|18-bit mode]]; in this mode, the PA and PB UNIBUS [[parity]] lines are used for data bits 16 and 17. The [[KS10]] made use of this capability.
  
 
==Second UNIBUS==
 
==Second UNIBUS==
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The [[register]]s in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, [[interrupt]]s of the [[Central Processing Unit|CPU]] are only possible via UNIBUS 'A'. The RH11 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B').
 
The [[register]]s in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, [[interrupt]]s of the [[Central Processing Unit|CPU]] are only possible via UNIBUS 'A'. The RH11 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B').
  
If no CPU is connected to UNIBUS 'B', an [[M9300 terminator]] at the start of the bus can be configured to do [[Non-Processor Request|NPR]] grants. A jumper allows the RH11 to do block transfers on UNIBUS 'B' without going through an arbitration cycle; the 'A' UNIBUS has a mode where it does two DMA cycles per grant.
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If no CPU is connected to UNIBUS 'B', an [[M9300 terminator]] at the start of the bus can be configured to do [[Non-Processor Request|NPR]] [[bus grant]]s. A [[jumper]] allows the RH11 to do block transfers on UNIBUS 'B' without going through an [[arbitration]] cycle; the 'A' UNIBUS has a mode where it does two DMA cycles per grant.
  
 
==Registers==
 
==Registers==
  
The RH11 contains 4 registers, plus a share of a fifth; they are
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The RH11 contains 4 [[register]]s, plus a share of a fifth; they are
  
 
* RHCS1 - Control and Status 1 (shared)
 
* RHCS1 - Control and Status 1 (shared)
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==Hardware==
 
==Hardware==
  
The RH11 consisted of a double [[system unit]] [[backplane]] into which plugged a number of cards:
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The RH11 consisted of a double [[system unit]] [[backplane]] (below) into which plugged a number of cards:
  
 
Two of them [[DEC card form factor|hex]]-sized:
 
Two of them [[DEC card form factor|hex]]-sized:
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* M7295 - BCT - Bus Control
 
* M7295 - BCT - Bus Control
  
Two [[DEC card form factor|dual]]-sized cards containing controller logic:
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Two dual-sized cards containing controller logic:
  
 
* M7296 - CSR - Control and Status
 
* M7296 - CSR - Control and Status
 
* M7297 - PAC - Parity Generation and Checking
 
* M7297 - PAC - Parity Generation and Checking
  
Three [[DEC card form factor|dual]]-height M5904 MASSBUS transceiver modules.
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Three dual-height M5904 MASSBUS transceiver modules.
  
Optionally one or two (see below) [[DEC card form factor|single]]-height cards:
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Optionally one or two single-height cards:
  
 
* M688 - UNIBUS Power Fail Driver
 
* M688 - UNIBUS Power Fail Driver
  
 
The RH11 backplane also contained three [[Small Peripheral Controller|SPC]] slots in otherwise-unused slots.
 
The RH11 backplane also contained three [[Small Peripheral Controller|SPC]] slots in otherwise-unused slots.
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===Backplane layout===
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Board locations (as seen from the board insertion side of the backplane, not the [[wire-wrap]] pin side, as is common in [[DEC]] documentation) are:
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{| class="wikitable"
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! !! colspan="6" | Connector
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|-
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! Slot !! A !! B !! C !! D !! E !! F
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|-
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| 1 || colspan="2" style="text-align:center;" | UNIBUS A In || colspan="2" style="text-align:center;" | M7297 Parity || colspan="2" style="text-align:center;" | M7296 Control/Status
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|-
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| 2 || colspan="6" style="text-align:center;" | M7295 Bus Control
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|-
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| 3 || colspan="6" style="text-align:center;" | M7294 Data/Buffer Control
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|-
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| 4 || colspan="2" style="text-align:center;" | Unused || colspan="2" style="text-align:center;" | M5904 Transceiver || M688 - UNIBUS B Power Fail || Unused
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|-
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| 5 || colspan="2" style="text-align:center;" | Unused || colspan="2" style="text-align:center;" | M5904 Transceiver || M688 - UNIBUS A Power Fail || Unused
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|-
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| 6 || colspan="2" style="text-align:center;" | Unused || colspan="2" style="text-align:center;" | M5904 Transceiver || colspan="4" style="text-align:center;" | Unused
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|-
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| 7 || colspan="2" style="text-align:center;" | UNIBUS B Out || colspan="4" style="text-align:center;" | SPC
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|-
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| 8 || colspan="2" style="text-align:center;" | UNIBUS B In || colspan="4" style="text-align:center;" | SPC
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|-
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| 9 || colspan="2" style="text-align:center;" | UNIBUS A Out || colspan="4" style="text-align:center;" | SPC
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|}
  
 
[[Category: MASSBUS Controllers]]
 
[[Category: MASSBUS Controllers]]
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[[Category: UNIBUS Storage Controllers]]

Revision as of 16:57, 21 November 2019

The RH11 MASSBUS controller (technically, the RH11-AB) allowed the interconnection of MASSBUS devices such as the RP04 to systems with a UNIBUS, primarily on PDP-11's.

The RH11 has the capability to operate in 18-bit mode; in this mode, the PA and PB UNIBUS parity lines are used for data bits 16 and 17. The KS10 made use of this capability.

Second UNIBUS

The RH11 contains connectors and circuitry for two separate UNIBUSes; the second UNIBUS is primarily used on systems with multi-port memory, such as the PDP-11/45.

The registers in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, interrupts of the CPU are only possible via UNIBUS 'A'. The RH11 can be set under software control to do DMA data transfers on either the first or second UNIBUS (UNIBUS 'B').

If no CPU is connected to UNIBUS 'B', an M9300 terminator at the start of the bus can be configured to do NPR bus grants. A jumper allows the RH11 to do block transfers on UNIBUS 'B' without going through an arbitration cycle; the 'A' UNIBUS has a mode where it does two DMA cycles per grant.

Registers

The RH11 contains 4 registers, plus a share of a fifth; they are

  • RHCS1 - Control and Status 1 (shared)
  • RHWC - Word Count
  • RHBA - Bus Address
  • RHCS2 - Control and Status 2
  • RHDB - Data Buffer (for maintenance)

As is standard for the MASSBUS, all the other device registers are in the device.

Hardware

The RH11 consisted of a double system unit backplane (below) into which plugged a number of cards:

Two of them hex-sized:

  • M7294 - DBC - Data Buffer and Control
  • M7295 - BCT - Bus Control

Two dual-sized cards containing controller logic:

  • M7296 - CSR - Control and Status
  • M7297 - PAC - Parity Generation and Checking

Three dual-height M5904 MASSBUS transceiver modules.

Optionally one or two single-height cards:

  • M688 - UNIBUS Power Fail Driver

The RH11 backplane also contained three SPC slots in otherwise-unused slots.

Backplane layout

Board locations (as seen from the board insertion side of the backplane, not the wire-wrap pin side, as is common in DEC documentation) are:

Connector
Slot A B C D E F
1 UNIBUS A In M7297 Parity M7296 Control/Status
2 M7295 Bus Control
3 M7294 Data/Buffer Control
4 Unused M5904 Transceiver M688 - UNIBUS B Power Fail Unused
5 Unused M5904 Transceiver M688 - UNIBUS A Power Fail Unused
6 Unused M5904 Transceiver Unused
7 UNIBUS B Out SPC
8 UNIBUS B In SPC
9 UNIBUS A Out SPC