Difference between revisions of "Talk:MB20 core memory"

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(Messed up the editing.)
(Mid-period: Temporal label, I think)
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What is a "mid-period KL10"?  What period is that, and what are the associate hardware characteristics? [[User:Larsbrinkhoff|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff|talk]]) 05:57, 5 July 2019 (CEST)
 
What is a "mid-period KL10"?  What period is that, and what are the associate hardware characteristics? [[User:Larsbrinkhoff|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff|talk]]) 05:57, 5 July 2019 (CEST)
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: Hmmm... trying to reconstruct what I was thinking when I wrote that!
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: I guess that at a hardware '''system''' level, there are two main KL10 variants, those with internal and external memory. But for the '''CPUs''', there are a number of subtle variations (not all of which I remember off the top of my head); e.g. I seem to recall there are 'Model B' KL10's, which sort of implies there must have been an 'A' - and I forget the differences between them. Then there's extended addressing, and also ISTR there were different amounts of microcode.
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: None of which is laid out in the [[KL10]] article, we should fix that.
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: I guess by 'mid-period KL10' I was referring more to a ''temporal'' thing, rather than a particular hardware configuration; I meant early internal memory machines (since later ones all want to DRAM). [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 15:35, 5 July 2019 (CEST)

Revision as of 14:35, 5 July 2019

Interleaving

Memory interleaving:

https://images.slideplayer.com/25/8010523/slides/slide_11.jpg

Basically you start access on the first word, then while you read the first word, the memory controller starts access on the second word, and while you read the second word, the memory controller starts access on the third word,

Now, depending on burst length, like 8 words, you can restart access on the first word again, while you are reading the fourth word, and start the cycle over again, until you reach the length of the burst length.

The iPX 420 did bit interleaving. the 8088 did byte interleaving, ( 8bit processor 1 word interleaving. ) the 8086 also did byte interleaving, the 286 did word interleaving, two bytes at a time, the 386 did word interleaving, 4 bytes at a time, but it had to start on a 4 word boundry for the first read.

ForOldHack (talk) 10:55, 21 March 2019‎ ‎ (CET)

Err, I do actually know about interleaving (worked on machines that used it, back in the day); that "still trying to understand interleaving" really meant 'still trying to understand the interleaving on the MB20'.
BTW, what you've described isn't really interleaving (in the classical sense of that term); not sure of the exact term for the above, it's kind of like pipelined multi-word block reads. Interleaving is when you have two (for 2-way interleaving) separate memory controllers (each with an associated block of storage), and reads to location N and N+1 each go to different controllers. This is useful for core memory, since it's destructive readout (i.e. on read, the data has to be written back), so the cycle time is considerably longer than the access time. (And now that I look, the interleaving article doesn't include that bit about why the cycle time is longer for core, I'll have to add it.) Jnc (talk) 15:15, 21 March 2019 (CET)

Mid-period

What is a "mid-period KL10"? What period is that, and what are the associate hardware characteristics? Larsbrinkhoff (talk) 05:57, 5 July 2019 (CEST)

Hmmm... trying to reconstruct what I was thinking when I wrote that!
I guess that at a hardware system level, there are two main KL10 variants, those with internal and external memory. But for the CPUs, there are a number of subtle variations (not all of which I remember off the top of my head); e.g. I seem to recall there are 'Model B' KL10's, which sort of implies there must have been an 'A' - and I forget the differences between them. Then there's extended addressing, and also ISTR there were different amounts of microcode.
None of which is laid out in the KL10 article, we should fix that.
I guess by 'mid-period KL10' I was referring more to a temporal thing, rather than a particular hardware configuration; I meant early internal memory machines (since later ones all want to DRAM). Jnc (talk) 15:35, 5 July 2019 (CEST)