Chaosnet interface
The Chaosnet UNIBUS interface (also called the CHAOS-11, CH11, QUAD and QAD; there was no generally-used name) and QBCHNI are Chaosnet network interfaces, for the UNIBUS and QBUS respectively. (The two device controllers are identical in programming terms, so they are both covered in this single article.)
They use programmed I/O to transfer data to and from buffers in main memory. They have on-board buffers (one each for inbound and outbound) which can hold one packet of data.
They are both a single quad wire-wrapped card.
Their bus address and interrupt vectors can be set via DIP switches; the defaults are 0764140 and 0270. The network address is also set via a DIP switch.
Contents
Device registers
They have 7 registers:
| Register | Abbreviation | Address |
|---|---|---|
| Command and Status Register | CAICSR | 764140 |
| My address (read only) | CAIMYN | 764142 |
| Write buffer (write only) | CAIWBF | 764142 |
| Read buffer | CAIRBF | 764144 |
| Read bit counter | CAIRBC | 764146 |
| Unused | 764150 | |
| Initiate transmission | CAIXMT | 764152 |
| Unused | 764154 | |
| Unused | 764156 | |
| Load interval timer (write only) | CAITIM | 764160 |
In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in italics, and those which are write-only are shown in bold.
764140: Control Status Register (CSR)
| RDN | ERR | RST | LSTCN | TCL | TDN | TAB | TEN | REN | RCL | SPY | LPBK | TIE | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Bits are:
| Bits | Use |
|---|---|
| RDN | Receive done |
| ERR | CRC error |
| RST | I/O reset for interface |
| LSTCN | Count of messages lost |
| TCL | Transmitter clear |
| TDN | Transmitter done |
| TAB | Transmit aborted by conflict |
| TEN | Transmit interrupt enable |
| REN | Receive interrupt enable |
| RCL | Receiver clear |
| SPY | Accept all messages |
| LPBK | Loop back in interface |
| TIE | Timer interrupt enable (was Transmitter busy) |
764142: My Address Register (MYN)
| Subnet7 <---> Subnet0 | Host7 <---> Host0 | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Read-only register.
764142: Write Buffer Register (WBF)
| OutData15 <---> OutData00 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Write-only register.
764144: Read Buffer Register (RBF)
| InData15 <---> InData0 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Read-only register.
764146: Read Bit Counter Register (RBC)
| Unused | BitCount11 <---> BitCount0 | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
On the Chaosnet UNIBUS interface, a read-only register.
On the QBCHNI, writing the interface's network address into this register initiates transmission of a packet.
764152: Initiate Transmission Register (XMT)
| Subnet7 <---> Subnet0 | Host7 <---> Host0 | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
On the Chaosnet UNIBUS interface, a read-only register; reading it initiates transmission of a packet. (The data returned is the interface's network address.)
764160: Load Interval Timer Register (TIM)
| Timer15 <---> Timer00 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Write-only register.
External links
- CHAOS; - includes drawings and documentation
- CHS DEFS - register declarations
- $QUAD LOG - "Log of ChaosNet Interface Boards (quad-high, PDP-11 version)"
- QUAD SETUP - "how to setup .. Chaosnet Interfaces"
- QUAD ECO - "ECO to .. Change cable speed to 4 MHz"
- QADCHS NOTE - random jottings
- SUDS drawings converted to PNG pictures
