|Family:||Motorola M68000 Family|
|Number of registers:||15 general 32-bit registers (8 data, 7 address)|
|Cache:||8K byte icache+dcache|
|Clock Speed:||50, 60, 66, 75 MHz|
Performance was increased over earlier members by adopting a superscalar internal architecture; it has a dual instruction pipeline. It also has a 256-entry branch cache. Its floating point was not pipelined, which limited its floating point performance.
It was replaced by the PowerPC architecture.