Computer History Wiki - User contributions [en]

Power 6/32

2024-12-19T11:56:40Z

Jonathanjo: /* External links */

[[Image:Young-sherlock-holmes-knight.jpeg|thumb|right|3D rendering by a Power 6/32 in Young Sherlock Holmes]]

The '''Power 6/32''', code named '''Tahoe''', from [[Computer Consoles Incorporated]], was the [[Central Processing Unit|CPU]] for a [[supermini]]; the [[Computer Systems Research Group|CSRG]] [[software port|ported]] [[4.3 BSD]] to it, in the '4.3 BSD Tahoe' release.

Although it was not very successful commercially (in part because CCI exited the computer business shortly after it was released), it was very influential as the first non-[[VAX]] machine that [[BSD]] [[UNIX]] was ported to. The Tahoe did help separate out a lot of VAX-specific code from the base, allowing BSD to become more portable, but the Power 6/32 machine quickly disappeared off the market, and not much is known about them.

It was re-sold (under other names) by several vendors: [[Unisys]] sold the 6/32 under the name 'Unisys 7000/40', using their own bastardized BSD+SYSV Unix. (Kuwait Petroleum in Denmark had one of them.) [[ICL]] had the 'Clan 7'. [[Harris]] had the HCX-5, -7, and -9 models (for which a bit survives - below), running the [[SysV]] derivative HCX/UX.

Pixar used a Power 6/32 to render the stained-glass knight in the 1985 movie ''Young Sherlock Holmes''.

==Details==

The Power 6/32 [[CPU]] was implemented in [[transistor-transistor logic|TTL]]; it had a [[clock rate]] of 100nS.

All that I can find out about them is this table from [https://web.archive.org/web/20150123191735/http://www.dunnington.u-net.com/public/dhrystone.c http://www.dunnington.u-net.com/public/dhrystone.c] (archive link)

<pre>
*----------------DHRYSTONE VERSION 1.0 RESULTS BEGIN--------------------------
*
* MACHINE MICROPROCESSOR OPERATING COMPILER DHRYSTONES/SEC.
* TYPE SYSTEM NO REG REGS
* -------------------------- ------------ ----------- ---------------
* CCI POWER 6/32 COS(SV+4.2) cc 7500 7800
* CCI POWER 6/32 POWER 6 UNIX/V cc 8236 8498
* CCI POWER 6/32 4.2 Rel. 1.2b cc 8963 9544
* VAX 11/780 - UNIX 5.2 cc 1515 1562
* VAX 11/780 - UNIX 4.3bsd cc 1646 1662
</pre>

Which may give some indication on the initial reasons why the Power 6/32 was chosen as the successor to the VAX by CSRG.

==Instruction Set==

We can infer a lot from the 4.3BSD-tahoe source file <code>usr/src/bin/as/as.tahoe/instrs</code>

* The CPU has sixteen 32-bit registers r0 ... r13 (fp), r14 (sp), r15 (pc).
* The opcode map and mnemonics for the assembler are as follows:

{| class="wikitable"
! || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || a || b || c || d || e ||f
|-
! 0x00
| halt || - || - || - || - || sinf || ldf || ldd || addb2 || movb || addw2 || movw || addl2 || movl || bbs || -
|-
! 0x10
| nop || brb || - || brw || - || cosf || lnf || lnd || addb3 || cmpb || addw3 || cmpw || addl3 || cmpl || bbc || -
|-
! 0x20
| rei || bneq/bnequ || - || cvtwl || - || atanf || stf || std || subb2 || mcomb || subw2 || mcomw || subl2 || mcoml || emul || aoblss
|-
! 0x30
| bpt || beql/beqlu || - || cvtwb || - || logf || cmpf || cmpd || subb3 || bitb || subw3 || bitw || subl3 || bitl || ediv || aobleq
|-
! 0x40
| ret || bgtr || - || - || - || sqrtf || cmpf2 || cmpd2 || shll || clrb || shlq || clrw || mull2 || clrl || shal || -
|-
! 0x50
| - || bleq || - || - || - || expf || tstf || tstd || shrl || tstb || shrq || tstw || mull3 || tstl || shar || bbssi
|-
! 0x60
| ldpctx || - || - || - || - || - || - || pushd || - || incb || - || incw || divl2 || incl || - || cvtlb
|-
! 0x70
| svpctx || jmp || - || - || - || - || cvlf || cvld || - || decb || - || decw || divl3 || decl || - || cvtlw
|-
! 0x80
| - || bgeq || movs2 || - || - || - || cvfl || cvdl || orb2 || cvtbl || orw2 || bispsw || orl2 || adwc || adda || -
|-
! 0x90
| - || blss || cmps2 || - || - || - || - || ldfd || orb3 || cvtbw || orw3 || bicpsw || orl3 || sbwc || suba || -
|-
! 0xa0
| - || bgtru || - || - || - || - || cvdf || - || andb2 || movzbl || andw2 || loadr || andl2 || mtpr || ffs || -
|-
! 0xb0
| - || blequ || - || - || - || - || negf || negd || andb3 || movzbw || andw3 || storer || andl3 || mfpr || ffc || calls
|-
! 0xc0
| prober || bvc || movs3 || movzwl || - || - || addf || addd || xorb2 || movob || xorw2 || movow || xorl2 || movpsl || btcs || kcall
|-
! 0xd0
| probew || bvs || cmps3 || - || - || - || subf || subd || xorb3 || pushb || xorw3 || pushw || xorl3 || pushl || - || -
|-
! 0xe0
| insque || bgequ/bcs || - || - || - || - || mulf || muld || mnegb || movab || mnegw || movaw || mnegl || moval || - || -
|-
! 0xf0
| remque || bcc/blssu || - || - || - || - || divf || divd || movblk || pushab || - || pushaw || casel || pushal || callf || -

|}

{{semi-stub}}

==See also==

* [[Harris CX series]]

==External links==

* [https://virtuallyfun.com/wp-content/uploads/2017/02/harris_hcx5.jpg Harris HCX-5] - ad
* [https://virtuallyfun.com/wp-content/uploads/2017/02/Harris-HCX-9-print-ad.jpg Harris HCX-9] - ad
* [https://virtuallyfun.com/2017/02/24/the-harris-hcx-9-aka-tahoe-platform/ The Harris HCX-9 aka TAHOE platform]
* Cook, Carpenter, Catmull 1987 "The Reyes Image Rendering Architecture" in ACM ''Computer Graphics'' Vol. 21, No. 4 [http://dl.acm.org/citation.cfm?id=37414 PDF] indicating this machine was used at Pixar for a number of films

[[Category: Superminis]]

4.3 BSD Tahoe

2024-12-19T11:39:22Z

Jonathanjo: A little is known, trying to find more

{{Infobox OS
| image = 43bsd.png
| caption = Logging into a 4.3 BSD system
| name = 4.3 BSD
| creator = CSRG, University of California, Berkeley
| current version = 4.3BSD-Tahoe (1988)
| year introduced = 1988
| type = Multitasking, multiuser
| architecture = [[VAX]], [[Tahoe]] theoretically portable
}}

== 4.3 BSD-Tahoe ==

Tahoe follows up on [[4.3 BSD]] in 1988 with plans to ditch the aging (ironically it would be around for 12 more years...) [[VAX]] platform with machine independence and a port to the short-lived "Tahoe" [[Power 6/32]] platform. However by introducing the Tahoe port, it helped separate out the VAX specific code, there by allowing 4.3 BSD to become a more portable operating system.

The original announcement is here http://groups.google.com/group/comp.sys.tahoe/browse_thread/thread/e7431a9ef74cd7eb#

=== Announcement ===

<pre>
Newsgroups: comp.sys.tahoe
From: bos...@OKEEFFE.BERKELEY.EDU (Keith Bostic)
Date: 15 Jun 88 23:56:31 GMT
Local: Wed, Jun 15 1988 6:56 pm
Subject: 4.3BSD-tahoe release

We are happy to announce the availability of the release of
4.3BSD for the tahoe processors. Attached is a brief summary
of the information mailed to all 4.2 and 4.3BSD licensees.
This mailing contains all necessary ordering information;
if you have not received it by July 5th, please contact our
distribution office at +1-415-642-7780.

Mike Karels
Kirk McKusick
Keith Bostic

========================
We are happy to send you information about our June
1988 revision of the Fourth Berkeley Software Distribution,
hereafter referred to as the ``4.3BSD tahoe'' distribution.
The purpose of this release is to provide 4.3BSD support for
the ``tahoe'' processor and to get feedback on some new
features and facilities that we expect to include in future
Berkeley releases. This distribution is not a standard
Berkeley release; it is an interim release intended for
testing and evaluation rather than production use by naive
users. The distribution is available to users with licenses
for the April 1986 4.3BSD release for the VAX.

What is the 4.3BSD Tahoe Release?

The distribution consists of one 6250 BPI or three 1600
BPI magnetic tapes, certain updated manual pages, and a copy
of ``Installing and Operating 4.3BSD on the Tahoe.'' The
magnetic tape(s) contain copies of source code and documen-
tation for both the VAX and the tahoe, and binaries for the
tahoe. On the three-tape 1600 BPI set, parts of the user-
contributed software are shipped as compressed archives to
save space.

The primary purpose of this release is to provide sup-
port for the ``tahoe'' processor, the CPU used by Computer
Consoles, Inc. (CCI Power 6/32, 6/32SX), and high end lines
of Harris (HCX-7 and HCX-9), Unisys (7000/40), and ICL (Clan
7). Support for this processor is derived from the 4.2BSD
system done by CCI. Support for new DEC equipment has also
been added, including support for the 8250 BI-based CPU and
the KDB-50 BI disk controller from Chris Torek, and the QVSS
and QDSS display drivers for the MicroVAX II, contributed by
Digital Equipment Corporation. We expect to provide support
for both the VAX and the tahoe processors in future
releases.

The major new software systems include the following
features:

+ The TCP and IP code is the same as that recently made
available via the ARPANET and Usenet. Several new
algorithms are used in TCP, in particular Van
Jacobson's slow start and dynamic window size selection
algorithms and Phil Karn's modification to the round-
trip timing algorithm. These changes increase
throughput and reduce congestion and retransmission.
Several fixes were made in the handling of IP options
and other gateway support.

+ The file system has been generalized to remove the lim-
its on the maximum number of inodes per cylinder group,
cylinders per cylinder group, and number of dis-
tinguished rotational positions. The kernel and file
system utilities operate normally on both new and old
format file systems; old kernels treat the new file
systems as read-only. This change allows better utili-
zation of newer disks with larger numbers of sectors
per cylinder.

+ The system has full support for disk labels that con-
tain disk geometry information and partition layout on
each disk. Labels are used on disks using the hp or
uda drivers on the VAX (hp or ra disks) and all sup-
ported disks on the tahoe. The utility to read and
write disk labels can be used with the system running
multiuser; the labels are used and updated as appropri-
ate by newfs, bad144, the kernel and the bootstrap pro-
grams. Basic file system parameters are stored in the
label so that fsck can locate alternate superblocks.
The filesystem and newfs use additional information
about the disk geometry that is now available, such as
track-to-track skew.

+ A new general-purpose dynamic memory allocator has been
written that can be used by all the kernel subsystems.
The design of this allocator takes advantage of known
memory usage patterns in the UNIX kernel, using a
hybrid strategy that is time-efficient for small allo-
cations and space-efficient for large allocations.
This allocator replaces most of the previous memory
allocation interfaces with a single easy-to-program
interface, results in more efficient use of global
memory by eliminating partitioned and specialized
memory pools, and is quick enough that no performance
loss is observed relative to the previous implementa-
tions. Most of the kernel memory allocation is now
done using this allocator.

+ The source code has been reorganized to ease support of
multiple machine types.

+ The Olson/Harris/Elz timezone implementation has been
added to the system.

+ Numerous bug fixes and enhancements have been made
throughout the system, including new versions of the
nameserver named and the routing daemon routed.
Several years' backlog of bug fixes have been applied.

+ We have started a process of identifying the code in
the 4.3BSD distribution that is not derived from AT&T
code. The copyrights in this code have been changed to
indicate that it may be freely distributed if the copy-
right notice is retained and that due credit for its
origin is given to The Regents of the University of
California. Over 1000 files have been identified in
this distribution.

</pre>

== How do I get this to run?! ==

[[SIMH]] Installation instructions
*Installation instructions for 4.3 BSD TAHOE can be found [[Installing 4.3 BSD TAHOE on SIMH|here]]

The [[TUHS]] tape images are broken, and there is no current installed base that I'm aware of. There is complete images on the [[CSRG]] cdrom's however all binaries are built for the Tahoe...

== What Runs? ==

Nothing.

{{Nav Unix}}

[[Category:CSRG BSD]]

Power 6/32

2024-12-19T11:22:04Z

Jonathanjo: Added instruction set

DL11 asynchronous serial line interface

2024-09-27T07:47:38Z

Jonathanjo: Explanation of TTL portion

[[Image:M7800DL11E.jpg|300px|thumb|right|DL11-E card]]

The '''DL11 asynchronous serial line interface''' card (M7800) was a [[UNIBUS]] [[peripheral]] for the [[PDP-11]] series of computers which provided a single [[asynchronous serial line]]. It was a [[DEC card form factor|quad]] format card, and used an [[Small Peripheral Controller|SPC]] slot.

It provided both [[20mA current loop serial line interface|20mA]] and (in some versions) [[EIA RS-232 serial line interface|EIA RS-232]] connectivity at speeds of 110 to 9600 [[baud rate|baud]] (the range depended on the version); the DL11-E version also provided full [[modem]] control. Line connection was via a 40-pin [[Berg connector]] header on the top edge of the card, using the standard [[DEC asynchronous serial line pinout]]. In fact, TTL-level signals are also on this connector.

It was a functionally identical single-board replacement for the [[KL11 asynchronous serial line interface]], which consisted of a dual card, along with two standard single card [[FLIP CHIP]]s. The DL11 also made use of the then-new [[Universal Asynchronous Receiver/Transmitter|UART]] [[MSI]] [[integrated circuit|chip]].

The [[TU58]] tape drive is connected to a DL11-type device, so the device [[address]], etc for TU58's are as for DL11's - the [[register]] addresses and [[interrupt vector]]s are those given below for the 'first' DL11 (DL11 #1).

==Connection==

Selecting between current-loop and EIA interface inputs is done by loopbacks on the Berg connector, called "interlock".

* The actual input is TTL on E: labelled "Serial Input TTL" and "Interlock In"
* The current loop receiver has input on K and S, output on H "20 mA Interlock Out"
* The current loop output is on AA and KK
* (optional) EIA level receiver has input on J, output on M "EIA Interlock Out"
* (optional) EIA output is on F

So, for current loop, we join H to E (and connect K, S, AA, KK to the communicating system). For EIA we join M to E (and connect at least J, F
to the other system.) These configurations are normally done in the cable; see the DL11 manual, tables 3-3 to 3-6.

==Programming interface==

The DL11 has 2 device registers for the receive side (one Control and Status Register - CSR - and one data buffer register), and similarly, two for the transmit side. Each DL11 has two interrupt vectors - again, one receive, and one transmit.

For the PDP-11 main console (which is always a KL11/DL11 compatible device), the 'zeroth' DL11, the standard is that 0777560 is the base address (so the receiver registers are 0777560-2, and the transmitter are 0777564-6), and 060 is the base vector.

The first DL11 after the console is always assigned the address 0776500, and vector 0300. Additional DL11's are assigned addresses and vectors immediately following, for DL11's #1-#16 (i.e. 0776500-676 and 0300-0476).

==Configuration==

The bus address, interrupt vector, and line parameters ([[parity]], number of stop and data bits) were selected by soldered [[jumper]]s; the baud rate was set by a combination of a replaceable crystal (several different ones were standard), and a pair of 10-position dial selectors (one for transmit, one for receive) which selected a rate:

{| class="wikitable"
! Crystal Speed !! 1 !! 2 !! 3 !! 4 !! 5 !! 6 !! 7 !! 8
|-
| 884.8 KHz || 35.7 || 55 || 110 || 220 || 440 || 880 || 1320 || 1760
|-
| 1.033 MHz || 44.8 || 67.3 || 134.5 || 269 || 538 || 1076 || 1614 || 2152
|-
| 1.152 MHz || 50 || 75 || 150 || 300 || 600 || 1200 || 1800 || 2400
|-
| 4.608 MHz || 200 || 300 || 600 || 1200 || 2400 || 4800 || 7200 || 9600
|}

(The 9th and 10th dial selector positions selected external [[clock]] inputs, not divisions of the crystal.)

The address and vector jumpers specify the base of the register bus addresses, and vectors, in binary. On the DL11, it is only possible to set the base of the entire group of 4 registers; the transmit and receive register groups cannot be moved around independently. Similarly for the vector, only the base of the pair of vectors can be configured; the receive (at B) and transmit (at B+4) are paired in the hardware.

The simple rule on the DL11 is that vector jumpers are the inverse of address jumpers: for the vector, jumpers are 'in' for '1', and for the address, they are 'in' for '0'. (This inversion can be a memory jogger - 'Oh, the DL11, that blasted interface where the jumper sense is inverted between address and vector!' Then one only has to look up one of the two.)

Address jumper A3 is the 3rd bit of the address, i.e. the 010 bit, the lowest one that is configurable (the device is a block of 8 bytes, from xxxxx0 to xxxxx7, so it is not possible to set any of the low 3 bits in the base address, they must be 0), and A10 is the highest bit which can be changed. V3 through V8 perform a similar function for the vectors.

The following table shows the bits which are affected when the jumper is '''''in'''''.

{| class="wikitable"
! Address Jumper !! Address Bit !! Vector Jumper !! Vector bit
|-
| A3 || -010 || V3 || +010
|-
| A4 || -020 || V4 || +020
|-
| A5 || -040 || V5 || +040
|-
| A6 || -0100 || V6 || +0100
|-
| A7 || -0200 || V7 || +0200
|-
| A8 || -0400 || V8 || +0400
|-
| A9 || -01000
|-
| A10 || -02000
|}

===Sample configurations===

The following table gives the jumper configuration for the two most common DL11 configurations:
* main console (address 0777560, vector 060)
* 'first' DL11 - often a TU58, now (address 0776500, vector 0300)

{| class="wikitable"
! Jumper !! Bit !! Console !! First DL11
|-
| A3 || 010 || In || In
|-
| A4 || 020 || Out || In
|-
| A5 || 040 || Out || In
|-
| A6 || 0100 || Out || Out
|-
| A7 || 0200 || In || In
|-
| A8 || 0400 || Out || Out
|-
| A9 || 01000 || Out || In
|-
| A10 || 02000 ||Out || Out
|-
| colspan="3" |
|-
| V3 || 010 || Out || Out
|-
| V4 || 020 || In || Out
|-
| V5 || 040 || In || Out
|-
| V6 || 0100 || Out || In
|-
| V7 || 0200 || Out || In
|-
| V8 || 0400 || Out || Out
|}

==Versions==

The DL11 came in 5 versions, -A through -E.

The -A and -C versions (board M7800-YA on at least one of these) were 20mA interface '''only''', and omitted the components necessary for the EIA interface.

The -A and -B apparently did not provide full baud rate selection and selectable data coding (they were restricted to 8-bit data, no parity, and 1 or 2 stop bits); they also could not provide 'split' speeds (differing baud rates on transmit and receive). Apparently, these versions had more limited address selection capability; they could only be configured to 0776XX0, where XX ranged from 050 to 067.

Only the -C through -E could be ordered with the 4th (9600-baud capable) crystal (it is not known whether the earlier ones would work if this crystal were inserted). Only the -E provided full modem control.

The -A and -C versions are easy to identify visually; they are both missing a large number of components (five 14-pin chips including 1488, 1489 which are RS-232 receiver and driver chips).

How to tell the others apart (if, indeed, there is any difference between the -D and -E) is not yet documented.

==See also==

* [[DL11-W serial line unit/real-time clock option]]

==External links==

* [http://www.bitsavers.org/pdf/dec/unibus/EK-DL11-OP-001_Sep76.pdf DL11 asynchronous line interface user's manual] (EK-DL11-OP-001)
* [http://www.bitsavers.org/pdf/dec/unibus/EK-DL11-TM-003_DL11_Asynchronous_Line_Interface_Manual_Sep75.pdf DL11 asynchronous line interface manual] (EK-DL11-TM-003) - technical manual
* [http://www.bitsavers.org/pdf/dec/unibus/DL11_EngrDrws.pdf DL11 asynchronous line interface engineering drawings] - originals
* [http://www.bitsavers.org/pdf/dec/unibus/DL11_schem_Mar78.pdf DL11 asynchronous line interface engineering drawings] - redrawn
* [https://chdickman.com/pdp11/Notes/DL11.shtml Notes: DEC DL11]

[[Category: UNIBUS Asynchronous Serial Interfaces]]

20mA current loop serial line interface

2024-09-26T14:57:21Z

Jonathanjo: fixed typo

The '''20mA current loop serial line interface''' was an early standard (de facto, not formal) electrical system for [[asynchronous serial line]]s between [[terminal]]s and computers. It was made popular by the [[Teletype|Model 33 Teletype]].

Current loop interface, as the name implies, used the presence or absence of a [[current]] to encode signals, rather than [[voltage]] (as used in the [[EIA RS-232 serial line interface]]). The first current loop interfaces used a 60mA current, but this was later reduced to 20mA.

The absence of a current signals space (or high), and the presence of a current is used for mark (low). Thus, in the idle (mark) state (the normal for most lines, most of the time), no power is consumed.

Its main advantages are that it can be used over long distances, and in such applications, line losses are not problematic. Its main disadvantage is that high speeds cannot be used over long distances, as they can with voltage-based systems like RS-232.

=='Active' and 'passive' modes==

A current loop channel has 3 main components; a current source, a switch, and a detector. The component which is the source of the data (the keyboard, in a terminal; the computer, for an output channel, e.g. to the printer of a terminal) will include the switch; the consumer of the data (the printer, in the output channel case) will include the detector.

''Either end of the channel can have the current source''; the term 'active' is usually used to indicate that end. So an 'active receiver' would be one that includes a current source, and similarly an 'active transmitter'. Both receivers and transmitters can also be 'passive'. Normally, in a bi-directional link, both channels will have their active and passive ends at the same end of the link, and so the entire interface is described as 'active' or 'passive'.

[[Category: Serial Lines]]

Motorola

2024-09-02T16:04:49Z

Jonathanjo: Very many people know Motorola for their walkie talkies, CB radios etc

'''Motorola''' was established in 1928. The company created numerous products, for example two-way radios, but in the context of the Computer History Wiki the most interesting products were produced by the [[semiconductor]] division.

* [[MC6800|6800]] 8-bit [[microprocessor]], 1974
* [[Motorola MC68000|68000]] 16/32-bit microprosessor, 1980
* [[M88000|88000]], m88k, 32-bit [[Reduced Instruction Set Computer|RISC]] microprocessor, 1988

Motorola also produced all kinds of [[Transistor-transistor logic|TTL]] [[integrated circuit]]s. Motorola was also the first vendor to produce integrated circuits based on [[Emitter-coupled logic|ECL]], a process originally invented by [[International Business Machines|IBM]].

The original Motorola company was split in 2011. The semiconductor division was separated out before that, into On Semiconductor in 1999. The MC68K architecture is today maintained by [[Freescale]] which was spun off from Motorola in 2004. Freescale itself was acquired by NXP Semiconductors in late 2015, so presumably NXP Semiconductors are now responsible for keeping MC68K alive.

Motorola has also been manufacturing Single Board Computers (SBCs), and still continues to do so. A [[VME]]-based series has been in continuous production since 1988, and are or have been based around MC68K, M88K, and [[PowerPC]] [[Central Processing Unit|CPUs]].

{{semi-stub}}

[[Category: Manufacturers]]
[[Category: Microprocessor Manufacturers]]

John Lions

2024-04-08T08:24:09Z

Jonathanjo: From wanted pages

'''John Lions''' (1937-1998) was a professor of computer science at Adelaide University.

He is most famous for his book ''A Commentary on the Unix Operating System'', and its companion volume ''Unix Operating System Source Code, Level Six'', written in 1976 as teaching material. It covers source code of the Unix kernel, and as such was restricted for many years as part of the copyright and licensing legal processes. It was subsequently reissued as ''Lions' Commentary on UNIX 6th Edition with Source Code'', Peer-to-Peer Communications, 1996, and also widely distributed online.

Bitsavers: https://bitsavers.org/pdf/att/unix/6th_Edition/

Point-to-Point Protocol

2024-04-07T16:38:00Z

Jonathanjo: from wanted list

{{stub}}
'''PPP''' is the '''point-to-point protocol''', part of the [[TCP/IP]] suite. It is a link-level protocol defined in RFC 1134. It was intended to replace to often-used [[SLIP]].

GEC Computers

2024-04-07T16:31:20Z

Jonathanjo: Added GEC Series 63

'''GEC Computers''' was a British computer company, working in the [[real-time]] area. It was created in 1969 by the mergers of the real-time work of [[English Electric Computers]], GEC, AEI, Marconi and [[Elliott-Automation]], to form Marconi Elliott Computer Systems Limited, re-named GEC Computers in 1971. They were a subsidiary of General Electric Company of England.

In the 1980s the company brought out its Series 63 machines, intended to compete with the [[VAX]]; the British Government bought about ten of as part of its [[Alvey Project]], about half of all of those made.

Their products included the [[GEC 4000 Series]] (including the GEC 4080).

{{semi-stub}}

==External links==

* [https://web.archive.org/web/20191219194648/http://www.chilton-computing.org.uk/acd/icf/mums//gec/p005.htm GEC Systems]
* [https://web.archive.org/web/20190729180412/http://www.cucumber.demon.co.uk/geccl/ GEC Computers]
** [https://web.archive.org/web/20191022021346/http://www.cucumber.demon.co.uk/geccl/19471972/index.html GEC Computers - parentage - history, 1947-1972]

[[Category: Manufacturers]]

User:Jonathanjo

2024-04-07T15:30:00Z

Jonathanjo: just a glimpse

Sometime programmer, system manager, system designer; experience with 6809, 68000, VAX, PDP-11, also very many microcontrollers. Many varieties of Unix, writing device drivers and kernel modifications. Writing compilers, assemblers, simulators. Currently restoring some PDP-11 systems.

Turing machine

2024-04-07T12:45:27Z

Jonathanjo: From wanted pages

[[File:Minksy-computation-fig-6.0.1.png|right|thumb|A blank Turing machine from Minsky's ''Computation: Finite and Infinite Machines'']]

A '''Turing Machine''' is a kind of abstract computer, devised by mathematician [[Alan Turing]] in 1936, to develop theories of ''computability'' -- that which can, and which cannot, be computed.

The classic introduction to this kind of machine is MIT professor Marvin Minksy's ''Computation: Finite and Infinite Machines'' (Prentice-Hall 1967):

<blockquote>
A Turing machine is a finite-state machine associated with an external
storage or memory medium. This medium has the form of a sequence of
''squares'', marked of on a linear ''tape''. The machine is couple to the tape
through a ''head'', which is situated, at each moment, on some square of the
tape (see fig). The head has three functions, all of which are exercised
in each operation cycle of the finite-state machine. The functions are:
''reading'' the square of the tape beeing "scanned," ''writing'' on the scanned
square, and ''moving'' the machine to an adjacent square (which becomes the
scanned square in the next operation cycle).
</blockquote>

The basic operation is that each square can have a single symbol from a finite
set of symbols; each step possibly changes the symbol and moves the tape to the
left or the right.

They are comprehensively covered in computing literature, with endless variations, including a large number of physical implementations.

A number of very important theoretical results came from study of these machines:

* A Turing machine is adequate to simulate any other kind of automata, ignoring specified size and speed constraints.
* A machine which can simulate a Turing machine can therefore simulate ''any'' machine and is said to be ''Turing complete''.

File:Minksy-computation-fig-6.0.1.png

2024-04-07T12:40:30Z

Jonathanjo: Diagram of a Turing machine. Figure 6.0.1 from ''Computation: Finite and Infinite Machines'', Marvin Minksy, Prentice-Hall 1967.

Diagram of a Turing machine.
Figure 6.0.1 from ''Computation: Finite and Infinite Machines'', Marvin Minksy, Prentice-Hall 1967.

American National Standards Institute

2024-04-07T12:09:39Z

Jonathanjo: From wanted pages

'''ANSI''' (typically pronounced as an acronym "ann-see") is the '''American National Standards Institute''', a large engineering standards organisation with headquarters in Washington D.C and web site [http://ansi.org ansi.org]. It was founded in 1918.

It is responsible for a number of important standards in computing, including:

* ANSI Standard [[C]], usually called ANSI C, published as X3.159-1989.
* ANSI Standard [[Fortran]], usually called Fortran 66, published as ASA X3.9-1966.
* ANSI Standard [[Cobol]] standards in 1968, 1974, and 1985.
* Expansion of 7-bit [[ASCII]] character set beginning in 1963.

As well as many other general engineering standards with application to historical computers:

* The threads of inch-based machine screws including UNC (coarse) and UNF (fine), used in very many US-designed computers.