Computer History Wiki - User contributions [en]

Western Electric

2022-01-28T23:38:33Z

Mharriger: Added category

Western Electric was the manufacturing arm of the Bell System. They produced nearly everything needed for the telephone system in the United States. Most relevant to this wiki, they produced a series of computers designed to run [[UNIX]] or a real-time version of UNIX called DMERT. At one time many of switches in the US telephone network were controlled by these computers.

[[Category: Manufacturers]]

Western Electric

2022-01-28T23:37:50Z

Mharriger: Created page with "Western Electric was the manufacturing arm of the Bell System. They produced nearly everything needed for the telephone system in the United States. Most relevant to this wiki..."

Category:Computer Manufacturers

2022-01-05T18:18:27Z

Mharriger: Remove NeXT since that page has been created.

This is a category of Computer Manufacturers.

== Manufacturers which should get pages ==
[[Acorn]] -- [[Altos]] -- [[AT&T]] -- [[Coleco]] -- [[Computer Automation]] -- [[Cromemco]] -- [[Epson]] -- [[Exidy]] -- [[Franklin]] --[[Heathkit]] -- [[IBC]] -- [[ICL]] -- [[IMSAI]] -- [[Kaypro]] -- [[Logica VTS]] -- [[MITS]] -- [[Morrow]] -- [[North Star]] -- [[OSBORNE]] -- [[Otrona]] -- [[Polymorphic Systems]] -- [[Processor Technology]] -- [[Psion]] -- [[Radio Shack]] -- [[Sanyo]] -- [[Science of Cambridge]] --[[Sinclair Research]] -- [[SouthWest Technical Products Corporation (SWTPC)]] -- [[Silicon Graphics]] -- [[Tektronix]] -- [[Terak]] -- [[Timex]] (Sinclair) -- [[Vector Graphic]] -- [[Wang]] -- -- [[Zenith]]

[[Category: Manufacturers]]

Tandem Computers

2022-01-05T18:12:11Z

Mharriger: Created page

'''Tandem Computers, Inc.''' was a manufacturer of fault-tolerant computer systems designed to have no single points of failure. Tandem was acquired by Compaq in 1997 and later became a part of HP.

[[Category: Computer Manufacturers]]

Sun Microsystems

2022-01-05T18:06:25Z

Mharriger:

'''Sun Microsystems (Sun)''' was founded in California in 1982. Of relevance to hobbyists include their [[Sun-1]], [[Sun-2]], [[Sun-3]] machines, all based on [[Motorola 68000 family]] [[CPU]]s, early [[SPARC]] based computers and their [[software]] such as [[NFS]], [[SunOS]] and [[Solaris]]. Sun was acquired by Oracle in 2010.

{{stub}}

[[Category: Computer Manufacturers]]

PDP-11 architecture

2022-01-04T03:30:32Z

Mharriger: Fix bad internal link syntax

The '''[[PDP-11]]''' was an influential and widely-used family of 16-[[bit]] [[minicomputer]]s designed by [[Digital Equipment Corporation|DEC]], in production from 1970-1990. Although the basic [[address space]] was 16 bits, most models could hold more [[main memory]] than that, although only a limited subset was visible to the [[program]] at any time.

The [[Central Processing Unit|CPU]] had 8 [[general register|general purpose registers]]; the [[operand]] coding, which was applied regularly across essentially the entire [[instruction set]], allowed it to provide a two-[[address]] instruction [[architecture]], not a simple [[load-store architecture]] like its predecessor, the 12-bit [[PDP-8 family|PDP-8]].

One of the [[register]]s (R7) was dedicated to be the [[Program Counter]], and one (R6) was more or less dedicated to be the [[Stack Pointer]]. (Other registers can be used as [[stack]] [[pointer]]s, but the hardware uses this one for [[subroutine]] call and return, [[interrupt]]s, [[trap]]s, etc.) (There are a number of sometimes poorly-documented details of PDP-11 stack operation; see [[PDP-11 stacks|here]] for more.)

These registers, along with a variety of register-based addressing modes, allowed it to provide a variety of additional operand types, such as immediate (literal) data, absolute and relative addresses, and stack operations; very impressive on a machine which had only 16-bit [[word]]s (and thus [[instruction]]s).

The regular application of the operand coding across essentially the entire instruction set allowed these additional operand types to be widely available; this, and the power of the large range of operand modes, substantially reduced the code size. This was an important consideration both in the PDP-11's early life, when small and expensive [[core memory]] was the standard main memory; and in its later life, when the 16-bit address space became a severe limit.

Most instructions come in both [[byte]] and [[word]] data forms; an exception is ADD and SUB, which exist in only word forms (probably because there was not enough room in the instruction set to have them both in both forms).

On CPU models intended for use in [[time-sharing]] systems, two CPU modes, [[Kernel]] and [[User]], were supported, along with [[memory management]].

Early PDP-11's were all built around the [[UNIBUS]] [[bus]]; later models switched to the [[QBUS]], which used less pins.

==Extensions==

The first PDP-11 (the [[PDP-11/20]]) was limited to one-bit shift operations, and did not have hardware integer multiplication or division, or any hardware [[floating point]]. (An option, the [[KE11-A Extended Arithmetic Element]], did provide multiply, divide, etc in hardware, but it was a separate [[peripheral]] on the UNIBUS, not part of the CPU.)

The next model, the [[PDP-11/45]], added both of these classes (the latter as an option), although the follow-on low-cost machines, the [[PDP-11/05]] and [[PDP-11/04]], again did not have either.

Later machines tended to include the former group - although on some early mid-range machines such as the [[PDP-11/40]] and [[LSI-11s]], they were only an [[PDP-11 Extended Instruction Set|option]]. Floating point was also added to the later machines (although only as an option, until relatively late in the line).

Late in the PDP-11 family's lifetime, a [[Commercial Instruction Set]] was defined, and made available as an [[PDP-11 Commercial Instruction Set|option]] in some of the later machines.

===Floating point===

Two forms of floating point were added: a simplified form, [[FIS floating point]], with only the 4 basic operations, using 32-bit data, in a few early machines; and full-blown floating point (32-bit and 64-bit formats, many operations), [[FP11 floating point]].

The former was available as an option in the PDP-11/40, and later in the PDP-11/03. The latter was available as an option in the [[PDP-11/45]] and variants thereof (the [[PDP-11/50]] and [[PDP-11/55]]), the [[PDP-11/70]], [[PDP-11/34]], [[PDP-11/44]] and [[PDP-11/23]]; it was standard in the [[KDJ11 CPUs]] (although in these machines an optional [[FPJ11 floating point accelerator]] greatly improved the floating point performance).

===Memory management and CPU modes===

After a few disparate custom add-on units to provide memory management and CPU modes in the [[PDP-11/20]], they became [[PDP-11 Memory Management|standardized]] with the PDP-11/45 (in which memory management was an option); most later machines supported them. A simplified version was supported in the -11/40 and -11/23 (as an option, in both), and in the -11/34 (standard) and [[PDP-11/60]] (the lack of the full-blown version was a significant handicap in what was a relatively high-end machine).

==Operands==

The PDP-11 supported both single- and double-operand instructions. The operands are mostly the most flexible form, in which a 6-bit field holds three bits of register number, and three bits of mode. (Which is why PDP-11 [[object code]] is usually displayed in octal, as it is the optimal base for that, since each operand field will be in one octal 'digit'.)

As noted above, this operand form provided a large variety of operand types, including stack push and pop, literals, etc. This provides the basic instruction group with great flexibility, especially the double-operand instructions (MOV, ADD, etc).

A few instructions (mostly those which were added to the instruction repertoire later, e.g. MUL, DIV, XOR, etc) only provide a register number for one operand (i.e. if not already in a register, that operand must be pre-loaded into one by another instruction).

===Addressing modes===

The mode field is further subdivided into a 'Deferred' (indirect) bit, and a two bit field which selects among direct register, auto-increment, auto-decrement, and indexed modes. The indirect bit is the low bit, so odd values of the mode 'digit' are indirect.

The 'regular' modes are:

{| border=1
! Mode !! Name !! Symbolic !! Description
|-
|0 || Register || R || (R) is the operand
|-
|2 || Auto-increment || (R)+ || (R) is the address; (R) is then incremented by 1 or 2, in case of byte or word instructions.
|-
|4 || Auto-decrement || -(R) || (R) is decremented by 1 or 2, in case of byte or word instructions; R is then the address.
|-
|6 || Index || X(R) || (R) + X is the address.
|}

and the indirect modes are:

{| border=1
! Mode !! Name !! Symbolic !! Description
|-
|1 || Register deferred || @R or (R) || (R) contains address of operand
|-
|3 || Auto-increment deferred || @(R)+ || (R) is the address of the address; (R) is then incremented by 2
|-
|5 || Auto-decrement deferred || @-(R) || (R) is decremented by two; (R) is then the address of the address.
|-
|7 || Index deferred || @X(R) || (R) + X is the address of the address
|}

As mentioned, auto-increment and auto-decrement allow any register to be used as a stack pointer, but the hardware enforces the use of R6 as the SP, so it is un-common for another register to be used for this.

Note that when destination operands use auto-increment or auto-decrement mode, the modification is only made on the first use of the operand; the second uses the same address as that used by the first. (This makes sense; the [[microcode]] (or [[state machine]], in the [[KA11 CPU]]) calculates the address of the second operand once, and saves that address in a temporary register - usually, but not necessarily, the Bus Address Register. Then, for the write, it just re-uses that value.)

The use of auto-increment mode with the PC provides literal operands (both immediate, and absolute addresses); indexed modes with the PC can be used for [[location-independent code]].

==Instruction set==

The instruction set provided a number of double-operand instructions:

* MOV
* ADD
* SUB
* BIT (bit test)
* BIS (bit set)
* BIC (bit clear)

(as noted, ADD and SUB are only available in word mode), and many single-operand instructions:

* CLR
* TST (compare with 0)
* INC
* DEC
* NEG
* COM (complement)
* ASR (arithmetic shift right)
* ASL
* ROR (rotate right)
* ROL
* SWAB (swap bytes)
* ADC (add carry)
* SBC

===Condition codes and conditional branches===

The instruction set provided a plethora of branches, although all branches are limited to a range of 127 words before or after the current instruction; a limit which is not onerous in practise. All the [[conditional branch]]es depend on a prior instruction to set 4 [[condition codes]] (stored in the [[Processor Status Word]]):

* Z - Zero
* N - Negative (i.e. high bit set)
* C - Carry
* V - Overflow

Conditional branches:

* BR (un-conditional)
* BNE (non-zero)
* BEQ (zero)
* BMI (negative)
* BPL (positive)
* BVC (overflow clear)
* BVS (overflow)
* BCS (carry)
* BCC (no carry)

Signed branches:

* BGE (greater than or equal to 0)
* BGT
* BLE
* BLT

Unsigned branches:

* BHIS (higher than, or the same)
* BHI
* BLOS
* BLO

===Miscellaneous===

Other flow of control instructions (both JMP and JSR) can transfer to any location in the address space):

* JMP
* JSR - subroutine call
* RTS - subroutine return

A variety of other instructions (e.g. to trap to the [[operating system]], [[halt]] the CPU, etc) also exist.

===Added later===

The PDP-11/45 added a few miscellaneous instructions:

* SOB (decrement and conditionally branch)
* XOR (word only, and also only provides a register number for one operand)
* SXT (sign extend, word only)
* MARK (subroutine argument setup)
* RTT (return from interrupt while inhibiting 'trace' trap)
* SPL (set CPU priority level)

All of these, with the exception of SPL, appeared in all later models (except the -11/05 and -11/04).

Various later models added various instructions for Processor Status Word (PS) access, maintenance, etc.

==Processor Status Word==

All PDP-11's have a Processor Status Word register.The contents vary from model to model, but in all of the it contains the four condition code bits; a bit to control 'trace' traps (which allow [[single-step]]ping the CPU); and the CPU's current [[priority]] level (to allow or defer peripheral interrupts). On models which provide memory management, there are two fields to specify the current and previous [[PDP-11 Memory Management|modes]]. Some models provide two sets of general CPU registers (only one may be in use at any time); a bit in the PSW selects which one is in use.

The layout of the PSW is:
{{16bit-header}}
| colspan=2 | Current Mode || colspan=2 | Previous Mode || Register Set || colspan=3 | ''Unused'' || colspan=3 | Priority || T || N || Z || V || C
{{16bit-bitout}}

Some of the 'unused' bits (above) have uses on particular models; for example, in the -11/44's [[KD11-Z CPU]], bit 8 is used to indicate that a Commercial Instruction Set instruction is in process, but not completed (visible when the PS is saved in an interrupt).

The PSW appears at address 0177776 on most models (0777776 on the UNIBUS, in models with a UNIBUS); the sole exception is the LSI11 CPUs, on which it can only be read/written directly with the MFPS/MTPS instructions (which appear on some, but not all, models).

Depending on the CPU's model (and current mode, for those which support multiple modes), not all bits can be written directly, though. Consult the "PDP-11 Family Differences" appendix, in the ''PDP-11 Architecture Handbook'' (1983-84 version) or the ''MICRO/PDP-11 Handbook'' (1983-84 version) for details.

==Virtualization==

The PDP-11 is impossible to [[virtual machine|virtualize]], since there are a number of instructions used by operating systems which do not trap when executed by a program running in User mode. HALT does trap, but not others, including:

* RESET
* WAIT
* RT[IT]
* SPL
* M[TF]P[ID]
* M[TF]PS

Of these, in user mode RESET is a [[no-op]], RT[IT] cannot change the current and previous modes, MFPI acts like MPFD in User mode when the previous mode is also User (to prevent 'theft' of proprietary code), and MTPS can only set the condition codes.

==See also==

* [[PDP-11 Memory Management]]
* [[PDP-11 Extended Instruction Set]]
* [[PDP-11 Commercial Instruction Set]]
* [[UNIBUS map]]
* [[PDP-11 family differences appendix]]

{{PDP-11}}

[[Category: PDP-11s]]
[[Category: DEC Architectures]]

Intel 80386

2021-12-29T23:23:32Z

Mharriger:

[[Image:80386-12 CPU.jpg|150px|thumb|right|An i386 cpu]]

The '''Intel 80386''' (sometimes '''386''' or '''i386''' for short) is the 4th generation [[microprocessor]] [[Central Processing Unit|CPU]] from [[Intel]] based on the 8088/8086 CPU. The 386 was a 32-bit CPU, featuring all the features of the [[Intel 80286]] CPU, plus 32-bit [[protected mode]] with variable page sizes, allowing for a flat memory space where the entire 4GB of accessible [[Random Access Memory|RAM]] could be accessed without [[segment]]ation. The 386 was introduced in 1985, and finally discontinued in 2007.

The 386 also featured a special mode called v86 which facilitated the creation of [[VDM]]s. In this mode all un-privileged instructions of the 386 could execute in a hardware [[virtual machine]], and privileged instructions would fault.

The real success of this chip was that it made 32-bit software available to the masses, and for bringing 'real' [[Unix]] from the [[VAX]] environment to normal people, via cheap commodity hardware.

== programming ==
The most popular reference is the [[INTEL 80386 PROGRAMMER'S REFERENCE MANUAL]].

== 80386SX ==

The 80386SX was a low cost version of the 386. Instead of having a 32-bit [[address bus]], it was restricted to 24 bits, meaning the 386SX could only address 16MB of RAM maximum. The 386SX also only could transfer data 16 bits at a time, so reading a 32-bit word took two reads. This basically kept the 386SX comparable in speed to the 286. The internal [[register]]s were still 32bit wide, so it could run the same software.

== Trivia ==

The first 386 CPUs had an issue with the multiply [[instruction]] in 32-bit modes, so there had to be a recall on all parts. Later the parts were either stamped "16 bit software only" or with a double sigma sign to certify they would operate correctly.

IBM was not the first to manufacture a PC with the 386 CPU, they were too infatuated with the 286 and the 16-bit version of [[OS/2]] so it was [[Compaq]] who beat them to the first 386-based machine, with the [[Desqpro 386]].

Since there was no 386-specific software at its launch, Compaq pushed [[Microsoft]] to release [[Windows/386]] before Windows 2.0 so that there would be some compelling reason to buy a Compaq 386.

The next CPU in the line of [[Intel x86|x86]] CPUs was the [[Intel 80486]].

{{semi-stub}}

[[Category: Intel Microprocessors]]

Hewlett Packard Precision Architecture

2021-12-29T05:12:22Z

Mharriger: Created page with "Hewlett Packard Precision Architecture, also known as PA-RISC, is a RISC ISA introduced by HP in 1986."

Hewlett Packard Precision Architecture, also known as PA-RISC, is a RISC ISA introduced by HP in 1986.