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KA650 Main Memory System
2020-05-16T16:43:25Z
<p>Jzatarski: added another link to youtube video detailing memory troubleshooting process</p>
<hr />
<div>This page contains notes on troubleshooting, repair, and theory of operation of the [[DEC KA650]]/[[MS650]] memory subsystem.<br />
<br />
==Overview==<br />
<br />
The MS650-AA and MS650-BA memory module are intended to be used with the [[DEC KA650]] [[VAX]] [[CPU]], as the name might suggest. These quad width cards contain 8MB and 16MB of RAM for the VAX, respectively, complete with [[ECC]].<br />
<br />
==Theory of Operation==<br />
<br />
===Memory Controller General Architecture and Organization===<br />
<br />
====Memory Control Signals Provided by the CMCTL====<br />
The CMCTL IC is the [[DRAM]] controller for the KA650 CPU. It has 10 address line outputs, 39 memory data I/O lines (MD), 4 CAS outputs, 4 RAS outputs, a WE pin, and an SE pin. Also available to the RAM card are the inverse of the 20th and 21st address lines (XA20 & XA21), which are used as bank selection when using 256kxX DRAMs. The data lines are provided to the RAM cards through a 50 conductor ribbon cable, while the rest of the control lines are provided through the CD interconnect on the backplane. [[#KA650-print-set|[1]]]<br />
<br />
The 10 address lines carry the row address on the rising edge of a RAS line, followed by the column address on the rising edge of a CAS line.<br />
<br />
The 39 data I/O lines carry the 32 data and 7 ECC bits for the RAM.<br />
<br />
The 4 CAS (Column Address Strobe) lines allow strobing the column address on up to 4 separate memory modules.<br />
<br />
The 4 RAS (Row Address Strobe) lines allow selection of up to 4 banks on a single memory module.<br />
<br />
The WE (Write Enable) pin indicates that the CMCTL is writing to memory, rather than reading.<br />
<br />
The SE (Strobe Enable?) pin seems to indicate that the CMCTL is refreshing memory. This is necessary for the 8MB card to correctly strobe the RAS lines of each bank during a refresh cycle, due to the extra RAS gating circuitry necessary on cards with 256kxX DRAMs.<br />
<br />
The XA20 and XA21 lines are the inverse of the latched address lines from the CDAL bus.<br />
<br />
Note that many of the above control lines are inverse logic from what is normally used to drive DRAMs; in particular, CAS, RAS, and WE lines are inverted from the normal JEDEC DRAM convention of active low /RAS, /CAS, and /WE.<br />
<br />
====Memory Ranks & Banks====<br />
<br />
Due to the 10 bit address bus using conventional multiplexed row and column DRAM addressing, an effective 20 bit address is formed. This allows the CMCTL to address up to 1MWord per rank.<br />
<br />
By strobing different pairings of RAS and CAS (RAS0+CAS0 is one rank, while RAS0+CAS1 is another rank, while RAS1+CAS0 is yet another rank), the CMCTL supports up to 16 ranks of RAM, each 1Mx39. Each rank is thus 4MB of memory once ECC overhead is accounted for. This puts a 64MB cap on the maximum amount of memory the CMCTL can address (16 ranks of 4MB).<br />
<br />
When 256kxX DRAMs are used in place of 1MxX DRAMs, each 1Mx39 rank is further divided into 4 banks of 256kx39. Each bank is selected by XA20 and XA21, which are provided to the RAM cards via the CD interconnect. These address bits appear to only be valid on the rising edge of RAS. Before CAS has strobed, the bits have generally already changed since these are derived from the CDAL bus of the VAX CPU. These bits are used to gate the /RAS lines to the DRAMs ensuring that only the selected bank is addressed. The /CAS line for the card is not affected.<br />
<br />
The MS650-AA card contains 312 256kx1 ZIP DRAMs, organized into 8 banks of 256kx39. As previously mentioned, one memory rank as addressed by the CMCTL memory controller consists of 4 banks, making up a total of 1MWord of memory per rank. Each DRAM on the card corresponds to one bit of the 39 bit word within a 1MB address region of the VAX.<br />
<br />
===Addressing===<br />
<br />
The CMCTL appears to convert 32 bit VAX addresses into DRAM addressing as follows:<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
| A21 || A20 || A19 || A18 || A17 || A16 || A15 || A14 || A13 || A12 || A11 || A10 || A09 || A08 || A07 || A06 || A05 || A04 || A03 || A02<br />
|-<br />
| width=2.5% | R09 <br />
| width=2.5% | <br />
| width=2.5% | R08<br />
| width=2.5% | R07<br />
| width=2.5% | R06<br />
| width=2.5% | R05<br />
| width=2.5% | R04<br />
| width=2.5% | R03<br />
| width=2.5% | R02<br />
| width=2.5% | R01<br />
| width=2.5% | R00<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
|-<br />
| width=2.5% | <br />
| width=2.5% | C09<br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | C08<br />
| width=2.5% | C07<br />
| width=2.5% | C06<br />
| width=2.5% | C05<br />
| width=2.5% | C04<br />
| width=2.5% | C03<br />
| width=2.5% | C02<br />
| width=2.5% | C01<br />
| width=2.5% | C00<br />
|}<br />
<br />
Axx are VAX address lines<br />
Rxx are DRAM row address bits<br />
Cxx are DRAM column address bits<br />
<br />
This addressing scheme is used to ensure that 256kxX DRAMs (which use only 9 bit row and column addresses) are still supported for use with the CMCTL.<br />
<br />
It is, of course, still up to the CMCTL to determine which ranks are selected by the upper bits of a given physical address. This is determined by the MEMCSR0-15 registers, which seem to specify whether or not a bank is present, as well as what base address it resides at. It may perform other functions, but it does not seem to be documented in available documentation.<br />
<br />
===CAS and RAS Signals===<br />
<br />
Each 16MB or 8MB memory card for the KA650 uses one CAS line in its entirety. This is why a maximum of 4 cards may be used in a KA650 system. Each RAM card uses the first CAS line, and passes the remaining lines on to the next card, shifted down one bit. So for example, the first card gets CAS0 CAS1 CAS2 CAS3, in that order. It uses CAS0 and passes CAS1 CAS2 and CAS3 on to the next card, in that order. The next card uses CAS1 and passes on CAS2 and CAS3. This repeats until 4 cards have used up all of the available CAS lines.<br />
<br />
The CAS line is not gated in any way on the MS650-AA. The CAS line is simply buffered, inverted to match the polarity of the DRAMs, and distributed to all DRAMs on the card (likely with some hierarchical buffering methodology).<br />
<br />
RAS lines, on the other hand, are shared between all the cards in the system. The first rank of DRAMs on the card are address by RAS0, the second by RAS1, etc. As previously mentioned, the RAS lines to each bank within a rank are gated on or off by decoding circuitry based on the state of XA20/XA21.<br />
<br />
===Refresh===<br />
<br />
DRAMs are built using one tiny MOS capacitor for each bit. These capacitors leak slightly and need to be periodically refreshed. DRAM rows are refreshed by simply addressing a row. Any row access refreshes that row, no column needs to be strobed for a refresh.<br />
<br />
As such, during refresh cycles, the CMCTL places a row address to be refreshed on the address bus, asserts SE, and asserts all RAS lines for several clock cycles. The purpose of the SE signal is so that RAM cards with 256kxX DRAMs do not gate any of the /RAS lines going to the DRAMs, or else only whatever DRAM bank is (randomly) addressed by XA20 and XA21 would be refreshed.<br />
<br />
===ECC===<br />
<br />
The ECC supported by the CMCTL has the ability to detect and correct single data bit errors, detect single ECC bit errors, and detect double-bit data errors. [[#KA650-technical-manual|[2]]]<br />
<br />
[[ECC]] is generally based on producing parity bits of various collections of data bits. Since parity is based around the simple XOR, it is a linear operation in a manner of speaking. Luckily this means we can determine the ECC equations based on a number of sample data patterns and the respective ECC bits, such as the ECC produced for 0 data, and data with only one bit in the word set. By comparing the ECC for each test pattern to that of 0, we can determine which ECC bits each bit in the data word affects.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| bit || colspan=8 | data || ECC<br />
|-<br />
| || MSB || colspan = 6 | || LSB ||<br />
|-<br />
| - || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0111100<br />
|-<br />
| 0 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 1100100<br />
|-<br />
| 1 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0100000<br />
|-<br />
| 2 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0100110<br />
|-<br />
| 3 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 1100010<br />
|-<br />
| 4 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0100011<br />
|-<br />
| 5 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 1100111<br />
|-<br />
| 6 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 1100001<br />
|-<br />
| 7 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0100101<br />
|-<br />
| 8 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 1010100<br />
|-<br />
| 9 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0010000<br />
|-<br />
| 10 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0010110<br />
|-<br />
| 11 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 1010010<br />
|-<br />
| 12 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0010011<br />
|-<br />
| 13 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 1010111<br />
|-<br />
| 14 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 1010001<br />
|-<br />
| 15 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0010101<br />
|-<br />
| 16 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 1001100<br />
|-<br />
| 17 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0001000<br />
|-<br />
| 18 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0001110<br />
|-<br />
| 19 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 1001010<br />
|-<br />
| 20 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001011<br />
|-<br />
| 21 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001111<br />
|-<br />
| 22 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001001<br />
|-<br />
| 23 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001101<br />
|-<br />
| 24 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000100<br />
|-<br />
| 25 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000000<br />
|-<br />
| 26 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000110<br />
|-<br />
| 27 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000010<br />
|-<br />
| 28 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000011<br />
|-<br />
| 29 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000111<br />
|-<br />
| 30 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000001<br />
|-<br />
| 31 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000101<br />
|}<br />
<br />
<br />
The results of this are depicted below. The basic result is that toggling one of the bits that belongs to the ECC bit group will result in that ECC bit toggling as well.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| ECC bit || colspan=3 | MSB || colspan=26 | || colspan=3 | LSB<br />
|-<br />
|MD32<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|-<br />
|MD33<br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
|-<br />
|MD34<br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
|-<br />
|MD35<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD36<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD37<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|-<br />
|MD38<br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
|}<br />
<br />
An interesting and potentially useful point to note is that flipping bit 28 happens to flip all of the ECC bits together. Another interesting point is that inverting the entire data word produces the same ECC.<br />
<br />
From this information, we can derive some data patterns that produce useful ECC combinations, such as ECC of all zeroes, all ones, only one bit set, and only one bit clear. Looking at the table above, we got lucky and examples of many of these combinations were found by chance. In particular, we happened upon data combinations that produced every possibility of 1 ECC bit set. These, combined with the fact that we can toggle bit 28 to get the inverse ECC bits, gives us a set of data patterns which produce ECC with only one bit clear. From here, we only need to derive a combination which produces all-zero ECC, and from that, derive all-one ECC.<br />
<br />
Starting with the ECC for bit 31 set, we can toggle single bits at a time until we find a combination that produces the ECC we want.<br />
<nowiki><br />
31 1000 0000 0000 0000 0000 0000 0000 0000 1000101<br />
1000 0000 0000 0000 0000 0000 0000 0001 0011101<br />
1000 0000 0000 0000 0000 0010 0000 0001 0110001<br />
1000 0000 1000 0000 0000 0010 0000 0001 0000000 <--<br />
1001 0000 1000 0000 0000 0010 0000 0001 1111111 <--<br />
</nowiki><br />
<br />
The summary of these useful ECC combinations is tabulated below (data in hex, ECC in binary)<br />
<br />
useful ECC combinations:<br />
<br />
{| border=1 style="text-align:center"<br />
| ECC (binary) || data (hex)<br />
|-<br />
| 0000000 || 80800201<br />
|-<br />
| 0000001 || 40000000<br />
|-<br />
| 0000010 || 08000000<br />
|-<br />
| 0000100 || 01000000<br />
|-<br />
| 0001000 || 00020000<br />
|-<br />
| 0010000 || 00000200<br />
|-<br />
| 0100000 || 00000002<br />
|-<br />
| 1000000 || 02000000<br />
|-<br />
| 1111111 || 90800201<br />
|-<br />
| 1111110 || 50000000<br />
|-<br />
| 1111101 || 18000000<br />
|-<br />
| 1111011 || 11000000<br />
|-<br />
| 1110111 || 10020000<br />
|-<br />
| 1101111 || 10000200<br />
|-<br />
| 1011111 || 10000002<br />
|-<br />
| 0111111 || 12000000<br />
|}<br />
<br />
===KA650 Memory Bus Cycles===<br />
<br />
The memory cycles detailed below were captured on an HP 16700A logic analysis system. Memory data and ECC bits were captured, as well as memory address, XA20 and XA21 (inverted back to positive logic by the logic analyzer), the 4 CAS lines, the 4 RAS lines, the WE line, the SE line, the MCLK lines for timing reference. Additionally, the /CAS (DUTCAS), /RAS (DUTRAS), and data line (DUTDATA) of a DRAM located at 0x0XXXXX, bit 0 were captured to show the differences between a selected DRAM and one that was not selected.<br />
<br />
[[File:MS650-AA-Longword-write-same-rank-bank-cycle.png|thumb|none|Longword write cycle]]<br />
<br />
During a longword write cycle, the CMCTL first places the row address onto the memory address bus. Next, it asserts the RAS signal, causing the DRAMs to latch the row address. It then asserts the write enable signal and places the column address on the address bus, then asserts the CAS signal. Lastly, the data and ECC bits are placed on the bus, and some time later CAS deasserts, followed by RAS. On the MS650-AA RAM module, XA20 and XA21 are decoded to determine which bank is selected. Since the DUT being probed here is at address 0x0XXXXX, it is selected during this write.<br />
<br />
[[File:MS650-AA-Longword-write-diff-rank-same-bank-cycle.png|thumb|none|Longword write cycle to a different rank]]<br />
<br />
The CMCTL will assert only the RAS line for the rank which is selected based on the memory address the VAX CPU is accessing. As shown in the next capture, when an address in 0x1XXXXX is written, RAS2 is asserted instead, and thus the DUT being probed was not selected.<br />
<br />
[[File:MS650-AA-Longword-write-same-rank-diff-bank-cycle.png|thumb|none|Longword write cycle to a different bank]]<br />
<br />
Likewise, the MS650-AA decoding circuitry will only allow the RAS line for the bank selected by XA20 and XA21 to be asserted, while ensuring the RAS lines for the other banks are gated off.<br />
<br />
[[File:MS650-AA-byte-write-cycle.png|thumb|none|Byte write cycle]]<br />
<br />
During a byte write cycle, the CMCTL must first read the entire 39 bit word from the MS650, modify the byte which is being written, recalculate the ECC bits, and write the entire 39 bit word back to the MS650. Due to this, both a read and write cycle can be seen within a byte write cycle. Note that the RAS line stays asserted throughout both the read and write parts of the cycle.<br />
<br />
[[File:MS650-AA-qword-write-cycle.png|thumb|none|Quadword write cycle]]<br />
<br />
During a quadword write cycle, two 39 bit words must be written to the MS650. Note that RAS actually cycles twice during this cycle.<br />
<br />
[[File:MS650-AA-read-cycle.png|thumb|none|read cycle]]<br />
<br />
Any read cycle longword or smaller will appear to have the same cycle. Since the MS650 must be read or written as a full 39 bit cycle, there is no effective difference between a byte, word, or longword read. A quadword read, of course, involves reading two 39 bit words, and would thus result in a double cycle similar to the quadword write.<br />
<br />
[[File:MS650-AA-refresh-cycle.png|thumb|none|refresh cycle]]<br />
<br />
Lastly, during a refresh cycle, the SE signal is asserted to force an MS650-AA to allow all banks to be refreshed at once. This would not be necessary for the 1MxX DRAMs on an MS650-BA. Similarly, the CMCTL asserts all RAS lines to load the row to be refreshed into every DRAM connected to the KA650. There is no assertion of CAS since there is no need to actually access a specific location, just to refresh a given row.<br />
<br />
==Memory Connector Pinouts==<br />
<br />
The MS650 boards and KA650 CPU board communicate through the CD interconnect and a 50 pin ribbon cable. The pinouts are available and can be deduced from the KA650 technical manual and field maintenance print set. They are repeated here for ease of use.<br />
<br />
Although the memory card is in a Q-bus form factor, and it has edge connectors for the Q-bus half of the backplane (AB connectors), it does not seem to use any q-bus signals for operation other than power supply pins.<br />
<br />
===Data Bus Connector===<br />
<br />
{| border=1 style="text-align:center"<br />
| pin || signal || pin || signal<br />
|-<br />
| 01 || GND || 26 || D MD10 H<br />
|-<br />
| 02 || D MD9 H || 27 || GND<br />
|-<br />
| 03 || D MD8 H || 28 || D MD29 H<br />
|-<br />
| 04 || D MD7 H || 29 || D MD28 H<br />
|-<br />
| 05 || GND || 30 || D MD27 H<br />
|-<br />
| 06 || D MD6 H || 31 || GND<br />
|-<br />
| 07 || D MD5 H || 32 || D MD26 H<br />
|-<br />
| 08 || D MD4 H || 33 || D MD25 H<br />
|-<br />
| 09 || D MD3 H || 34 || D MD24 H<br />
|-<br />
| 10 || GND || 35 || D MD23 H<br />
|-<br />
| 11 || D MD2 H || 36 || GND<br />
|-<br />
| 12 || D MD1 H || 37 || D MD22 H<br />
|-<br />
| 13 || D MD0 H || 38 || D MD21 H<br />
|-<br />
| 14 || D MD19 H || 39 || D MD20 H<br />
|-<br />
| 15 || GND || 40 || D MD38 H<br />
|-<br />
| 16 || D MD18 H || 41 || GND<br />
|-<br />
| 17 || D MD17 H || 42 || D MD37 H<br />
|-<br />
| 18 || D MD16 H || 43 || D MD36 H<br />
|-<br />
| 19 || D MD15 H || 44 || D MD35 H<br />
|-<br />
| 20 || GND || 45 || D MD34 H<br />
|-<br />
| 21 || D MD14 H || 46 || GND<br />
|-<br />
| 22 || D MD13 H || 47 || D MD33 H<br />
|-<br />
| 23 || D MD12 H || 48 || D MD32 H<br />
|-<br />
| 24 || GND || 49 || D MD31 H<br />
|-<br />
| 25 || D MD11 H || 50 || D MD30 H<br />
|-<br />
|}<br />
<br />
===CD interconnect===<br />
<br />
Note that DEC pin naming conventions follow the [[DEC alphabet]], skipping various letters which could be mistaken for numerals.<br />
<br />
{| border=1 style="text-align:center"<br />
| signal || pin<br />
|-<br />
| MA0 || DB2<br />
|-<br />
| MA1 || DE2<br />
|-<br />
| MA2 || DH2<br />
|-<br />
| MA3 || DJ2<br />
|-<br />
| MA4 || DL2<br />
|-<br />
| MA5 || DM2<br />
|-<br />
| MA6 || DP2<br />
|-<br />
| MA7 || DR2<br />
|-<br />
| MA8 || DS2<br />
|-<br />
| MA9 || DU2<br />
|-<br />
| XA20 || CV2<br />
|-<br />
| XA21 || CU2<br />
|-<br />
| CAS0 || CF2<br />
|-<br />
| CAS1 || CK2<br />
|-<br />
| CAS2 || CN2<br />
|-<br />
| CAS3 || CS2<br />
|-<br />
| RAS0 || CE2<br />
|-<br />
| RAS1 || CJ2<br />
|-<br />
| RAS2 || CM2<br />
|-<br />
| RAS3 || CR2<br />
|-<br />
| WE || CB2<br />
|-<br />
| SE || CA1<br />
|-<br />
|}<br />
<br />
==KA650 VAX Firmware Memory Tests==<br />
<br />
Many of the tests built in to the firmware of the VAX can be quite thorough, if used properly. The tests can be accessed by the TEST command in the monitor, abbreviated to 't'.<br />
<br />
The tests report diagnostic information upon failure, encoded simply as a number of values in registers and memory locations on the stack. With the proper documentation, these values could be decoded to determine the problem. Lacking that documentation, I was able to reverse engineer enough of one test that was failing to understand it's output.<br />
<br />
===TEST 48: MEM_Addr_shrts===<br />
<br />
This test is normally used to check for shorted address lines. It will fill the memory with a pattern first, then it will check each word in order to see if it is still the same pattern. After checking a word, it will check the CMCTL status register to ensure there were no detected errors. Then it will replace the word with another pattern (usually mostly an inverse of the first pattern).<br />
<br />
If any address line is shorted, when the test writes the second pattern, it will affect another location in memory. When that location is encountered, it will read as the wrong data thus showing the issue. However, the test is also capable of detecting stuck bits the way it is designed, and this test happened to find all DRAM errors in my case.<br />
<br />
The output when the test encounters an error looks like the following:<br />
<br />
<nowiki><br />
>>>t 48<br />
<br />
<br />
?48 2 08 FF 00 0002<br />
<br />
P1=00000000 P2=04000000 P3=00000004 P4=00031000 P5=AAAAAAAA<br />
P6=55555555 P7=00000043 P8=200C5875 P9=00000000 P10=2005311F<br />
r0=45555555 r1=000C5860 r2=45555555 r3=00000004 r4=0000006B<br />
r5=AAAAAAAA r6=20080140 r7=20080144 r8=00000000 ERF=80000000<br />
<br />
Normal operation not possible.<br />
<br />
>>><br />
</nowiki><br />
<br />
I figured out the meaning of some of these registers for this test. First of all, P10 indicates an address where presumably DEC personnel would check a source listing to find out the exact meaning of the rest of the values shown. The meanings of the registers I have found are only valid for this routine, located near 2005311F.<br />
<br />
{| border=1 style="text-align:center"<br />
| register || description<br />
|-<br />
| r0 || contents of memory at address being tested<br />
|-<br />
| r1 || address being tested<br />
|-<br />
| r2 || expected pattern from memory being tested<br />
|-<br />
| r5 || pattern to replace location with<br />
|-<br />
| r6 || address of CMCTL MEMCSR16 (a diagnostic register)<br />
|-<br />
| P8 || contents of MEMCSR16<br />
|}<br />
<br />
==MEMCSR16 Register==<br />
<br />
The MEMCSR16 register gives us information on what kind of memory failure<br />
occurred. The bit meanings are as follows, according to the KA650 technical manual:<br />
<br />
{| border=1 style="text-align:center"<br />
| bits || description<br />
|-<br />
| <31> || set if uncorrectable error occurred<br />
|-<br />
| <30> || set if multiple uncorrectable errors occurred<br />
|-<br />
| <29> || set if correctable error occurred<br />
|-<br />
| <28:9> || page address where error occurred (pages are 512 bytes)<br />
|-<br />
| <8> || set if error ocurred during DMA<br />
|-<br />
| <7> || set if CDAL bus parity error occurred<br />
|-<br />
| <6:0> || error syndrome: a unique combination is produced here for each possible single bit error<br />
|}<br />
<br />
writing 1s to bits 31, 30, 29, 8, or 7 of MEMCSR16 resets those bits. bits 28:9 and 6:0 are read only.<br />
<br />
The MEMCSR registers can be read with test 9c.<br />
<br />
===Error Syndrome Field===<br />
<br />
The error syndrome is particularly useful for troubleshooting memory errors as it can tell us exactly which bit had the error. A list of the syndromes and the corresponding bit error is given below.<br />
<br />
{| border=1 style="text-align:center"<br />
| syndrome || bit position or error description<br />
|-<br />
| 0000000 || no error<br />
|-<br />
| 0000001 || 32<br />
|-<br />
| 0000010 || 33<br />
|-<br />
| 0000100 || 34<br />
|-<br />
| 0000111 || result of incorrect check bits written on CDAL parity error<br />
|-<br />
| 0001000 || 35<br />
|-<br />
| 0010000 || 36<br />
|-<br />
| 0011001 || 7<br />
|-<br />
| 0011010 || 2<br />
|-<br />
| 0011100 || 1<br />
|-<br />
| 0011111 || 4<br />
|-<br />
| 0100000 || 37<br />
|-<br />
| 0101001 || 15<br />
|-<br />
| 0101010 || 10<br />
|-<br />
| 0101100 || 9<br />
|-<br />
| 0101111 || 12<br />
|-<br />
| 0110001 || 23<br />
|-<br />
| 0110010 || 18<br />
|-<br />
| 0110100 || 17<br />
|-<br />
| 0110111 || 20<br />
|-<br />
| 0111000 || 24<br />
|-<br />
| 0111011 || 29<br />
|-<br />
| 0111101 || 30<br />
|-<br />
| 0111110 || 27<br />
|-<br />
| 1000000 || 38<br />
|-<br />
| 1011000 || 0<br />
|-<br />
| 1011011 || 5<br />
|-<br />
| 1011101 || 6<br />
|-<br />
| 1011110 || 3<br />
|-<br />
| 1101000 || 8<br />
|-<br />
| 1101011 || 13<br />
|-<br />
| 1101101 || 14<br />
|-<br />
| 1101110 || 11<br />
|-<br />
| 1110000 || 16<br />
|-<br />
| 1110011 || 21<br />
|-<br />
| 1110101 || 22<br />
|-<br />
| 1110110 || 19<br />
|-<br />
| 1111001 || 31<br />
|-<br />
| 1111010 || 26<br />
|-<br />
| 1111100 || 25<br />
|-<br />
| 1111111 || 28<br />
|-<br />
| other || multibit error<br />
|}<br />
<br />
==Troubleshooting==<br />
<br />
We now have all of the information necessary to narrow down which bits in which address regions are bad. However, that doesn't do any good for repair unless we also know which physical DRAMs that bit and region correspond to.<br />
<br />
===MS650-AA===<br />
<br />
Shown below is a diagram of the MS650-AA RAM card, broken up into 11 columns and 37 rows. Each spot in this grid contains up to 1 DRAM, but some locations contain other circuitry instead.<br />
<br />
<nowiki><br />
<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
--------------------------------------------------------------------------------<br />
01 | ooooooooooooooooooooooooo |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 01<br />
| --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
08 | --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 08<br />
|-------------------------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
09 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 09<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
16 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 16<br />
17 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 17<br />
18 |DDDDDDD|TTTTTTT TTTTTTTTT TTTTTTTT |DDDDDDDDDDDDD|TTTTTTTT TTTTTTTTT TTTTTTTT | 18<br />
19 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 19<br />
20 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 20<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
32 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 32<br />
33 |DDDDDDD-----------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 33<br />
36 |DDDDDDD| PPPPPPP TTTTT TTTTT |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 35<br />
37 |-------- TTTTTTT TTTTTTT --------DDDDDDDDDDDDDD-------DDDDDDDDDDDDDD| 37<br />
| -------------- --------------| <br />
| ___- - ___- |<br />
| | | || | | |<br />
-------------------- ----------------------------------------------------------<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
<br />
-----------------------------------------------<br />
| D DRAMS |<br />
| T TTL IC |<br />
| B some kind of DEC custom fast data buffer? |<br />
| P PAL16L8 |<br />
| o data connector |<br />
| | border |<br />
| - border |<br />
-----------------------------------------------<br />
<br />
</nowiki><br />
<br />
The MS650-AA RAM card uses two RAS lines. During normal initialization of the VAX, the rank connected to RAS0 will be first in memory, followed by the rank connected to RAS1. Presumably, the MS650-BA card would have 4 ranks.<br />
<br />
RAS0 - first 4MB<br />
RAS1 - second 4MB<br />
<br />
Based on the bit with the error, as well as the memory region where the error occurred, the specific DRAM with the failure can be found and replaced.<br />
<br />
Below is a list of the DRAMs sorted by memory region and bit, showing the grid location of the DRAM IC.<br />
<br />
By using the built in tests, along with MEMCSR16, and perhaps some manual DEPOSIT and EXAMINE testing, the bad DRAM should be possible to locate and then, using this table, the DRAM can be replaced.<br />
<br />
{| border=1 style="text-align:center"<br />
| DRAM || Address || data bit<br />
|-<br />
| A12 || 0XXXXX || MD00<br />
|-<br />
| A11 || 1XXXXX || MD00<br />
|-<br />
| A10 || 2XXXXX || MD00<br />
|-<br />
| A09 || 3XXXXX || MD00<br />
|-<br />
| A16 || 4XXXXX || MD00<br />
|-<br />
| A15 || 5XXXXX || MD00<br />
|-<br />
| A14 || 6XXXXX || MD00<br />
|-<br />
| A13 || 7XXXXX || MD00<br />
|-<br />
| A24 || 0XXXXX || MD01<br />
|-<br />
| A23 || 1XXXXX || MD01<br />
|-<br />
| A22 || 2XXXXX || MD01<br />
|-<br />
| A21 || 3XXXXX || MD01<br />
|-<br />
| A20 || 4XXXXX || MD01<br />
|-<br />
| A19 || 5XXXXX || MD01<br />
|-<br />
| A18 || 6XXXXX || MD01<br />
|-<br />
| A17 || 7XXXXX || MD01<br />
|-<br />
| A32 || 0XXXXX || MD02<br />
|-<br />
| A31 || 1XXXXX || MD02<br />
|-<br />
| A30 || 2XXXXX || MD02<br />
|-<br />
| A29 || 3XXXXX || MD02<br />
|-<br />
| A28 || 4XXXXX || MD02<br />
|-<br />
| A27 || 5XXXXX || MD02<br />
|-<br />
| A26 || 6XXXXX || MD02<br />
|-<br />
| A25 || 7XXXXX || MD02<br />
|-<br />
| B12 || 0XXXXX || MD03<br />
|-<br />
| B11 || 1XXXXX || MD03<br />
|-<br />
| B10 || 2XXXXX || MD03<br />
|-<br />
| B09 || 3XXXXX || MD03<br />
|-<br />
| A36 || 4XXXXX || MD03<br />
|-<br />
| A35 || 5XXXXX || MD03<br />
|-<br />
| A34 || 6XXXXX || MD03<br />
|-<br />
| A33 || 7XXXXX || MD03<br />
|-<br />
| B24 || 0XXXXX || MD04<br />
|-<br />
| B23 || 1XXXXX || MD04<br />
|-<br />
| B22 || 2XXXXX || MD04<br />
|-<br />
| B21 || 3XXXXX || MD04<br />
|-<br />
| B16 || 4XXXXX || MD04<br />
|-<br />
| B15 || 5XXXXX || MD04<br />
|-<br />
| B14 || 6XXXXX || MD04<br />
|-<br />
| B13 || 7XXXXX || MD04<br />
|-<br />
| B32 || 0XXXXX || MD05<br />
|-<br />
| B31 || 1XXXXX || MD05<br />
|-<br />
| B30 || 2XXXXX || MD05<br />
|-<br />
| B29 || 3XXXXX || MD05<br />
|-<br />
| B28 || 4XXXXX || MD05<br />
|-<br />
| B27 || 5XXXXX || MD05<br />
|-<br />
| B26 || 6XXXXX || MD05<br />
|-<br />
| B25 || 7XXXXX || MD05<br />
|-<br />
| C12 || 0XXXXX || MD06<br />
|-<br />
| C11 || 1XXXXX || MD06<br />
|-<br />
| C10 || 2XXXXX || MD06<br />
|-<br />
| C09 || 3XXXXX || MD06<br />
|-<br />
| C16 || 4XXXXX || MD06<br />
|-<br />
| C15 || 5XXXXX || MD06<br />
|-<br />
| C14 || 6XXXXX || MD06<br />
|-<br />
| C13 || 7XXXXX || MD06<br />
|-<br />
| C24 || 0XXXXX || MD07<br />
|-<br />
| C23 || 1XXXXX || MD07<br />
|-<br />
| C22 || 2XXXXX || MD07<br />
|-<br />
| C21 || 3XXXXX || MD07<br />
|-<br />
| E20 || 4XXXXX || MD07<br />
|-<br />
| D20 || 5XXXXX || MD07<br />
|-<br />
| C20 || 6XXXXX || MD07<br />
|-<br />
| B20 || 7XXXXX || MD07<br />
|-<br />
| C32 || 0XXXXX || MD08<br />
|-<br />
| C31 || 1XXXXX || MD08<br />
|-<br />
| C30 || 2XXXXX || MD08<br />
|-<br />
| C29 || 3XXXXX || MD08<br />
|-<br />
| C28 || 4XXXXX || MD08<br />
|-<br />
| C27 || 5XXXXX || MD08<br />
|-<br />
| C26 || 6XXXXX || MD08<br />
|-<br />
| C25 || 7XXXXX || MD08<br />
|-<br />
| D32 || 0XXXXX || MD09<br />
|-<br />
| D31 || 1XXXXX || MD09<br />
|-<br />
| D30 || 2XXXXX || MD09<br />
|-<br />
| D29 || 3XXXXX || MD09<br />
|-<br />
| D28 || 4XXXXX || MD09<br />
|-<br />
| D27 || 5XXXXX || MD09<br />
|-<br />
| D26 || 6XXXXX || MD09<br />
|-<br />
| D25 || 7XXXXX || MD09<br />
|-<br />
| D24 || 0XXXXX || MD10<br />
|-<br />
| D23 || 1XXXXX || MD10<br />
|-<br />
| D22 || 2XXXXX || MD10<br />
|-<br />
| D21 || 3XXXXX || MD10<br />
|-<br />
| D16 || 4XXXXX || MD10<br />
|-<br />
| D15 || 5XXXXX || MD10<br />
|-<br />
| D14 || 6XXXXX || MD10<br />
|-<br />
| D13 || 7XXXXX || MD10<br />
|-<br />
| D12 || 0XXXXX || MD11<br />
|-<br />
| D11 || 1XXXXX || MD11<br />
|-<br />
| D10 || 2XXXXX || MD11<br />
|-<br />
| D09 || 3XXXXX || MD11<br />
|-<br />
| E16 || 4XXXXX || MD11<br />
|-<br />
| E15 || 5XXXXX || MD11<br />
|-<br />
| E14 || 6XXXXX || MD11<br />
|-<br />
| E13 || 7XXXXX || MD11<br />
|-<br />
| E12 || 0XXXXX || MD12<br />
|-<br />
| E11 || 1XXXXX || MD12<br />
|-<br />
| E10 || 2XXXXX || MD12<br />
|-<br />
| E09 || 3XXXXX || MD12<br />
|-<br />
| E28 || 4XXXXX || MD12<br />
|-<br />
| E27 || 5XXXXX || MD12<br />
|-<br />
| E26 || 6XXXXX || MD12<br />
|-<br />
| E25 || 7XXXXX || MD12<br />
|-<br />
| E24 || 0XXXXX || MD13<br />
|-<br />
| E23 || 1XXXXX || MD13<br />
|-<br />
| E22 || 2XXXXX || MD13<br />
|-<br />
| E21 || 3XXXXX || MD13<br />
|-<br />
| F16 || 4XXXXX || MD13<br />
|-<br />
| F15 || 5XXXXX || MD13<br />
|-<br />
| F14 || 6XXXXX || MD13<br />
|-<br />
| F13 || 7XXXXX || MD13<br />
|-<br />
| E32 || 0XXXXX || MD14<br />
|-<br />
| E31 || 1XXXXX || MD14<br />
|-<br />
| E30 || 2XXXXX || MD14<br />
|-<br />
| E29 || 3XXXXX || MD14<br />
|-<br />
| F20 || 4XXXXX || MD14<br />
|-<br />
| F19 || 5XXXXX || MD14<br />
|-<br />
| F18 || 6XXXXX || MD14<br />
|-<br />
| F17 || 7XXXXX || MD14<br />
|-<br />
| F32 || 0XXXXX || MD15<br />
|-<br />
| F31 || 1XXXXX || MD15<br />
|-<br />
| F30 || 2XXXXX || MD15<br />
|-<br />
| F29 || 3XXXXX || MD15<br />
|-<br />
| F28 || 4XXXXX || MD15<br />
|-<br />
| F27 || 5XXXXX || MD15<br />
|-<br />
| F26 || 6XXXXX || MD15<br />
|-<br />
| F25 || 7XXXXX || MD15<br />
|-<br />
| F24 || 0XXXXX || MD16<br />
|-<br />
| F23 || 1XXXXX || MD16<br />
|-<br />
| F22 || 2XXXXX || MD16<br />
|-<br />
| F21 || 3XXXXX || MD16<br />
|-<br />
| F36 || 4XXXXX || MD16<br />
|-<br />
| F35 || 5XXXXX || MD16<br />
|-<br />
| F34 || 6XXXXX || MD16<br />
|-<br />
| F33 || 7XXXXX || MD16<br />
|-<br />
| G32 || 0XXXXX || MD17<br />
|-<br />
| G31 || 1XXXXX || MD17<br />
|-<br />
| G30 || 2XXXXX || MD17<br />
|-<br />
| G29 || 3XXXXX || MD17<br />
|-<br />
| G36 || 4XXXXX || MD17<br />
|-<br />
| G35 || 5XXXXX || MD17<br />
|-<br />
| G34 || 6XXXXX || MD17<br />
|-<br />
| G33 || 7XXXXX || MD17<br />
|-<br />
| G24 || 0XXXXX || MD18<br />
|-<br />
| G23 || 1XXXXX || MD18<br />
|-<br />
| G22 || 2XXXXX || MD18<br />
|-<br />
| G21 || 3XXXXX || MD18<br />
|-<br />
| G28 || 4XXXXX || MD18<br />
|-<br />
| G27 || 5XXXXX || MD18<br />
|-<br />
| G26 || 6XXXXX || MD18<br />
|-<br />
| G25 || 7XXXXX || MD18<br />
|-<br />
| H32 || 0XXXXX || MD19<br />
|-<br />
| H31 || 1XXXXX || MD19<br />
|-<br />
| H30 || 2XXXXX || MD19<br />
|-<br />
| H29 || 3XXXXX || MD19<br />
|-<br />
| G20 || 4XXXXX || MD19<br />
|-<br />
| G19 || 5XXXXX || MD19<br />
|-<br />
| G18 || 6XXXXX || MD19<br />
|-<br />
| G17 || 7XXXXX || MD19<br />
|-<br />
| H24 || 0XXXXX || MD20<br />
|-<br />
| H23 || 1XXXXX || MD20<br />
|-<br />
| H22 || 2XXXXX || MD20<br />
|-<br />
| H21 || 3XXXXX || MD20<br />
|-<br />
| K37 || 4XXXXX || MD20<br />
|-<br />
| J37 || 5XXXXX || MD20<br />
|-<br />
| H37 || 6XXXXX || MD20<br />
|-<br />
| G37 || 7XXXXX || MD20<br />
|-<br />
| I32 || 0XXXXX || MD21<br />
|-<br />
| I31 || 1XXXXX || MD21<br />
|-<br />
| I30 || 2XXXXX || MD21<br />
|-<br />
| I29 || 3XXXXX || MD21<br />
|-<br />
| H36 || 4XXXXX || MD21<br />
|-<br />
| H35 || 5XXXXX || MD21<br />
|-<br />
| H34 || 6XXXXX || MD21<br />
|-<br />
| H33 || 7XXXXX || MD21<br />
|-<br />
| I24 || 0XXXXX || MD22<br />
|-<br />
| I23 || 1XXXXX || MD22<br />
|-<br />
| I22 || 2XXXXX || MD22<br />
|-<br />
| I21 || 3XXXXX || MD22<br />
|-<br />
| H28 || 4XXXXX || MD22<br />
|-<br />
| H27 || 5XXXXX || MD22<br />
|-<br />
| H26 || 6XXXXX || MD22<br />
|-<br />
| H25 || 7XXXXX || MD22<br />
|-<br />
| J32 || 0XXXXX || MD23<br />
|-<br />
| J31 || 1XXXXX || MD23<br />
|-<br />
| J30 || 2XXXXX || MD23<br />
|-<br />
| J29 || 3XXXXX || MD23<br />
|-<br />
| I36 || 4XXXXX || MD23<br />
|-<br />
| I35 || 5XXXXX || MD23<br />
|-<br />
| I34 || 6XXXXX || MD23<br />
|-<br />
| I33 || 7XXXXX || MD23<br />
|-<br />
| J24 || 0XXXXX || MD24<br />
|-<br />
| J23 || 1XXXXX || MD24<br />
|-<br />
| J22 || 2XXXXX || MD24<br />
|-<br />
| J21 || 3XXXXX || MD24<br />
|-<br />
| I28 || 4XXXXX || MD24<br />
|-<br />
| I27 || 5XXXXX || MD24<br />
|-<br />
| I26 || 6XXXXX || MD24<br />
|-<br />
| I25 || 7XXXXX || MD24<br />
|-<br />
| K32 || 0XXXXX || MD25<br />
|-<br />
| K31 || 1XXXXX || MD25<br />
|-<br />
| K30 || 2XXXXX || MD25<br />
|-<br />
| K29 || 3XXXXX || MD25<br />
|-<br />
| J36 || 4XXXXX || MD25<br />
|-<br />
| J35 || 5XXXXX || MD25<br />
|-<br />
| J34 || 6XXXXX || MD25<br />
|-<br />
| J33 || 7XXXXX || MD25<br />
|-<br />
| K24 || 0XXXXX || MD26<br />
|-<br />
| K23 || 1XXXXX || MD26<br />
|-<br />
| K22 || 2XXXXX || MD26<br />
|-<br />
| K21 || 3XXXXX || MD26<br />
|-<br />
| J28 || 4XXXXX || MD26<br />
|-<br />
| J27 || 5XXXXX || MD26<br />
|-<br />
| J26 || 6XXXXX || MD26<br />
|-<br />
| J25 || 7XXXXX || MD26<br />
|-<br />
| K20 || 0XXXXX || MD27<br />
|-<br />
| J20 || 1XXXXX || MD27<br />
|-<br />
| I20 || 2XXXXX || MD27<br />
|-<br />
| H20 || 3XXXXX || MD27<br />
|-<br />
| K36 || 4XXXXX || MD27<br />
|-<br />
| K35 || 5XXXXX || MD27<br />
|-<br />
| K34 || 6XXXXX || MD27<br />
|-<br />
| K33 || 7XXXXX || MD27<br />
|-<br />
| F12 || 0XXXXX || MD28<br />
|-<br />
| F11 || 1XXXXX || MD28<br />
|-<br />
| F10 || 2XXXXX || MD28<br />
|-<br />
| F09 || 3XXXXX || MD28<br />
|-<br />
| K28 || 4XXXXX || MD28<br />
|-<br />
| K26 || 6XXXXX || MD28<br />
|-<br />
| K27 || 5XXXXX || MD28<br />
|-<br />
| K25 || 7XXXXX || MD28<br />
|-<br />
| G12 || 0XXXXX || MD29<br />
|-<br />
| G11 || 1XXXXX || MD29<br />
|-<br />
| G10 || 2XXXXX || MD29<br />
|-<br />
| G09 || 3XXXXX || MD29<br />
|-<br />
| G16 || 4XXXXX || MD29<br />
|-<br />
| G15 || 5XXXXX || MD29<br />
|-<br />
| G14 || 6XXXXX || MD29<br />
|-<br />
| G13 || 7XXXXX || MD29<br />
|-<br />
| G04 || 0XXXXX || MD30<br />
|-<br />
| G03 || 1XXXXX || MD30<br />
|-<br />
| G02 || 2XXXXX || MD30<br />
|-<br />
| G01 || 3XXXXX || MD30<br />
|-<br />
| G08 || 4XXXXX || MD30<br />
|-<br />
| G07 || 5XXXXX || MD30<br />
|-<br />
| G06 || 6XXXXX || MD30<br />
|-<br />
| G05 || 7XXXXX || MD30<br />
|-<br />
| H04 || 0XXXXX || MD31<br />
|-<br />
| H03 || 1XXXXX || MD31<br />
|-<br />
| H02 || 2XXXXX || MD31<br />
|-<br />
| H01 || 3XXXXX || MD31<br />
|-<br />
| H08 || 4XXXXX || MD31<br />
|-<br />
| H07 || 5XXXXX || MD31<br />
|-<br />
| H06 || 6XXXXX || MD31<br />
|-<br />
| H05 || 7XXXXX || MD31<br />
|-<br />
| H12 || 0XXXXX || MD32<br />
|-<br />
| H11 || 1XXXXX || MD32<br />
|-<br />
| H10 || 2XXXXX || MD32<br />
|-<br />
| H09 || 3XXXXX || MD32<br />
|-<br />
| H16 || 4XXXXX || MD32<br />
|-<br />
| H15 || 5XXXXX || MD32<br />
|-<br />
| H14 || 6XXXXX || MD32<br />
|-<br />
| H13 || 7XXXXX || MD32<br />
|-<br />
| I04 || 0XXXXX || MD33<br />
|-<br />
| I03 || 1XXXXX || MD33<br />
|-<br />
| I02 || 2XXXXX || MD33<br />
|-<br />
| I01 || 3XXXXX || MD33<br />
|-<br />
| I08 || 4XXXXX || MD33<br />
|-<br />
| I07 || 5XXXXX || MD33<br />
|-<br />
| I06 || 6XXXXX || MD33<br />
|-<br />
| I05 || 7XXXXX || MD33<br />
|-<br />
| I12 || 0XXXXX || MD34<br />
|-<br />
| I11 || 1XXXXX || MD34<br />
|-<br />
| I10 || 2XXXXX || MD34<br />
|-<br />
| I09 || 3XXXXX || MD34<br />
|-<br />
| I16 || 4XXXXX || MD34<br />
|-<br />
| I15 || 5XXXXX || MD34<br />
|-<br />
| I14 || 6XXXXX || MD34<br />
|-<br />
| I13 || 7XXXXX || MD34<br />
|-<br />
| J04 || 0XXXXX || MD35<br />
|-<br />
| J03 || 1XXXXX || MD35<br />
|-<br />
| J02 || 2XXXXX || MD35<br />
|-<br />
| J01 || 3XXXXX || MD35<br />
|-<br />
| J08 || 4XXXXX || MD35<br />
|-<br />
| J07 || 5XXXXX || MD35<br />
|-<br />
| J06 || 6XXXXX || MD35<br />
|-<br />
| J05 || 7XXXXX || MD35<br />
|-<br />
| J12 || 0XXXXX || MD36<br />
|-<br />
| J11 || 1XXXXX || MD36<br />
|-<br />
| J10 || 2XXXXX || MD36<br />
|-<br />
| J09 || 3XXXXX || MD36<br />
|-<br />
| J16 || 4XXXXX || MD36<br />
|-<br />
| J15 || 5XXXXX || MD36<br />
|-<br />
| J14 || 6XXXXX || MD36<br />
|-<br />
| J13 || 7XXXXX || MD36<br />
|-<br />
| K04 || 0XXXXX || MD37<br />
|-<br />
| K03 || 1XXXXX || MD37<br />
|-<br />
| K02 || 2XXXXX || MD37<br />
|-<br />
| K01 || 3XXXXX || MD37<br />
|-<br />
| K08 || 4XXXXX || MD37<br />
|-<br />
| K07 || 5XXXXX || MD37<br />
|-<br />
| K06 || 6XXXXX || MD37<br />
|-<br />
| K05 || 7XXXXX || MD37<br />
|-<br />
| K12 || 0XXXXX || MD38<br />
|-<br />
| K11 || 1XXXXX || MD38<br />
|-<br />
| K10 || 2XXXXX || MD38<br />
|-<br />
| K09 || 3XXXXX || MD38<br />
|-<br />
| K16 || 4XXXXX || MD38<br />
|-<br />
| K15 || 5XXXXX || MD38<br />
|-<br />
| K14 || 6XXXXX || MD38<br />
|-<br />
| K13 || 7XXXXX || MD38<br />
|}<br />
<br />
===MS650-BA===<br />
<br />
Because I did not have an MS650-BA to test, I do not have as much information on this module as on the MS650-AA. Presumably, the MS650-BA has 4 ranks of 4MB in 1MBxX DRAMs, meaning there is no need to have 4 banks in each rank like the 256kx1 DRAMs on the MS650-AA.<br />
<br />
==External Links==<br />
<br />
* [https://youtu.be/eDMhdAEFEgc Youtube - KA650 Memory Troubleshooting]<br />
* [https://youtu.be/3LxTJIzow2k Youtube - VAXStation 3200: More RAM Repair]<br />
<br />
==References==<br />
<br />
<div id="KA650-print-set">[1] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="KA650-technical-manual">[2] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div><br />
<br />
[[Category: VAXen]]<br />
[[Category: DEC Memories]]</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_Main_Memory_System&diff=22294
KA650 Main Memory System
2020-05-16T14:02:49Z
<p>Jzatarski: added pinout information</p>
<hr />
<div>This page contains notes on troubleshooting, repair, and theory of operation of the [[DEC KA650]]/[[MS650]] memory subsystem.<br />
<br />
==Overview==<br />
<br />
The MS650-AA and MS650-BA memory module are intended to be used with the [[DEC KA650]] [[VAX]] [[CPU]], as the name might suggest. These quad width cards contain 8MB and 16MB of RAM for the VAX, respectively, complete with [[ECC]].<br />
<br />
==Theory of Operation==<br />
<br />
===Memory Controller General Architecture and Organization===<br />
<br />
====Memory Control Signals Provided by the CMCTL====<br />
The CMCTL IC is the [[DRAM]] controller for the KA650 CPU. It has 10 address line outputs, 39 memory data I/O lines (MD), 4 CAS outputs, 4 RAS outputs, a WE pin, and an SE pin. Also available to the RAM card are the inverse of the 20th and 21st address lines (XA20 & XA21), which are used as bank selection when using 256kxX DRAMs. The data lines are provided to the RAM cards through a 50 conductor ribbon cable, while the rest of the control lines are provided through the CD interconnect on the backplane. [[#KA650-print-set|[1]]]<br />
<br />
The 10 address lines carry the row address on the rising edge of a RAS line, followed by the column address on the rising edge of a CAS line.<br />
<br />
The 39 data I/O lines carry the 32 data and 7 ECC bits for the RAM.<br />
<br />
The 4 CAS (Column Address Strobe) lines allow strobing the column address on up to 4 separate memory modules.<br />
<br />
The 4 RAS (Row Address Strobe) lines allow selection of up to 4 banks on a single memory module.<br />
<br />
The WE (Write Enable) pin indicates that the CMCTL is writing to memory, rather than reading.<br />
<br />
The SE (Strobe Enable?) pin seems to indicate that the CMCTL is refreshing memory. This is necessary for the 8MB card to correctly strobe the RAS lines of each bank during a refresh cycle, due to the extra RAS gating circuitry necessary on cards with 256kxX DRAMs.<br />
<br />
The XA20 and XA21 lines are the inverse of the latched address lines from the CDAL bus.<br />
<br />
Note that many of the above control lines are inverse logic from what is normally used to drive DRAMs; in particular, CAS, RAS, and WE lines are inverted from the normal JEDEC DRAM convention of active low /RAS, /CAS, and /WE.<br />
<br />
====Memory Ranks & Banks====<br />
<br />
Due to the 10 bit address bus using conventional multiplexed row and column DRAM addressing, an effective 20 bit address is formed. This allows the CMCTL to address up to 1MWord per rank.<br />
<br />
By strobing different pairings of RAS and CAS (RAS0+CAS0 is one rank, while RAS0+CAS1 is another rank, while RAS1+CAS0 is yet another rank), the CMCTL supports up to 16 ranks of RAM, each 1Mx39. Each rank is thus 4MB of memory once ECC overhead is accounted for. This puts a 64MB cap on the maximum amount of memory the CMCTL can address (16 ranks of 4MB).<br />
<br />
When 256kxX DRAMs are used in place of 1MxX DRAMs, each 1Mx39 rank is further divided into 4 banks of 256kx39. Each bank is selected by XA20 and XA21, which are provided to the RAM cards via the CD interconnect. These address bits appear to only be valid on the rising edge of RAS. Before CAS has strobed, the bits have generally already changed since these are derived from the CDAL bus of the VAX CPU. These bits are used to gate the /RAS lines to the DRAMs ensuring that only the selected bank is addressed. The /CAS line for the card is not affected.<br />
<br />
The MS650-AA card contains 312 256kx1 ZIP DRAMs, organized into 8 banks of 256kx39. As previously mentioned, one memory rank as addressed by the CMCTL memory controller consists of 4 banks, making up a total of 1MWord of memory per rank. Each DRAM on the card corresponds to one bit of the 39 bit word within a 1MB address region of the VAX.<br />
<br />
===Addressing===<br />
<br />
The CMCTL appears to convert 32 bit VAX addresses into DRAM addressing as follows:<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
| A21 || A20 || A19 || A18 || A17 || A16 || A15 || A14 || A13 || A12 || A11 || A10 || A09 || A08 || A07 || A06 || A05 || A04 || A03 || A02<br />
|-<br />
| width=2.5% | R09 <br />
| width=2.5% | <br />
| width=2.5% | R08<br />
| width=2.5% | R07<br />
| width=2.5% | R06<br />
| width=2.5% | R05<br />
| width=2.5% | R04<br />
| width=2.5% | R03<br />
| width=2.5% | R02<br />
| width=2.5% | R01<br />
| width=2.5% | R00<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
|-<br />
| width=2.5% | <br />
| width=2.5% | C09<br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | C08<br />
| width=2.5% | C07<br />
| width=2.5% | C06<br />
| width=2.5% | C05<br />
| width=2.5% | C04<br />
| width=2.5% | C03<br />
| width=2.5% | C02<br />
| width=2.5% | C01<br />
| width=2.5% | C00<br />
|}<br />
<br />
Axx are VAX address lines<br />
Rxx are DRAM row address bits<br />
Cxx are DRAM column address bits<br />
<br />
This addressing scheme is used to ensure that 256kxX DRAMs (which use only 9 bit row and column addresses) are still supported for use with the CMCTL.<br />
<br />
It is, of course, still up to the CMCTL to determine which ranks are selected by the upper bits of a given physical address. This is determined by the MEMCSR0-15 registers, which seem to specify whether or not a bank is present, as well as what base address it resides at. It may perform other functions, but it does not seem to be documented in available documentation.<br />
<br />
===CAS and RAS Signals===<br />
<br />
Each 16MB or 8MB memory card for the KA650 uses one CAS line in its entirety. This is why a maximum of 4 cards may be used in a KA650 system. Each RAM card uses the first CAS line, and passes the remaining lines on to the next card, shifted down one bit. So for example, the first card gets CAS0 CAS1 CAS2 CAS3, in that order. It uses CAS0 and passes CAS1 CAS2 and CAS3 on to the next card, in that order. The next card uses CAS1 and passes on CAS2 and CAS3. This repeats until 4 cards have used up all of the available CAS lines.<br />
<br />
The CAS line is not gated in any way on the MS650-AA. The CAS line is simply buffered, inverted to match the polarity of the DRAMs, and distributed to all DRAMs on the card (likely with some hierarchical buffering methodology).<br />
<br />
RAS lines, on the other hand, are shared between all the cards in the system. The first rank of DRAMs on the card are address by RAS0, the second by RAS1, etc. As previously mentioned, the RAS lines to each bank within a rank are gated on or off by decoding circuitry based on the state of XA20/XA21.<br />
<br />
===Refresh===<br />
<br />
DRAMs are built using one tiny MOS capacitor for each bit. These capacitors leak slightly and need to be periodically refreshed. DRAM rows are refreshed by simply addressing a row. Any row access refreshes that row, no column needs to be strobed for a refresh.<br />
<br />
As such, during refresh cycles, the CMCTL places a row address to be refreshed on the address bus, asserts SE, and asserts all RAS lines for several clock cycles. The purpose of the SE signal is so that RAM cards with 256kxX DRAMs do not gate any of the /RAS lines going to the DRAMs, or else only whatever DRAM bank is (randomly) addressed by XA20 and XA21 would be refreshed.<br />
<br />
===ECC===<br />
<br />
The ECC supported by the CMCTL has the ability to detect and correct single data bit errors, detect single ECC bit errors, and detect double-bit data errors. [[#KA650-technical-manual|[2]]]<br />
<br />
[[ECC]] is generally based on producing parity bits of various collections of data bits. Since parity is based around the simple XOR, it is a linear operation in a manner of speaking. Luckily this means we can determine the ECC equations based on a number of sample data patterns and the respective ECC bits, such as the ECC produced for 0 data, and data with only one bit in the word set. By comparing the ECC for each test pattern to that of 0, we can determine which ECC bits each bit in the data word affects.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| bit || colspan=8 | data || ECC<br />
|-<br />
| || MSB || colspan = 6 | || LSB ||<br />
|-<br />
| - || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0111100<br />
|-<br />
| 0 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 1100100<br />
|-<br />
| 1 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0100000<br />
|-<br />
| 2 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0100110<br />
|-<br />
| 3 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 1100010<br />
|-<br />
| 4 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0100011<br />
|-<br />
| 5 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 1100111<br />
|-<br />
| 6 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 1100001<br />
|-<br />
| 7 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0100101<br />
|-<br />
| 8 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 1010100<br />
|-<br />
| 9 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0010000<br />
|-<br />
| 10 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0010110<br />
|-<br />
| 11 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 1010010<br />
|-<br />
| 12 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0010011<br />
|-<br />
| 13 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 1010111<br />
|-<br />
| 14 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 1010001<br />
|-<br />
| 15 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0010101<br />
|-<br />
| 16 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 1001100<br />
|-<br />
| 17 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0001000<br />
|-<br />
| 18 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0001110<br />
|-<br />
| 19 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 1001010<br />
|-<br />
| 20 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001011<br />
|-<br />
| 21 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001111<br />
|-<br />
| 22 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001001<br />
|-<br />
| 23 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001101<br />
|-<br />
| 24 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000100<br />
|-<br />
| 25 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000000<br />
|-<br />
| 26 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000110<br />
|-<br />
| 27 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000010<br />
|-<br />
| 28 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000011<br />
|-<br />
| 29 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000111<br />
|-<br />
| 30 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000001<br />
|-<br />
| 31 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000101<br />
|}<br />
<br />
<br />
The results of this are depicted below. The basic result is that toggling one of the bits that belongs to the ECC bit group will result in that ECC bit toggling as well.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| ECC bit || colspan=3 | MSB || colspan=26 | || colspan=3 | LSB<br />
|-<br />
|MD32<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|-<br />
|MD33<br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
|-<br />
|MD34<br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
|-<br />
|MD35<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD36<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD37<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|-<br />
|MD38<br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
|}<br />
<br />
An interesting and potentially useful point to note is that flipping bit 28 happens to flip all of the ECC bits together. Another interesting point is that inverting the entire data word produces the same ECC.<br />
<br />
From this information, we can derive some data patterns that produce useful ECC combinations, such as ECC of all zeroes, all ones, only one bit set, and only one bit clear. Looking at the table above, we got lucky and examples of many of these combinations were found by chance. In particular, we happened upon data combinations that produced every possibility of 1 ECC bit set. These, combined with the fact that we can toggle bit 28 to get the inverse ECC bits, gives us a set of data patterns which produce ECC with only one bit clear. From here, we only need to derive a combination which produces all-zero ECC, and from that, derive all-one ECC.<br />
<br />
Starting with the ECC for bit 31 set, we can toggle single bits at a time until we find a combination that produces the ECC we want.<br />
<nowiki><br />
31 1000 0000 0000 0000 0000 0000 0000 0000 1000101<br />
1000 0000 0000 0000 0000 0000 0000 0001 0011101<br />
1000 0000 0000 0000 0000 0010 0000 0001 0110001<br />
1000 0000 1000 0000 0000 0010 0000 0001 0000000 <--<br />
1001 0000 1000 0000 0000 0010 0000 0001 1111111 <--<br />
</nowiki><br />
<br />
The summary of these useful ECC combinations is tabulated below (data in hex, ECC in binary)<br />
<br />
useful ECC combinations:<br />
<br />
{| border=1 style="text-align:center"<br />
| ECC (binary) || data (hex)<br />
|-<br />
| 0000000 || 80800201<br />
|-<br />
| 0000001 || 40000000<br />
|-<br />
| 0000010 || 08000000<br />
|-<br />
| 0000100 || 01000000<br />
|-<br />
| 0001000 || 00020000<br />
|-<br />
| 0010000 || 00000200<br />
|-<br />
| 0100000 || 00000002<br />
|-<br />
| 1000000 || 02000000<br />
|-<br />
| 1111111 || 90800201<br />
|-<br />
| 1111110 || 50000000<br />
|-<br />
| 1111101 || 18000000<br />
|-<br />
| 1111011 || 11000000<br />
|-<br />
| 1110111 || 10020000<br />
|-<br />
| 1101111 || 10000200<br />
|-<br />
| 1011111 || 10000002<br />
|-<br />
| 0111111 || 12000000<br />
|}<br />
<br />
===KA650 Memory Bus Cycles===<br />
<br />
The memory cycles detailed below were captured on an HP 16700A logic analysis system. Memory data and ECC bits were captured, as well as memory address, XA20 and XA21 (inverted back to positive logic by the logic analyzer), the 4 CAS lines, the 4 RAS lines, the WE line, the SE line, the MCLK lines for timing reference. Additionally, the /CAS (DUTCAS), /RAS (DUTRAS), and data line (DUTDATA) of a DRAM located at 0x0XXXXX, bit 0 were captured to show the differences between a selected DRAM and one that was not selected.<br />
<br />
[[File:MS650-AA-Longword-write-same-rank-bank-cycle.png|thumb|none|Longword write cycle]]<br />
<br />
During a longword write cycle, the CMCTL first places the row address onto the memory address bus. Next, it asserts the RAS signal, causing the DRAMs to latch the row address. It then asserts the write enable signal and places the column address on the address bus, then asserts the CAS signal. Lastly, the data and ECC bits are placed on the bus, and some time later CAS deasserts, followed by RAS. On the MS650-AA RAM module, XA20 and XA21 are decoded to determine which bank is selected. Since the DUT being probed here is at address 0x0XXXXX, it is selected during this write.<br />
<br />
[[File:MS650-AA-Longword-write-diff-rank-same-bank-cycle.png|thumb|none|Longword write cycle to a different rank]]<br />
<br />
The CMCTL will assert only the RAS line for the rank which is selected based on the memory address the VAX CPU is accessing. As shown in the next capture, when an address in 0x1XXXXX is written, RAS2 is asserted instead, and thus the DUT being probed was not selected.<br />
<br />
[[File:MS650-AA-Longword-write-same-rank-diff-bank-cycle.png|thumb|none|Longword write cycle to a different bank]]<br />
<br />
Likewise, the MS650-AA decoding circuitry will only allow the RAS line for the bank selected by XA20 and XA21 to be asserted, while ensuring the RAS lines for the other banks are gated off.<br />
<br />
[[File:MS650-AA-byte-write-cycle.png|thumb|none|Byte write cycle]]<br />
<br />
During a byte write cycle, the CMCTL must first read the entire 39 bit word from the MS650, modify the byte which is being written, recalculate the ECC bits, and write the entire 39 bit word back to the MS650. Due to this, both a read and write cycle can be seen within a byte write cycle. Note that the RAS line stays asserted throughout both the read and write parts of the cycle.<br />
<br />
[[File:MS650-AA-qword-write-cycle.png|thumb|none|Quadword write cycle]]<br />
<br />
During a quadword write cycle, two 39 bit words must be written to the MS650. Note that RAS actually cycles twice during this cycle.<br />
<br />
[[File:MS650-AA-read-cycle.png|thumb|none|read cycle]]<br />
<br />
Any read cycle longword or smaller will appear to have the same cycle. Since the MS650 must be read or written as a full 39 bit cycle, there is no effective difference between a byte, word, or longword read. A quadword read, of course, involves reading two 39 bit words, and would thus result in a double cycle similar to the quadword write.<br />
<br />
[[File:MS650-AA-refresh-cycle.png|thumb|none|refresh cycle]]<br />
<br />
Lastly, during a refresh cycle, the SE signal is asserted to force an MS650-AA to allow all banks to be refreshed at once. This would not be necessary for the 1MxX DRAMs on an MS650-BA. Similarly, the CMCTL asserts all RAS lines to load the row to be refreshed into every DRAM connected to the KA650. There is no assertion of CAS since there is no need to actually access a specific location, just to refresh a given row.<br />
<br />
==Memory Connector Pinouts==<br />
<br />
The MS650 boards and KA650 CPU board communicate through the CD interconnect and a 50 pin ribbon cable. The pinouts are available and can be deduced from the KA650 technical manual and field maintenance print set. They are repeated here for ease of use.<br />
<br />
Although the memory card is in a Q-bus form factor, and it has edge connectors for the Q-bus half of the backplane (AB connectors), it does not seem to use any q-bus signals for operation other than power supply pins.<br />
<br />
===Data Bus Connector===<br />
<br />
{| border=1 style="text-align:center"<br />
| pin || signal || pin || signal<br />
|-<br />
| 01 || GND || 26 || D MD10 H<br />
|-<br />
| 02 || D MD9 H || 27 || GND<br />
|-<br />
| 03 || D MD8 H || 28 || D MD29 H<br />
|-<br />
| 04 || D MD7 H || 29 || D MD28 H<br />
|-<br />
| 05 || GND || 30 || D MD27 H<br />
|-<br />
| 06 || D MD6 H || 31 || GND<br />
|-<br />
| 07 || D MD5 H || 32 || D MD26 H<br />
|-<br />
| 08 || D MD4 H || 33 || D MD25 H<br />
|-<br />
| 09 || D MD3 H || 34 || D MD24 H<br />
|-<br />
| 10 || GND || 35 || D MD23 H<br />
|-<br />
| 11 || D MD2 H || 36 || GND<br />
|-<br />
| 12 || D MD1 H || 37 || D MD22 H<br />
|-<br />
| 13 || D MD0 H || 38 || D MD21 H<br />
|-<br />
| 14 || D MD19 H || 39 || D MD20 H<br />
|-<br />
| 15 || GND || 40 || D MD38 H<br />
|-<br />
| 16 || D MD18 H || 41 || GND<br />
|-<br />
| 17 || D MD17 H || 42 || D MD37 H<br />
|-<br />
| 18 || D MD16 H || 43 || D MD36 H<br />
|-<br />
| 19 || D MD15 H || 44 || D MD35 H<br />
|-<br />
| 20 || GND || 45 || D MD34 H<br />
|-<br />
| 21 || D MD14 H || 46 || GND<br />
|-<br />
| 22 || D MD13 H || 47 || D MD33 H<br />
|-<br />
| 23 || D MD12 H || 48 || D MD32 H<br />
|-<br />
| 24 || GND || 49 || D MD31 H<br />
|-<br />
| 25 || D MD11 H || 50 || D MD30 H<br />
|-<br />
|}<br />
<br />
===CD interconnect===<br />
<br />
Note that DEC pin naming conventions follow the [[DEC alphabet]], skipping various letters which could be mistaken for numerals.<br />
<br />
{| border=1 style="text-align:center"<br />
| signal || pin<br />
|-<br />
| MA0 || DB2<br />
|-<br />
| MA1 || DE2<br />
|-<br />
| MA2 || DH2<br />
|-<br />
| MA3 || DJ2<br />
|-<br />
| MA4 || DL2<br />
|-<br />
| MA5 || DM2<br />
|-<br />
| MA6 || DP2<br />
|-<br />
| MA7 || DR2<br />
|-<br />
| MA8 || DS2<br />
|-<br />
| MA9 || DU2<br />
|-<br />
| XA20 || CV2<br />
|-<br />
| XA21 || CU2<br />
|-<br />
| CAS0 || CF2<br />
|-<br />
| CAS1 || CK2<br />
|-<br />
| CAS2 || CN2<br />
|-<br />
| CAS3 || CS2<br />
|-<br />
| RAS0 || CE2<br />
|-<br />
| RAS1 || CJ2<br />
|-<br />
| RAS2 || CM2<br />
|-<br />
| RAS3 || CR2<br />
|-<br />
| WE || CB2<br />
|-<br />
| SE || CA1<br />
|-<br />
|}<br />
<br />
==KA650 VAX Firmware Memory Tests==<br />
<br />
Many of the tests built in to the firmware of the VAX can be quite thorough, if used properly. The tests can be accessed by the TEST command in the monitor, abbreviated to 't'.<br />
<br />
The tests report diagnostic information upon failure, encoded simply as a number of values in registers and memory locations on the stack. With the proper documentation, these values could be decoded to determine the problem. Lacking that documentation, I was able to reverse engineer enough of one test that was failing to understand it's output.<br />
<br />
===TEST 48: MEM_Addr_shrts===<br />
<br />
This test is normally used to check for shorted address lines. It will fill the memory with a pattern first, then it will check each word in order to see if it is still the same pattern. After checking a word, it will check the CMCTL status register to ensure there were no detected errors. Then it will replace the word with another pattern (usually mostly an inverse of the first pattern).<br />
<br />
If any address line is shorted, when the test writes the second pattern, it will affect another location in memory. When that location is encountered, it will read as the wrong data thus showing the issue. However, the test is also capable of detecting stuck bits the way it is designed, and this test happened to find all DRAM errors in my case.<br />
<br />
The output when the test encounters an error looks like the following:<br />
<br />
<nowiki><br />
>>>t 48<br />
<br />
<br />
?48 2 08 FF 00 0002<br />
<br />
P1=00000000 P2=04000000 P3=00000004 P4=00031000 P5=AAAAAAAA<br />
P6=55555555 P7=00000043 P8=200C5875 P9=00000000 P10=2005311F<br />
r0=45555555 r1=000C5860 r2=45555555 r3=00000004 r4=0000006B<br />
r5=AAAAAAAA r6=20080140 r7=20080144 r8=00000000 ERF=80000000<br />
<br />
Normal operation not possible.<br />
<br />
>>><br />
</nowiki><br />
<br />
I figured out the meaning of some of these registers for this test. First of all, P10 indicates an address where presumably DEC personnel would check a source listing to find out the exact meaning of the rest of the values shown. The meanings of the registers I have found are only valid for this routine, located near 2005311F.<br />
<br />
{| border=1 style="text-align:center"<br />
| register || description<br />
|-<br />
| r0 || contents of memory at address being tested<br />
|-<br />
| r1 || address being tested<br />
|-<br />
| r2 || expected pattern from memory being tested<br />
|-<br />
| r5 || pattern to replace location with<br />
|-<br />
| r6 || address of CMCTL MEMCSR16 (a diagnostic register)<br />
|-<br />
| P8 || contents of MEMCSR16<br />
|}<br />
<br />
==MEMCSR16 Register==<br />
<br />
The MEMCSR16 register gives us information on what kind of memory failure<br />
occurred. The bit meanings are as follows, according to the KA650 technical manual:<br />
<br />
{| border=1 style="text-align:center"<br />
| bits || description<br />
|-<br />
| <31> || set if uncorrectable error occurred<br />
|-<br />
| <30> || set if multiple uncorrectable errors occurred<br />
|-<br />
| <29> || set if correctable error occurred<br />
|-<br />
| <28:9> || page address where error occurred (pages are 512 bytes)<br />
|-<br />
| <8> || set if error ocurred during DMA<br />
|-<br />
| <7> || set if CDAL bus parity error occurred<br />
|-<br />
| <6:0> || error syndrome: a unique combination is produced here for each possible single bit error<br />
|}<br />
<br />
writing 1s to bits 31, 30, 29, 8, or 7 of MEMCSR16 resets those bits. bits 28:9 and 6:0 are read only.<br />
<br />
The MEMCSR registers can be read with test 9c.<br />
<br />
===Error Syndrome Field===<br />
<br />
The error syndrome is particularly useful for troubleshooting memory errors as it can tell us exactly which bit had the error. A list of the syndromes and the corresponding bit error is given below.<br />
<br />
{| border=1 style="text-align:center"<br />
| syndrome || bit position or error description<br />
|-<br />
| 0000000 || no error<br />
|-<br />
| 0000001 || 32<br />
|-<br />
| 0000010 || 33<br />
|-<br />
| 0000100 || 34<br />
|-<br />
| 0000111 || result of incorrect check bits written on CDAL parity error<br />
|-<br />
| 0001000 || 35<br />
|-<br />
| 0010000 || 36<br />
|-<br />
| 0011001 || 7<br />
|-<br />
| 0011010 || 2<br />
|-<br />
| 0011100 || 1<br />
|-<br />
| 0011111 || 4<br />
|-<br />
| 0100000 || 37<br />
|-<br />
| 0101001 || 15<br />
|-<br />
| 0101010 || 10<br />
|-<br />
| 0101100 || 9<br />
|-<br />
| 0101111 || 12<br />
|-<br />
| 0110001 || 23<br />
|-<br />
| 0110010 || 18<br />
|-<br />
| 0110100 || 17<br />
|-<br />
| 0110111 || 20<br />
|-<br />
| 0111000 || 24<br />
|-<br />
| 0111011 || 29<br />
|-<br />
| 0111101 || 30<br />
|-<br />
| 0111110 || 27<br />
|-<br />
| 1000000 || 38<br />
|-<br />
| 1011000 || 0<br />
|-<br />
| 1011011 || 5<br />
|-<br />
| 1011101 || 6<br />
|-<br />
| 1011110 || 3<br />
|-<br />
| 1101000 || 8<br />
|-<br />
| 1101011 || 13<br />
|-<br />
| 1101101 || 14<br />
|-<br />
| 1101110 || 11<br />
|-<br />
| 1110000 || 16<br />
|-<br />
| 1110011 || 21<br />
|-<br />
| 1110101 || 22<br />
|-<br />
| 1110110 || 19<br />
|-<br />
| 1111001 || 31<br />
|-<br />
| 1111010 || 26<br />
|-<br />
| 1111100 || 25<br />
|-<br />
| 1111111 || 28<br />
|-<br />
| other || multibit error<br />
|}<br />
<br />
==Troubleshooting==<br />
<br />
We now have all of the information necessary to narrow down which bits in which address regions are bad. However, that doesn't do any good for repair unless we also know which physical DRAMs that bit and region correspond to.<br />
<br />
===MS650-AA===<br />
<br />
Shown below is a diagram of the MS650-AA RAM card, broken up into 11 columns and 37 rows. Each spot in this grid contains up to 1 DRAM, but some locations contain other circuitry instead.<br />
<br />
<nowiki><br />
<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
--------------------------------------------------------------------------------<br />
01 | ooooooooooooooooooooooooo |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 01<br />
| --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
08 | --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 08<br />
|-------------------------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
09 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 09<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
16 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 16<br />
17 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 17<br />
18 |DDDDDDD|TTTTTTT TTTTTTTTT TTTTTTTT |DDDDDDDDDDDDD|TTTTTTTT TTTTTTTTT TTTTTTTT | 18<br />
19 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 19<br />
20 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 20<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
32 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 32<br />
33 |DDDDDDD-----------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 33<br />
36 |DDDDDDD| PPPPPPP TTTTT TTTTT |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 35<br />
37 |-------- TTTTTTT TTTTTTT --------DDDDDDDDDDDDDD-------DDDDDDDDDDDDDD| 37<br />
| -------------- --------------| <br />
| ___- - ___- |<br />
| | | || | | |<br />
-------------------- ----------------------------------------------------------<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
<br />
-----------------------------------------------<br />
| D DRAMS |<br />
| T TTL IC |<br />
| B some kind of DEC custom fast data buffer? |<br />
| P PAL16L8 |<br />
| o data connector |<br />
| | border |<br />
| - border |<br />
-----------------------------------------------<br />
<br />
</nowiki><br />
<br />
The MS650-AA RAM card uses two RAS lines. During normal initialization of the VAX, the rank connected to RAS0 will be first in memory, followed by the rank connected to RAS1. Presumably, the MS650-BA card would have 4 ranks.<br />
<br />
RAS0 - first 4MB<br />
RAS1 - second 4MB<br />
<br />
Based on the bit with the error, as well as the memory region where the error occurred, the specific DRAM with the failure can be found and replaced.<br />
<br />
Below is a list of the DRAMs sorted by memory region and bit, showing the grid location of the DRAM IC.<br />
<br />
By using the built in tests, along with MEMCSR16, and perhaps some manual DEPOSIT and EXAMINE testing, the bad DRAM should be possible to locate and then, using this table, the DRAM can be replaced.<br />
<br />
{| border=1 style="text-align:center"<br />
| DRAM || Address || data bit<br />
|-<br />
| A12 || 0XXXXX || MD00<br />
|-<br />
| A11 || 1XXXXX || MD00<br />
|-<br />
| A10 || 2XXXXX || MD00<br />
|-<br />
| A09 || 3XXXXX || MD00<br />
|-<br />
| A16 || 4XXXXX || MD00<br />
|-<br />
| A15 || 5XXXXX || MD00<br />
|-<br />
| A14 || 6XXXXX || MD00<br />
|-<br />
| A13 || 7XXXXX || MD00<br />
|-<br />
| A24 || 0XXXXX || MD01<br />
|-<br />
| A23 || 1XXXXX || MD01<br />
|-<br />
| A22 || 2XXXXX || MD01<br />
|-<br />
| A21 || 3XXXXX || MD01<br />
|-<br />
| A20 || 4XXXXX || MD01<br />
|-<br />
| A19 || 5XXXXX || MD01<br />
|-<br />
| A18 || 6XXXXX || MD01<br />
|-<br />
| A17 || 7XXXXX || MD01<br />
|-<br />
| A32 || 0XXXXX || MD02<br />
|-<br />
| A31 || 1XXXXX || MD02<br />
|-<br />
| A30 || 2XXXXX || MD02<br />
|-<br />
| A29 || 3XXXXX || MD02<br />
|-<br />
| A28 || 4XXXXX || MD02<br />
|-<br />
| A27 || 5XXXXX || MD02<br />
|-<br />
| A26 || 6XXXXX || MD02<br />
|-<br />
| A25 || 7XXXXX || MD02<br />
|-<br />
| B12 || 0XXXXX || MD03<br />
|-<br />
| B11 || 1XXXXX || MD03<br />
|-<br />
| B10 || 2XXXXX || MD03<br />
|-<br />
| B09 || 3XXXXX || MD03<br />
|-<br />
| A36 || 4XXXXX || MD03<br />
|-<br />
| A35 || 5XXXXX || MD03<br />
|-<br />
| A34 || 6XXXXX || MD03<br />
|-<br />
| A33 || 7XXXXX || MD03<br />
|-<br />
| B24 || 0XXXXX || MD04<br />
|-<br />
| B23 || 1XXXXX || MD04<br />
|-<br />
| B22 || 2XXXXX || MD04<br />
|-<br />
| B21 || 3XXXXX || MD04<br />
|-<br />
| B16 || 4XXXXX || MD04<br />
|-<br />
| B15 || 5XXXXX || MD04<br />
|-<br />
| B14 || 6XXXXX || MD04<br />
|-<br />
| B13 || 7XXXXX || MD04<br />
|-<br />
| B32 || 0XXXXX || MD05<br />
|-<br />
| B31 || 1XXXXX || MD05<br />
|-<br />
| B30 || 2XXXXX || MD05<br />
|-<br />
| B29 || 3XXXXX || MD05<br />
|-<br />
| B28 || 4XXXXX || MD05<br />
|-<br />
| B27 || 5XXXXX || MD05<br />
|-<br />
| B26 || 6XXXXX || MD05<br />
|-<br />
| B25 || 7XXXXX || MD05<br />
|-<br />
| C12 || 0XXXXX || MD06<br />
|-<br />
| C11 || 1XXXXX || MD06<br />
|-<br />
| C10 || 2XXXXX || MD06<br />
|-<br />
| C09 || 3XXXXX || MD06<br />
|-<br />
| C16 || 4XXXXX || MD06<br />
|-<br />
| C15 || 5XXXXX || MD06<br />
|-<br />
| C14 || 6XXXXX || MD06<br />
|-<br />
| C13 || 7XXXXX || MD06<br />
|-<br />
| C24 || 0XXXXX || MD07<br />
|-<br />
| C23 || 1XXXXX || MD07<br />
|-<br />
| C22 || 2XXXXX || MD07<br />
|-<br />
| C21 || 3XXXXX || MD07<br />
|-<br />
| E20 || 4XXXXX || MD07<br />
|-<br />
| D20 || 5XXXXX || MD07<br />
|-<br />
| C20 || 6XXXXX || MD07<br />
|-<br />
| B20 || 7XXXXX || MD07<br />
|-<br />
| C32 || 0XXXXX || MD08<br />
|-<br />
| C31 || 1XXXXX || MD08<br />
|-<br />
| C30 || 2XXXXX || MD08<br />
|-<br />
| C29 || 3XXXXX || MD08<br />
|-<br />
| C28 || 4XXXXX || MD08<br />
|-<br />
| C27 || 5XXXXX || MD08<br />
|-<br />
| C26 || 6XXXXX || MD08<br />
|-<br />
| C25 || 7XXXXX || MD08<br />
|-<br />
| D32 || 0XXXXX || MD09<br />
|-<br />
| D31 || 1XXXXX || MD09<br />
|-<br />
| D30 || 2XXXXX || MD09<br />
|-<br />
| D29 || 3XXXXX || MD09<br />
|-<br />
| D28 || 4XXXXX || MD09<br />
|-<br />
| D27 || 5XXXXX || MD09<br />
|-<br />
| D26 || 6XXXXX || MD09<br />
|-<br />
| D25 || 7XXXXX || MD09<br />
|-<br />
| D24 || 0XXXXX || MD10<br />
|-<br />
| D23 || 1XXXXX || MD10<br />
|-<br />
| D22 || 2XXXXX || MD10<br />
|-<br />
| D21 || 3XXXXX || MD10<br />
|-<br />
| D16 || 4XXXXX || MD10<br />
|-<br />
| D15 || 5XXXXX || MD10<br />
|-<br />
| D14 || 6XXXXX || MD10<br />
|-<br />
| D13 || 7XXXXX || MD10<br />
|-<br />
| D12 || 0XXXXX || MD11<br />
|-<br />
| D11 || 1XXXXX || MD11<br />
|-<br />
| D10 || 2XXXXX || MD11<br />
|-<br />
| D09 || 3XXXXX || MD11<br />
|-<br />
| E16 || 4XXXXX || MD11<br />
|-<br />
| E15 || 5XXXXX || MD11<br />
|-<br />
| E14 || 6XXXXX || MD11<br />
|-<br />
| E13 || 7XXXXX || MD11<br />
|-<br />
| E12 || 0XXXXX || MD12<br />
|-<br />
| E11 || 1XXXXX || MD12<br />
|-<br />
| E10 || 2XXXXX || MD12<br />
|-<br />
| E09 || 3XXXXX || MD12<br />
|-<br />
| E28 || 4XXXXX || MD12<br />
|-<br />
| E27 || 5XXXXX || MD12<br />
|-<br />
| E26 || 6XXXXX || MD12<br />
|-<br />
| E25 || 7XXXXX || MD12<br />
|-<br />
| E24 || 0XXXXX || MD13<br />
|-<br />
| E23 || 1XXXXX || MD13<br />
|-<br />
| E22 || 2XXXXX || MD13<br />
|-<br />
| E21 || 3XXXXX || MD13<br />
|-<br />
| F16 || 4XXXXX || MD13<br />
|-<br />
| F15 || 5XXXXX || MD13<br />
|-<br />
| F14 || 6XXXXX || MD13<br />
|-<br />
| F13 || 7XXXXX || MD13<br />
|-<br />
| E32 || 0XXXXX || MD14<br />
|-<br />
| E31 || 1XXXXX || MD14<br />
|-<br />
| E30 || 2XXXXX || MD14<br />
|-<br />
| E29 || 3XXXXX || MD14<br />
|-<br />
| F20 || 4XXXXX || MD14<br />
|-<br />
| F19 || 5XXXXX || MD14<br />
|-<br />
| F18 || 6XXXXX || MD14<br />
|-<br />
| F17 || 7XXXXX || MD14<br />
|-<br />
| F32 || 0XXXXX || MD15<br />
|-<br />
| F31 || 1XXXXX || MD15<br />
|-<br />
| F30 || 2XXXXX || MD15<br />
|-<br />
| F29 || 3XXXXX || MD15<br />
|-<br />
| F28 || 4XXXXX || MD15<br />
|-<br />
| F27 || 5XXXXX || MD15<br />
|-<br />
| F26 || 6XXXXX || MD15<br />
|-<br />
| F25 || 7XXXXX || MD15<br />
|-<br />
| F24 || 0XXXXX || MD16<br />
|-<br />
| F23 || 1XXXXX || MD16<br />
|-<br />
| F22 || 2XXXXX || MD16<br />
|-<br />
| F21 || 3XXXXX || MD16<br />
|-<br />
| F36 || 4XXXXX || MD16<br />
|-<br />
| F35 || 5XXXXX || MD16<br />
|-<br />
| F34 || 6XXXXX || MD16<br />
|-<br />
| F33 || 7XXXXX || MD16<br />
|-<br />
| G32 || 0XXXXX || MD17<br />
|-<br />
| G31 || 1XXXXX || MD17<br />
|-<br />
| G30 || 2XXXXX || MD17<br />
|-<br />
| G29 || 3XXXXX || MD17<br />
|-<br />
| G36 || 4XXXXX || MD17<br />
|-<br />
| G35 || 5XXXXX || MD17<br />
|-<br />
| G34 || 6XXXXX || MD17<br />
|-<br />
| G33 || 7XXXXX || MD17<br />
|-<br />
| G24 || 0XXXXX || MD18<br />
|-<br />
| G23 || 1XXXXX || MD18<br />
|-<br />
| G22 || 2XXXXX || MD18<br />
|-<br />
| G21 || 3XXXXX || MD18<br />
|-<br />
| G28 || 4XXXXX || MD18<br />
|-<br />
| G27 || 5XXXXX || MD18<br />
|-<br />
| G26 || 6XXXXX || MD18<br />
|-<br />
| G25 || 7XXXXX || MD18<br />
|-<br />
| H32 || 0XXXXX || MD19<br />
|-<br />
| H31 || 1XXXXX || MD19<br />
|-<br />
| H30 || 2XXXXX || MD19<br />
|-<br />
| H29 || 3XXXXX || MD19<br />
|-<br />
| G20 || 4XXXXX || MD19<br />
|-<br />
| G19 || 5XXXXX || MD19<br />
|-<br />
| G18 || 6XXXXX || MD19<br />
|-<br />
| G17 || 7XXXXX || MD19<br />
|-<br />
| H24 || 0XXXXX || MD20<br />
|-<br />
| H23 || 1XXXXX || MD20<br />
|-<br />
| H22 || 2XXXXX || MD20<br />
|-<br />
| H21 || 3XXXXX || MD20<br />
|-<br />
| K37 || 4XXXXX || MD20<br />
|-<br />
| J37 || 5XXXXX || MD20<br />
|-<br />
| H37 || 6XXXXX || MD20<br />
|-<br />
| G37 || 7XXXXX || MD20<br />
|-<br />
| I32 || 0XXXXX || MD21<br />
|-<br />
| I31 || 1XXXXX || MD21<br />
|-<br />
| I30 || 2XXXXX || MD21<br />
|-<br />
| I29 || 3XXXXX || MD21<br />
|-<br />
| H36 || 4XXXXX || MD21<br />
|-<br />
| H35 || 5XXXXX || MD21<br />
|-<br />
| H34 || 6XXXXX || MD21<br />
|-<br />
| H33 || 7XXXXX || MD21<br />
|-<br />
| I24 || 0XXXXX || MD22<br />
|-<br />
| I23 || 1XXXXX || MD22<br />
|-<br />
| I22 || 2XXXXX || MD22<br />
|-<br />
| I21 || 3XXXXX || MD22<br />
|-<br />
| H28 || 4XXXXX || MD22<br />
|-<br />
| H27 || 5XXXXX || MD22<br />
|-<br />
| H26 || 6XXXXX || MD22<br />
|-<br />
| H25 || 7XXXXX || MD22<br />
|-<br />
| J32 || 0XXXXX || MD23<br />
|-<br />
| J31 || 1XXXXX || MD23<br />
|-<br />
| J30 || 2XXXXX || MD23<br />
|-<br />
| J29 || 3XXXXX || MD23<br />
|-<br />
| I36 || 4XXXXX || MD23<br />
|-<br />
| I35 || 5XXXXX || MD23<br />
|-<br />
| I34 || 6XXXXX || MD23<br />
|-<br />
| I33 || 7XXXXX || MD23<br />
|-<br />
| J24 || 0XXXXX || MD24<br />
|-<br />
| J23 || 1XXXXX || MD24<br />
|-<br />
| J22 || 2XXXXX || MD24<br />
|-<br />
| J21 || 3XXXXX || MD24<br />
|-<br />
| I28 || 4XXXXX || MD24<br />
|-<br />
| I27 || 5XXXXX || MD24<br />
|-<br />
| I26 || 6XXXXX || MD24<br />
|-<br />
| I25 || 7XXXXX || MD24<br />
|-<br />
| K32 || 0XXXXX || MD25<br />
|-<br />
| K31 || 1XXXXX || MD25<br />
|-<br />
| K30 || 2XXXXX || MD25<br />
|-<br />
| K29 || 3XXXXX || MD25<br />
|-<br />
| J36 || 4XXXXX || MD25<br />
|-<br />
| J35 || 5XXXXX || MD25<br />
|-<br />
| J34 || 6XXXXX || MD25<br />
|-<br />
| J33 || 7XXXXX || MD25<br />
|-<br />
| K24 || 0XXXXX || MD26<br />
|-<br />
| K23 || 1XXXXX || MD26<br />
|-<br />
| K22 || 2XXXXX || MD26<br />
|-<br />
| K21 || 3XXXXX || MD26<br />
|-<br />
| J28 || 4XXXXX || MD26<br />
|-<br />
| J27 || 5XXXXX || MD26<br />
|-<br />
| J26 || 6XXXXX || MD26<br />
|-<br />
| J25 || 7XXXXX || MD26<br />
|-<br />
| K20 || 0XXXXX || MD27<br />
|-<br />
| J20 || 1XXXXX || MD27<br />
|-<br />
| I20 || 2XXXXX || MD27<br />
|-<br />
| H20 || 3XXXXX || MD27<br />
|-<br />
| K36 || 4XXXXX || MD27<br />
|-<br />
| K35 || 5XXXXX || MD27<br />
|-<br />
| K34 || 6XXXXX || MD27<br />
|-<br />
| K33 || 7XXXXX || MD27<br />
|-<br />
| F12 || 0XXXXX || MD28<br />
|-<br />
| F11 || 1XXXXX || MD28<br />
|-<br />
| F10 || 2XXXXX || MD28<br />
|-<br />
| F09 || 3XXXXX || MD28<br />
|-<br />
| K28 || 4XXXXX || MD28<br />
|-<br />
| K26 || 6XXXXX || MD28<br />
|-<br />
| K27 || 5XXXXX || MD28<br />
|-<br />
| K25 || 7XXXXX || MD28<br />
|-<br />
| G12 || 0XXXXX || MD29<br />
|-<br />
| G11 || 1XXXXX || MD29<br />
|-<br />
| G10 || 2XXXXX || MD29<br />
|-<br />
| G09 || 3XXXXX || MD29<br />
|-<br />
| G16 || 4XXXXX || MD29<br />
|-<br />
| G15 || 5XXXXX || MD29<br />
|-<br />
| G14 || 6XXXXX || MD29<br />
|-<br />
| G13 || 7XXXXX || MD29<br />
|-<br />
| G04 || 0XXXXX || MD30<br />
|-<br />
| G03 || 1XXXXX || MD30<br />
|-<br />
| G02 || 2XXXXX || MD30<br />
|-<br />
| G01 || 3XXXXX || MD30<br />
|-<br />
| G08 || 4XXXXX || MD30<br />
|-<br />
| G07 || 5XXXXX || MD30<br />
|-<br />
| G06 || 6XXXXX || MD30<br />
|-<br />
| G05 || 7XXXXX || MD30<br />
|-<br />
| H04 || 0XXXXX || MD31<br />
|-<br />
| H03 || 1XXXXX || MD31<br />
|-<br />
| H02 || 2XXXXX || MD31<br />
|-<br />
| H01 || 3XXXXX || MD31<br />
|-<br />
| H08 || 4XXXXX || MD31<br />
|-<br />
| H07 || 5XXXXX || MD31<br />
|-<br />
| H06 || 6XXXXX || MD31<br />
|-<br />
| H05 || 7XXXXX || MD31<br />
|-<br />
| H12 || 0XXXXX || MD32<br />
|-<br />
| H11 || 1XXXXX || MD32<br />
|-<br />
| H10 || 2XXXXX || MD32<br />
|-<br />
| H09 || 3XXXXX || MD32<br />
|-<br />
| H16 || 4XXXXX || MD32<br />
|-<br />
| H15 || 5XXXXX || MD32<br />
|-<br />
| H14 || 6XXXXX || MD32<br />
|-<br />
| H13 || 7XXXXX || MD32<br />
|-<br />
| I04 || 0XXXXX || MD33<br />
|-<br />
| I03 || 1XXXXX || MD33<br />
|-<br />
| I02 || 2XXXXX || MD33<br />
|-<br />
| I01 || 3XXXXX || MD33<br />
|-<br />
| I08 || 4XXXXX || MD33<br />
|-<br />
| I07 || 5XXXXX || MD33<br />
|-<br />
| I06 || 6XXXXX || MD33<br />
|-<br />
| I05 || 7XXXXX || MD33<br />
|-<br />
| I12 || 0XXXXX || MD34<br />
|-<br />
| I11 || 1XXXXX || MD34<br />
|-<br />
| I10 || 2XXXXX || MD34<br />
|-<br />
| I09 || 3XXXXX || MD34<br />
|-<br />
| I16 || 4XXXXX || MD34<br />
|-<br />
| I15 || 5XXXXX || MD34<br />
|-<br />
| I14 || 6XXXXX || MD34<br />
|-<br />
| I13 || 7XXXXX || MD34<br />
|-<br />
| J04 || 0XXXXX || MD35<br />
|-<br />
| J03 || 1XXXXX || MD35<br />
|-<br />
| J02 || 2XXXXX || MD35<br />
|-<br />
| J01 || 3XXXXX || MD35<br />
|-<br />
| J08 || 4XXXXX || MD35<br />
|-<br />
| J07 || 5XXXXX || MD35<br />
|-<br />
| J06 || 6XXXXX || MD35<br />
|-<br />
| J05 || 7XXXXX || MD35<br />
|-<br />
| J12 || 0XXXXX || MD36<br />
|-<br />
| J11 || 1XXXXX || MD36<br />
|-<br />
| J10 || 2XXXXX || MD36<br />
|-<br />
| J09 || 3XXXXX || MD36<br />
|-<br />
| J16 || 4XXXXX || MD36<br />
|-<br />
| J15 || 5XXXXX || MD36<br />
|-<br />
| J14 || 6XXXXX || MD36<br />
|-<br />
| J13 || 7XXXXX || MD36<br />
|-<br />
| K04 || 0XXXXX || MD37<br />
|-<br />
| K03 || 1XXXXX || MD37<br />
|-<br />
| K02 || 2XXXXX || MD37<br />
|-<br />
| K01 || 3XXXXX || MD37<br />
|-<br />
| K08 || 4XXXXX || MD37<br />
|-<br />
| K07 || 5XXXXX || MD37<br />
|-<br />
| K06 || 6XXXXX || MD37<br />
|-<br />
| K05 || 7XXXXX || MD37<br />
|-<br />
| K12 || 0XXXXX || MD38<br />
|-<br />
| K11 || 1XXXXX || MD38<br />
|-<br />
| K10 || 2XXXXX || MD38<br />
|-<br />
| K09 || 3XXXXX || MD38<br />
|-<br />
| K16 || 4XXXXX || MD38<br />
|-<br />
| K15 || 5XXXXX || MD38<br />
|-<br />
| K14 || 6XXXXX || MD38<br />
|-<br />
| K13 || 7XXXXX || MD38<br />
|}<br />
<br />
===MS650-BA===<br />
<br />
Because I did not have an MS650-BA to test, I do not have as much information on this module as on the MS650-AA. Presumably, the MS650-BA has 4 ranks of 4MB in 1MBxX DRAMs, meaning there is no need to have 4 banks in each rank like the 256kx1 DRAMs on the MS650-AA.<br />
<br />
==External Links==<br />
<br />
* [https://youtu.be/eDMhdAEFEgc Youtube - KA650 Memory Troubleshooting]<br />
<br />
==References==<br />
<br />
<div id="KA650-print-set">[1] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="KA650-technical-manual">[2] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div><br />
<br />
[[Category: VAXen]]<br />
[[Category: DEC Memories]]</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_Main_Memory_System&diff=21871
KA650 Main Memory System
2019-11-24T17:26:13Z
<p>Jzatarski: added link to youtube video related to memory troubleshooting</p>
<hr />
<div>This page contains notes on troubleshooting, repair, and theory of operation of the [[DEC KA650]]/[[MS650]] memory subsystem.<br />
<br />
==Overview==<br />
<br />
The MS650-AA and MS650-BA memory module are intended to be used with the [[DEC KA650]] [[VAX]] [[CPU]], as the name might suggest. These quad width cards contain 8MB and 16MB of RAM for the VAX, respectively, complete with [[ECC]].<br />
<br />
==Theory of Operation==<br />
<br />
===Memory Controller General Architecture and Organization===<br />
<br />
====Memory Control Signals Provided by the CMCTL====<br />
The CMCTL IC is the [[DRAM]] controller for the KA650 CPU. It has 10 address line outputs, 39 memory data I/O lines (MD), 4 CAS outputs, 4 RAS outputs, a WE pin, and an SE pin. Also available to the RAM card are the inverse of the 20th and 21st address lines (XA20 & XA21), which are used as bank selection when using 256kxX DRAMs. The data lines are provided to the RAM cards through a 50 conductor ribbon cable, while the rest of the control lines are provided through the CD interconnect on the backplane. [[#KA650-print-set|[1]]]<br />
<br />
The 10 address lines carry the row address on the rising edge of a RAS line, followed by the column address on the rising edge of a CAS line.<br />
<br />
The 39 data I/O lines carry the 32 data and 7 ECC bits for the RAM.<br />
<br />
The 4 CAS (Column Address Strobe) lines allow strobing the column address on up to 4 separate memory modules.<br />
<br />
The 4 RAS (Row Address Strobe) lines allow selection of up to 4 banks on a single memory module.<br />
<br />
The WE (Write Enable) pin indicates that the CMCTL is writing to memory, rather than reading.<br />
<br />
The SE (Strobe Enable?) pin seems to indicate that the CMCTL is refreshing memory. This is necessary for the 8MB card to correctly strobe the RAS lines of each bank during a refresh cycle, due to the extra RAS gating circuitry necessary on cards with 256kxX DRAMs.<br />
<br />
The XA20 and XA21 lines are the inverse of the latched address lines from the CDAL bus.<br />
<br />
Note that many of the above control lines are inverse logic from what is normally used to drive DRAMs; in particular, CAS, RAS, and WE lines are inverted from the normal JEDEC DRAM convention of active low /RAS, /CAS, and /WE.<br />
<br />
====Memory Ranks & Banks====<br />
<br />
Due to the 10 bit address bus using conventional multiplexed row and column DRAM addressing, an effective 20 bit address is formed. This allows the CMCTL to address up to 1MWord per rank.<br />
<br />
By strobing different pairings of RAS and CAS (RAS0+CAS0 is one rank, while RAS0+CAS1 is another rank, while RAS1+CAS0 is yet another rank), the CMCTL supports up to 16 ranks of RAM, each 1Mx39. Each rank is thus 4MB of memory once ECC overhead is accounted for. This puts a 64MB cap on the maximum amount of memory the CMCTL can address (16 ranks of 4MB).<br />
<br />
When 256kxX DRAMs are used in place of 1MxX DRAMs, each 1Mx39 rank is further divided into 4 banks of 256kx39. Each bank is selected by XA20 and XA21, which are provided to the RAM cards via the CD interconnect. These address bits appear to only be valid on the rising edge of RAS. Before CAS has strobed, the bits have generally already changed since these are derived from the CDAL bus of the VAX CPU. These bits are used to gate the /RAS lines to the DRAMs ensuring that only the selected bank is addressed. The /CAS line for the card is not affected.<br />
<br />
The MS650-AA card contains 312 256kx1 ZIP DRAMs, organized into 8 banks of 256kx39. As previously mentioned, one memory rank as addressed by the CMCTL memory controller consists of 4 banks, making up a total of 1MWord of memory per rank. Each DRAM on the card corresponds to one bit of the 39 bit word within a 1MB address region of the VAX.<br />
<br />
===Addressing===<br />
<br />
The CMCTL appears to convert 32 bit VAX addresses into DRAM addressing as follows:<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
| A21 || A20 || A19 || A18 || A17 || A16 || A15 || A14 || A13 || A12 || A11 || A10 || A09 || A08 || A07 || A06 || A05 || A04 || A03 || A02<br />
|-<br />
| width=2.5% | R09 <br />
| width=2.5% | <br />
| width=2.5% | R08<br />
| width=2.5% | R07<br />
| width=2.5% | R06<br />
| width=2.5% | R05<br />
| width=2.5% | R04<br />
| width=2.5% | R03<br />
| width=2.5% | R02<br />
| width=2.5% | R01<br />
| width=2.5% | R00<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
|-<br />
| width=2.5% | <br />
| width=2.5% | C09<br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | C08<br />
| width=2.5% | C07<br />
| width=2.5% | C06<br />
| width=2.5% | C05<br />
| width=2.5% | C04<br />
| width=2.5% | C03<br />
| width=2.5% | C02<br />
| width=2.5% | C01<br />
| width=2.5% | C00<br />
|}<br />
<br />
Axx are VAX address lines<br />
Rxx are DRAM row address bits<br />
Cxx are DRAM column address bits<br />
<br />
This addressing scheme is used to ensure that 256kxX DRAMs (which use only 9 bit row and column addresses) are still supported for use with the CMCTL.<br />
<br />
It is, of course, still up to the CMCTL to determine which ranks are selected by the upper bits of a given physical address. This is determined by the MEMCSR0-15 registers, which seem to specify whether or not a bank is present, as well as what base address it resides at. It may perform other functions, but it does not seem to be documented in available documentation.<br />
<br />
===CAS and RAS Signals===<br />
<br />
Each 16MB or 8MB memory card for the KA650 uses one CAS line in its entirety. This is why a maximum of 4 cards may be used in a KA650 system. Each RAM card uses the first CAS line, and passes the remaining lines on to the next card, shifted down one bit. So for example, the first card gets CAS0 CAS1 CAS2 CAS3, in that order. It uses CAS0 and passes CAS1 CAS2 and CAS3 on to the next card, in that order. The next card uses CAS1 and passes on CAS2 and CAS3. This repeats until 4 cards have used up all of the available CAS lines.<br />
<br />
The CAS line is not gated in any way on the MS650-AA. The CAS line is simply buffered, inverted to match the polarity of the DRAMs, and distributed to all DRAMs on the card (likely with some hierarchical buffering methodology).<br />
<br />
RAS lines, on the other hand, are shared between all the cards in the system. The first rank of DRAMs on the card are address by RAS0, the second by RAS1, etc. As previously mentioned, the RAS lines to each bank within a rank are gated on or off by decoding circuitry based on the state of XA20/XA21.<br />
<br />
===Refresh===<br />
<br />
DRAMs are built using one tiny MOS capacitor for each bit. These capacitors leak slightly and need to be periodically refreshed. DRAM rows are refreshed by simply addressing a row. Any row access refreshes that row, no column needs to be strobed for a refresh.<br />
<br />
As such, during refresh cycles, the CMCTL places a row address to be refreshed on the address bus, asserts SE, and asserts all RAS lines for several clock cycles. The purpose of the SE signal is so that RAM cards with 256kxX DRAMs do not gate any of the /RAS lines going to the DRAMs, or else only whatever DRAM bank is (randomly) addressed by XA20 and XA21 would be refreshed.<br />
<br />
===ECC===<br />
<br />
The ECC supported by the CMCTL has the ability to detect and correct single data bit errors, detect single ECC bit errors, and detect double-bit data errors. [[#KA650-technical-manual|[2]]]<br />
<br />
[[ECC]] is generally based on producing parity bits of various collections of data bits. Since parity is based around the simple XOR, it is a linear operation in a manner of speaking. Luckily this means we can determine the ECC equations based on a number of sample data patterns and the respective ECC bits, such as the ECC produced for 0 data, and data with only one bit in the word set. By comparing the ECC for each test pattern to that of 0, we can determine which ECC bits each bit in the data word affects.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| bit || colspan=8 | data || ECC<br />
|-<br />
| || MSB || colspan = 6 | || LSB ||<br />
|-<br />
| - || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0111100<br />
|-<br />
| 0 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 1100100<br />
|-<br />
| 1 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0100000<br />
|-<br />
| 2 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0100110<br />
|-<br />
| 3 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 1100010<br />
|-<br />
| 4 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0100011<br />
|-<br />
| 5 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 1100111<br />
|-<br />
| 6 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 1100001<br />
|-<br />
| 7 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0100101<br />
|-<br />
| 8 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 1010100<br />
|-<br />
| 9 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0010000<br />
|-<br />
| 10 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0010110<br />
|-<br />
| 11 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 1010010<br />
|-<br />
| 12 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0010011<br />
|-<br />
| 13 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 1010111<br />
|-<br />
| 14 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 1010001<br />
|-<br />
| 15 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0010101<br />
|-<br />
| 16 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 1001100<br />
|-<br />
| 17 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0001000<br />
|-<br />
| 18 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0001110<br />
|-<br />
| 19 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 1001010<br />
|-<br />
| 20 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001011<br />
|-<br />
| 21 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001111<br />
|-<br />
| 22 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001001<br />
|-<br />
| 23 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001101<br />
|-<br />
| 24 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000100<br />
|-<br />
| 25 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000000<br />
|-<br />
| 26 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000110<br />
|-<br />
| 27 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000010<br />
|-<br />
| 28 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000011<br />
|-<br />
| 29 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000111<br />
|-<br />
| 30 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000001<br />
|-<br />
| 31 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000101<br />
|}<br />
<br />
<br />
The results of this are depicted below. The basic result is that toggling one of the bits that belongs to the ECC bit group will result in that ECC bit toggling as well.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| ECC bit || colspan=3 | MSB || colspan=26 | || colspan=3 | LSB<br />
|-<br />
|MD32<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|-<br />
|MD33<br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
|-<br />
|MD34<br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
|-<br />
|MD35<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD36<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD37<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|-<br />
|MD38<br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
|}<br />
<br />
An interesting and potentially useful point to note is that flipping bit 28 happens to flip all of the ECC bits together. Another interesting point is that inverting the entire data word produces the same ECC.<br />
<br />
From this information, we can derive some data patterns that produce useful ECC combinations, such as ECC of all zeroes, all ones, only one bit set, and only one bit clear. Looking at the table above, we got lucky and examples of many of these combinations were found by chance. In particular, we happened upon data combinations that produced every possibility of 1 ECC bit set. These, combined with the fact that we can toggle bit 28 to get the inverse ECC bits, gives us a set of data patterns which produce ECC with only one bit clear. From here, we only need to derive a combination which produces all-zero ECC, and from that, derive all-one ECC.<br />
<br />
Starting with the ECC for bit 31 set, we can toggle single bits at a time until we find a combination that produces the ECC we want.<br />
<nowiki><br />
31 1000 0000 0000 0000 0000 0000 0000 0000 1000101<br />
1000 0000 0000 0000 0000 0000 0000 0001 0011101<br />
1000 0000 0000 0000 0000 0010 0000 0001 0110001<br />
1000 0000 1000 0000 0000 0010 0000 0001 0000000 <--<br />
1001 0000 1000 0000 0000 0010 0000 0001 1111111 <--<br />
</nowiki><br />
<br />
The summary of these useful ECC combinations is tabulated below (data in hex, ECC in binary)<br />
<br />
useful ECC combinations:<br />
<br />
{| border=1 style="text-align:center"<br />
| ECC (binary) || data (hex)<br />
|-<br />
| 0000000 || 80800201<br />
|-<br />
| 0000001 || 40000000<br />
|-<br />
| 0000010 || 08000000<br />
|-<br />
| 0000100 || 01000000<br />
|-<br />
| 0001000 || 00020000<br />
|-<br />
| 0010000 || 00000200<br />
|-<br />
| 0100000 || 00000002<br />
|-<br />
| 1000000 || 02000000<br />
|-<br />
| 1111111 || 90800201<br />
|-<br />
| 1111110 || 50000000<br />
|-<br />
| 1111101 || 18000000<br />
|-<br />
| 1111011 || 11000000<br />
|-<br />
| 1110111 || 10020000<br />
|-<br />
| 1101111 || 10000200<br />
|-<br />
| 1011111 || 10000002<br />
|-<br />
| 0111111 || 12000000<br />
|}<br />
<br />
===KA650 Memory Bus Cycles===<br />
<br />
The memory cycles detailed below were captured on an HP 16700A logic analysis system. Memory data and ECC bits were captured, as well as memory address, XA20 and XA21 (inverted back to positive logic by the logic analyzer), the 4 CAS lines, the 4 RAS lines, the WE line, the SE line, the MCLK lines for timing reference. Additionally, the /CAS (DUTCAS), /RAS (DUTRAS), and data line (DUTDATA) of a DRAM located at 0x0XXXXX, bit 0 were captured to show the differences between a selected DRAM and one that was not selected.<br />
<br />
[[File:MS650-AA-Longword-write-same-rank-bank-cycle.png|thumb|none|Longword write cycle]]<br />
<br />
During a longword write cycle, the CMCTL first places the row address onto the memory address bus. Next, it asserts the RAS signal, causing the DRAMs to latch the row address. It then asserts the write enable signal and places the column address on the address bus, then asserts the CAS signal. Lastly, the data and ECC bits are placed on the bus, and some time later CAS deasserts, followed by RAS. On the MS650-AA RAM module, XA20 and XA21 are decoded to determine which bank is selected. Since the DUT being probed here is at address 0x0XXXXX, it is selected during this write.<br />
<br />
[[File:MS650-AA-Longword-write-diff-rank-same-bank-cycle.png|thumb|none|Longword write cycle to a different rank]]<br />
<br />
The CMCTL will assert only the RAS line for the rank which is selected based on the memory address the VAX CPU is accessing. As shown in the next capture, when an address in 0x1XXXXX is written, RAS2 is asserted instead, and thus the DUT being probed was not selected.<br />
<br />
[[File:MS650-AA-Longword-write-same-rank-diff-bank-cycle.png|thumb|none|Longword write cycle to a different bank]]<br />
<br />
Likewise, the MS650-AA decoding circuitry will only allow the RAS line for the bank selected by XA20 and XA21 to be asserted, while ensuring the RAS lines for the other banks are gated off.<br />
<br />
[[File:MS650-AA-byte-write-cycle.png|thumb|none|Byte write cycle]]<br />
<br />
During a byte write cycle, the CMCTL must first read the entire 39 bit word from the MS650, modify the byte which is being written, recalculate the ECC bits, and write the entire 39 bit word back to the MS650. Due to this, both a read and write cycle can be seen within a byte write cycle. Note that the RAS line stays asserted throughout both the read and write parts of the cycle.<br />
<br />
[[File:MS650-AA-qword-write-cycle.png|thumb|none|Quadword write cycle]]<br />
<br />
During a quadword write cycle, two 39 bit words must be written to the MS650. Note that RAS actually cycles twice during this cycle.<br />
<br />
[[File:MS650-AA-read-cycle.png|thumb|none|read cycle]]<br />
<br />
Any read cycle longword or smaller will appear to have the same cycle. Since the MS650 must be read or written as a full 39 bit cycle, there is no effective difference between a byte, word, or longword read. A quadword read, of course, involves reading two 39 bit words, and would thus result in a double cycle similar to the quadword write.<br />
<br />
[[File:MS650-AA-refresh-cycle.png|thumb|none|refresh cycle]]<br />
<br />
Lastly, during a refresh cycle, the SE signal is asserted to force an MS650-AA to allow all banks to be refreshed at once. This would not be necessary for the 1MxX DRAMs on an MS650-BA. Similarly, the CMCTL asserts all RAS lines to load the row to be refreshed into every DRAM connected to the KA650. There is no assertion of CAS since there is no need to actually access a specific location, just to refresh a given row.<br />
<br />
==KA650 VAX Firmware Memory Tests==<br />
<br />
Many of the tests built in to the firmware of the VAX can be quite thorough, if used properly. The tests can be accessed by the TEST command in the monitor, abbreviated to 't'.<br />
<br />
The tests report diagnostic information upon failure, encoded simply as a number of values in registers and memory locations on the stack. With the proper documentation, these values could be decoded to determine the problem. Lacking that documentation, I was able to reverse engineer enough of one test that was failing to understand it's output.<br />
<br />
===TEST 48: MEM_Addr_shrts===<br />
<br />
This test is normally used to check for shorted address lines. It will fill the memory with a pattern first, then it will check each word in order to see if it is still the same pattern. After checking a word, it will check the CMCTL status register to ensure there were no detected errors. Then it will replace the word with another pattern (usually mostly an inverse of the first pattern).<br />
<br />
If any address line is shorted, when the test writes the second pattern, it will affect another location in memory. When that location is encountered, it will read as the wrong data thus showing the issue. However, the test is also capable of detecting stuck bits the way it is designed, and this test happened to find all DRAM errors in my case.<br />
<br />
The output when the test encounters an error looks like the following:<br />
<br />
<nowiki><br />
>>>t 48<br />
<br />
<br />
?48 2 08 FF 00 0002<br />
<br />
P1=00000000 P2=04000000 P3=00000004 P4=00031000 P5=AAAAAAAA<br />
P6=55555555 P7=00000043 P8=200C5875 P9=00000000 P10=2005311F<br />
r0=45555555 r1=000C5860 r2=45555555 r3=00000004 r4=0000006B<br />
r5=AAAAAAAA r6=20080140 r7=20080144 r8=00000000 ERF=80000000<br />
<br />
Normal operation not possible.<br />
<br />
>>><br />
</nowiki><br />
<br />
I figured out the meaning of some of these registers for this test. First of all, P10 indicates an address where presumably DEC personnel would check a source listing to find out the exact meaning of the rest of the values shown. The meanings of the registers I have found are only valid for this routine, located near 2005311F.<br />
<br />
{| border=1 style="text-align:center"<br />
| register || description<br />
|-<br />
| r0 || contents of memory at address being tested<br />
|-<br />
| r1 || address being tested<br />
|-<br />
| r2 || expected pattern from memory being tested<br />
|-<br />
| r5 || pattern to replace location with<br />
|-<br />
| r6 || address of CMCTL MEMCSR16 (a diagnostic register)<br />
|-<br />
| P8 || contents of MEMCSR16<br />
|}<br />
<br />
==MEMCSR16 Register==<br />
<br />
The MEMCSR16 register gives us information on what kind of memory failure<br />
occurred. The bit meanings are as follows, according to the KA650 technical manual:<br />
<br />
{| border=1 style="text-align:center"<br />
| bits || description<br />
|-<br />
| <31> || set if uncorrectable error occurred<br />
|-<br />
| <30> || set if multiple uncorrectable errors occurred<br />
|-<br />
| <29> || set if correctable error occurred<br />
|-<br />
| <28:9> || page address where error occurred (pages are 512 bytes)<br />
|-<br />
| <8> || set if error ocurred during DMA<br />
|-<br />
| <7> || set if CDAL bus parity error occurred<br />
|-<br />
| <6:0> || error syndrome: a unique combination is produced here for each possible single bit error<br />
|}<br />
<br />
writing 1s to bits 31, 30, 29, 8, or 7 of MEMCSR16 resets those bits. bits 28:9 and 6:0 are read only.<br />
<br />
The MEMCSR registers can be read with test 9c.<br />
<br />
===Error Syndrome Field===<br />
<br />
The error syndrome is particularly useful for troubleshooting memory errors as it can tell us exactly which bit had the error. A list of the syndromes and the corresponding bit error is given below.<br />
<br />
{| border=1 style="text-align:center"<br />
| syndrome || bit position or error description<br />
|-<br />
| 0000000 || no error<br />
|-<br />
| 0000001 || 32<br />
|-<br />
| 0000010 || 33<br />
|-<br />
| 0000100 || 34<br />
|-<br />
| 0000111 || result of incorrect check bits written on CDAL parity error<br />
|-<br />
| 0001000 || 35<br />
|-<br />
| 0010000 || 36<br />
|-<br />
| 0011001 || 7<br />
|-<br />
| 0011010 || 2<br />
|-<br />
| 0011100 || 1<br />
|-<br />
| 0011111 || 4<br />
|-<br />
| 0100000 || 37<br />
|-<br />
| 0101001 || 15<br />
|-<br />
| 0101010 || 10<br />
|-<br />
| 0101100 || 9<br />
|-<br />
| 0101111 || 12<br />
|-<br />
| 0110001 || 23<br />
|-<br />
| 0110010 || 18<br />
|-<br />
| 0110100 || 17<br />
|-<br />
| 0110111 || 20<br />
|-<br />
| 0111000 || 24<br />
|-<br />
| 0111011 || 29<br />
|-<br />
| 0111101 || 30<br />
|-<br />
| 0111110 || 27<br />
|-<br />
| 1000000 || 38<br />
|-<br />
| 1011000 || 0<br />
|-<br />
| 1011011 || 5<br />
|-<br />
| 1011101 || 6<br />
|-<br />
| 1011110 || 3<br />
|-<br />
| 1101000 || 8<br />
|-<br />
| 1101011 || 13<br />
|-<br />
| 1101101 || 14<br />
|-<br />
| 1101110 || 11<br />
|-<br />
| 1110000 || 16<br />
|-<br />
| 1110011 || 21<br />
|-<br />
| 1110101 || 22<br />
|-<br />
| 1110110 || 19<br />
|-<br />
| 1111001 || 31<br />
|-<br />
| 1111010 || 26<br />
|-<br />
| 1111100 || 25<br />
|-<br />
| 1111111 || 28<br />
|-<br />
| other || multibit error<br />
|}<br />
<br />
==Troubleshooting==<br />
<br />
We now have all of the information necessary to narrow down which bits in which address regions are bad. However, that doesn't do any good for repair unless we also know which physical DRAMs that bit and region correspond to.<br />
<br />
===MS650-AA===<br />
<br />
Shown below is a diagram of the MS650-AA RAM card, broken up into 11 columns and 37 rows. Each spot in this grid contains up to 1 DRAM, but some locations contain other circuitry instead.<br />
<br />
<nowiki><br />
<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
--------------------------------------------------------------------------------<br />
01 | ooooooooooooooooooooooooo |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 01<br />
| --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
08 | --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 08<br />
|-------------------------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
09 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 09<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
16 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 16<br />
17 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 17<br />
18 |DDDDDDD|TTTTTTT TTTTTTTTT TTTTTTTT |DDDDDDDDDDDDD|TTTTTTTT TTTTTTTTT TTTTTTTT | 18<br />
19 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 19<br />
20 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 20<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
32 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 32<br />
33 |DDDDDDD-----------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 33<br />
36 |DDDDDDD| PPPPPPP TTTTT TTTTT |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 35<br />
37 |-------- TTTTTTT TTTTTTT --------DDDDDDDDDDDDDD-------DDDDDDDDDDDDDD| 37<br />
| -------------- --------------| <br />
| ___- - ___- |<br />
| | | || | | |<br />
-------------------- ----------------------------------------------------------<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
<br />
-----------------------------------------------<br />
| D DRAMS |<br />
| T TTL IC |<br />
| B some kind of DEC custom fast data buffer? |<br />
| P PAL16L8 |<br />
| o data connector |<br />
| | border |<br />
| - border |<br />
-----------------------------------------------<br />
<br />
</nowiki><br />
<br />
The MS650-AA RAM card uses two RAS lines. During normal initialization of the VAX, the rank connected to RAS0 will be first in memory, followed by the rank connected to RAS1. Presumably, the MS650-BA card would have 4 ranks.<br />
<br />
RAS0 - first 4MB<br />
RAS1 - second 4MB<br />
<br />
Based on the bit with the error, as well as the memory region where the error occurred, the specific DRAM with the failure can be found and replaced.<br />
<br />
Below is a list of the DRAMs sorted by memory region and bit, showing the grid location of the DRAM IC.<br />
<br />
By using the built in tests, along with MEMCSR16, and perhaps some manual DEPOSIT and EXAMINE testing, the bad DRAM should be possible to locate and then, using this table, the DRAM can be replaced.<br />
<br />
{| border=1 style="text-align:center"<br />
| DRAM || Address || data bit<br />
|-<br />
| A12 || 0XXXXX || MD00<br />
|-<br />
| A11 || 1XXXXX || MD00<br />
|-<br />
| A10 || 2XXXXX || MD00<br />
|-<br />
| A09 || 3XXXXX || MD00<br />
|-<br />
| A16 || 4XXXXX || MD00<br />
|-<br />
| A15 || 5XXXXX || MD00<br />
|-<br />
| A14 || 6XXXXX || MD00<br />
|-<br />
| A13 || 7XXXXX || MD00<br />
|-<br />
| A24 || 0XXXXX || MD01<br />
|-<br />
| A23 || 1XXXXX || MD01<br />
|-<br />
| A22 || 2XXXXX || MD01<br />
|-<br />
| A21 || 3XXXXX || MD01<br />
|-<br />
| A20 || 4XXXXX || MD01<br />
|-<br />
| A19 || 5XXXXX || MD01<br />
|-<br />
| A18 || 6XXXXX || MD01<br />
|-<br />
| A17 || 7XXXXX || MD01<br />
|-<br />
| A32 || 0XXXXX || MD02<br />
|-<br />
| A31 || 1XXXXX || MD02<br />
|-<br />
| A30 || 2XXXXX || MD02<br />
|-<br />
| A29 || 3XXXXX || MD02<br />
|-<br />
| A28 || 4XXXXX || MD02<br />
|-<br />
| A27 || 5XXXXX || MD02<br />
|-<br />
| A26 || 6XXXXX || MD02<br />
|-<br />
| A25 || 7XXXXX || MD02<br />
|-<br />
| B12 || 0XXXXX || MD03<br />
|-<br />
| B11 || 1XXXXX || MD03<br />
|-<br />
| B10 || 2XXXXX || MD03<br />
|-<br />
| B09 || 3XXXXX || MD03<br />
|-<br />
| A36 || 4XXXXX || MD03<br />
|-<br />
| A35 || 5XXXXX || MD03<br />
|-<br />
| A34 || 6XXXXX || MD03<br />
|-<br />
| A33 || 7XXXXX || MD03<br />
|-<br />
| B24 || 0XXXXX || MD04<br />
|-<br />
| B23 || 1XXXXX || MD04<br />
|-<br />
| B22 || 2XXXXX || MD04<br />
|-<br />
| B21 || 3XXXXX || MD04<br />
|-<br />
| B16 || 4XXXXX || MD04<br />
|-<br />
| B15 || 5XXXXX || MD04<br />
|-<br />
| B14 || 6XXXXX || MD04<br />
|-<br />
| B13 || 7XXXXX || MD04<br />
|-<br />
| B32 || 0XXXXX || MD05<br />
|-<br />
| B31 || 1XXXXX || MD05<br />
|-<br />
| B30 || 2XXXXX || MD05<br />
|-<br />
| B29 || 3XXXXX || MD05<br />
|-<br />
| B28 || 4XXXXX || MD05<br />
|-<br />
| B27 || 5XXXXX || MD05<br />
|-<br />
| B26 || 6XXXXX || MD05<br />
|-<br />
| B25 || 7XXXXX || MD05<br />
|-<br />
| C12 || 0XXXXX || MD06<br />
|-<br />
| C11 || 1XXXXX || MD06<br />
|-<br />
| C10 || 2XXXXX || MD06<br />
|-<br />
| C09 || 3XXXXX || MD06<br />
|-<br />
| C16 || 4XXXXX || MD06<br />
|-<br />
| C15 || 5XXXXX || MD06<br />
|-<br />
| C14 || 6XXXXX || MD06<br />
|-<br />
| C13 || 7XXXXX || MD06<br />
|-<br />
| C24 || 0XXXXX || MD07<br />
|-<br />
| C23 || 1XXXXX || MD07<br />
|-<br />
| C22 || 2XXXXX || MD07<br />
|-<br />
| C21 || 3XXXXX || MD07<br />
|-<br />
| E20 || 4XXXXX || MD07<br />
|-<br />
| D20 || 5XXXXX || MD07<br />
|-<br />
| C20 || 6XXXXX || MD07<br />
|-<br />
| B20 || 7XXXXX || MD07<br />
|-<br />
| C32 || 0XXXXX || MD08<br />
|-<br />
| C31 || 1XXXXX || MD08<br />
|-<br />
| C30 || 2XXXXX || MD08<br />
|-<br />
| C29 || 3XXXXX || MD08<br />
|-<br />
| C28 || 4XXXXX || MD08<br />
|-<br />
| C27 || 5XXXXX || MD08<br />
|-<br />
| C26 || 6XXXXX || MD08<br />
|-<br />
| C25 || 7XXXXX || MD08<br />
|-<br />
| D32 || 0XXXXX || MD09<br />
|-<br />
| D31 || 1XXXXX || MD09<br />
|-<br />
| D30 || 2XXXXX || MD09<br />
|-<br />
| D29 || 3XXXXX || MD09<br />
|-<br />
| D28 || 4XXXXX || MD09<br />
|-<br />
| D27 || 5XXXXX || MD09<br />
|-<br />
| D26 || 6XXXXX || MD09<br />
|-<br />
| D25 || 7XXXXX || MD09<br />
|-<br />
| D24 || 0XXXXX || MD10<br />
|-<br />
| D23 || 1XXXXX || MD10<br />
|-<br />
| D22 || 2XXXXX || MD10<br />
|-<br />
| D21 || 3XXXXX || MD10<br />
|-<br />
| D16 || 4XXXXX || MD10<br />
|-<br />
| D15 || 5XXXXX || MD10<br />
|-<br />
| D14 || 6XXXXX || MD10<br />
|-<br />
| D13 || 7XXXXX || MD10<br />
|-<br />
| D12 || 0XXXXX || MD11<br />
|-<br />
| D11 || 1XXXXX || MD11<br />
|-<br />
| D10 || 2XXXXX || MD11<br />
|-<br />
| D09 || 3XXXXX || MD11<br />
|-<br />
| E16 || 4XXXXX || MD11<br />
|-<br />
| E15 || 5XXXXX || MD11<br />
|-<br />
| E14 || 6XXXXX || MD11<br />
|-<br />
| E13 || 7XXXXX || MD11<br />
|-<br />
| E12 || 0XXXXX || MD12<br />
|-<br />
| E11 || 1XXXXX || MD12<br />
|-<br />
| E10 || 2XXXXX || MD12<br />
|-<br />
| E09 || 3XXXXX || MD12<br />
|-<br />
| E28 || 4XXXXX || MD12<br />
|-<br />
| E27 || 5XXXXX || MD12<br />
|-<br />
| E26 || 6XXXXX || MD12<br />
|-<br />
| E25 || 7XXXXX || MD12<br />
|-<br />
| E24 || 0XXXXX || MD13<br />
|-<br />
| E23 || 1XXXXX || MD13<br />
|-<br />
| E22 || 2XXXXX || MD13<br />
|-<br />
| E21 || 3XXXXX || MD13<br />
|-<br />
| F16 || 4XXXXX || MD13<br />
|-<br />
| F15 || 5XXXXX || MD13<br />
|-<br />
| F14 || 6XXXXX || MD13<br />
|-<br />
| F13 || 7XXXXX || MD13<br />
|-<br />
| E32 || 0XXXXX || MD14<br />
|-<br />
| E31 || 1XXXXX || MD14<br />
|-<br />
| E30 || 2XXXXX || MD14<br />
|-<br />
| E29 || 3XXXXX || MD14<br />
|-<br />
| F20 || 4XXXXX || MD14<br />
|-<br />
| F19 || 5XXXXX || MD14<br />
|-<br />
| F18 || 6XXXXX || MD14<br />
|-<br />
| F17 || 7XXXXX || MD14<br />
|-<br />
| F32 || 0XXXXX || MD15<br />
|-<br />
| F31 || 1XXXXX || MD15<br />
|-<br />
| F30 || 2XXXXX || MD15<br />
|-<br />
| F29 || 3XXXXX || MD15<br />
|-<br />
| F28 || 4XXXXX || MD15<br />
|-<br />
| F27 || 5XXXXX || MD15<br />
|-<br />
| F26 || 6XXXXX || MD15<br />
|-<br />
| F25 || 7XXXXX || MD15<br />
|-<br />
| F24 || 0XXXXX || MD16<br />
|-<br />
| F23 || 1XXXXX || MD16<br />
|-<br />
| F22 || 2XXXXX || MD16<br />
|-<br />
| F21 || 3XXXXX || MD16<br />
|-<br />
| F36 || 4XXXXX || MD16<br />
|-<br />
| F35 || 5XXXXX || MD16<br />
|-<br />
| F34 || 6XXXXX || MD16<br />
|-<br />
| F33 || 7XXXXX || MD16<br />
|-<br />
| G32 || 0XXXXX || MD17<br />
|-<br />
| G31 || 1XXXXX || MD17<br />
|-<br />
| G30 || 2XXXXX || MD17<br />
|-<br />
| G29 || 3XXXXX || MD17<br />
|-<br />
| G36 || 4XXXXX || MD17<br />
|-<br />
| G35 || 5XXXXX || MD17<br />
|-<br />
| G34 || 6XXXXX || MD17<br />
|-<br />
| G33 || 7XXXXX || MD17<br />
|-<br />
| G24 || 0XXXXX || MD18<br />
|-<br />
| G23 || 1XXXXX || MD18<br />
|-<br />
| G22 || 2XXXXX || MD18<br />
|-<br />
| G21 || 3XXXXX || MD18<br />
|-<br />
| G28 || 4XXXXX || MD18<br />
|-<br />
| G27 || 5XXXXX || MD18<br />
|-<br />
| G26 || 6XXXXX || MD18<br />
|-<br />
| G25 || 7XXXXX || MD18<br />
|-<br />
| H32 || 0XXXXX || MD19<br />
|-<br />
| H31 || 1XXXXX || MD19<br />
|-<br />
| H30 || 2XXXXX || MD19<br />
|-<br />
| H29 || 3XXXXX || MD19<br />
|-<br />
| G20 || 4XXXXX || MD19<br />
|-<br />
| G19 || 5XXXXX || MD19<br />
|-<br />
| G18 || 6XXXXX || MD19<br />
|-<br />
| G17 || 7XXXXX || MD19<br />
|-<br />
| H24 || 0XXXXX || MD20<br />
|-<br />
| H23 || 1XXXXX || MD20<br />
|-<br />
| H22 || 2XXXXX || MD20<br />
|-<br />
| H21 || 3XXXXX || MD20<br />
|-<br />
| K37 || 4XXXXX || MD20<br />
|-<br />
| J37 || 5XXXXX || MD20<br />
|-<br />
| H37 || 6XXXXX || MD20<br />
|-<br />
| G37 || 7XXXXX || MD20<br />
|-<br />
| I32 || 0XXXXX || MD21<br />
|-<br />
| I31 || 1XXXXX || MD21<br />
|-<br />
| I30 || 2XXXXX || MD21<br />
|-<br />
| I29 || 3XXXXX || MD21<br />
|-<br />
| H36 || 4XXXXX || MD21<br />
|-<br />
| H35 || 5XXXXX || MD21<br />
|-<br />
| H34 || 6XXXXX || MD21<br />
|-<br />
| H33 || 7XXXXX || MD21<br />
|-<br />
| I24 || 0XXXXX || MD22<br />
|-<br />
| I23 || 1XXXXX || MD22<br />
|-<br />
| I22 || 2XXXXX || MD22<br />
|-<br />
| I21 || 3XXXXX || MD22<br />
|-<br />
| H28 || 4XXXXX || MD22<br />
|-<br />
| H27 || 5XXXXX || MD22<br />
|-<br />
| H26 || 6XXXXX || MD22<br />
|-<br />
| H25 || 7XXXXX || MD22<br />
|-<br />
| J32 || 0XXXXX || MD23<br />
|-<br />
| J31 || 1XXXXX || MD23<br />
|-<br />
| J30 || 2XXXXX || MD23<br />
|-<br />
| J29 || 3XXXXX || MD23<br />
|-<br />
| I36 || 4XXXXX || MD23<br />
|-<br />
| I35 || 5XXXXX || MD23<br />
|-<br />
| I34 || 6XXXXX || MD23<br />
|-<br />
| I33 || 7XXXXX || MD23<br />
|-<br />
| J24 || 0XXXXX || MD24<br />
|-<br />
| J23 || 1XXXXX || MD24<br />
|-<br />
| J22 || 2XXXXX || MD24<br />
|-<br />
| J21 || 3XXXXX || MD24<br />
|-<br />
| I28 || 4XXXXX || MD24<br />
|-<br />
| I27 || 5XXXXX || MD24<br />
|-<br />
| I26 || 6XXXXX || MD24<br />
|-<br />
| I25 || 7XXXXX || MD24<br />
|-<br />
| K32 || 0XXXXX || MD25<br />
|-<br />
| K31 || 1XXXXX || MD25<br />
|-<br />
| K30 || 2XXXXX || MD25<br />
|-<br />
| K29 || 3XXXXX || MD25<br />
|-<br />
| J36 || 4XXXXX || MD25<br />
|-<br />
| J35 || 5XXXXX || MD25<br />
|-<br />
| J34 || 6XXXXX || MD25<br />
|-<br />
| J33 || 7XXXXX || MD25<br />
|-<br />
| K24 || 0XXXXX || MD26<br />
|-<br />
| K23 || 1XXXXX || MD26<br />
|-<br />
| K22 || 2XXXXX || MD26<br />
|-<br />
| K21 || 3XXXXX || MD26<br />
|-<br />
| J28 || 4XXXXX || MD26<br />
|-<br />
| J27 || 5XXXXX || MD26<br />
|-<br />
| J26 || 6XXXXX || MD26<br />
|-<br />
| J25 || 7XXXXX || MD26<br />
|-<br />
| K20 || 0XXXXX || MD27<br />
|-<br />
| J20 || 1XXXXX || MD27<br />
|-<br />
| I20 || 2XXXXX || MD27<br />
|-<br />
| H20 || 3XXXXX || MD27<br />
|-<br />
| K36 || 4XXXXX || MD27<br />
|-<br />
| K35 || 5XXXXX || MD27<br />
|-<br />
| K34 || 6XXXXX || MD27<br />
|-<br />
| K33 || 7XXXXX || MD27<br />
|-<br />
| F12 || 0XXXXX || MD28<br />
|-<br />
| F11 || 1XXXXX || MD28<br />
|-<br />
| F10 || 2XXXXX || MD28<br />
|-<br />
| F09 || 3XXXXX || MD28<br />
|-<br />
| K28 || 4XXXXX || MD28<br />
|-<br />
| K26 || 6XXXXX || MD28<br />
|-<br />
| K27 || 5XXXXX || MD28<br />
|-<br />
| K25 || 7XXXXX || MD28<br />
|-<br />
| G12 || 0XXXXX || MD29<br />
|-<br />
| G11 || 1XXXXX || MD29<br />
|-<br />
| G10 || 2XXXXX || MD29<br />
|-<br />
| G09 || 3XXXXX || MD29<br />
|-<br />
| G16 || 4XXXXX || MD29<br />
|-<br />
| G15 || 5XXXXX || MD29<br />
|-<br />
| G14 || 6XXXXX || MD29<br />
|-<br />
| G13 || 7XXXXX || MD29<br />
|-<br />
| G04 || 0XXXXX || MD30<br />
|-<br />
| G03 || 1XXXXX || MD30<br />
|-<br />
| G02 || 2XXXXX || MD30<br />
|-<br />
| G01 || 3XXXXX || MD30<br />
|-<br />
| G08 || 4XXXXX || MD30<br />
|-<br />
| G07 || 5XXXXX || MD30<br />
|-<br />
| G06 || 6XXXXX || MD30<br />
|-<br />
| G05 || 7XXXXX || MD30<br />
|-<br />
| H04 || 0XXXXX || MD31<br />
|-<br />
| H03 || 1XXXXX || MD31<br />
|-<br />
| H02 || 2XXXXX || MD31<br />
|-<br />
| H01 || 3XXXXX || MD31<br />
|-<br />
| H08 || 4XXXXX || MD31<br />
|-<br />
| H07 || 5XXXXX || MD31<br />
|-<br />
| H06 || 6XXXXX || MD31<br />
|-<br />
| H05 || 7XXXXX || MD31<br />
|-<br />
| H12 || 0XXXXX || MD32<br />
|-<br />
| H11 || 1XXXXX || MD32<br />
|-<br />
| H10 || 2XXXXX || MD32<br />
|-<br />
| H09 || 3XXXXX || MD32<br />
|-<br />
| H16 || 4XXXXX || MD32<br />
|-<br />
| H15 || 5XXXXX || MD32<br />
|-<br />
| H14 || 6XXXXX || MD32<br />
|-<br />
| H13 || 7XXXXX || MD32<br />
|-<br />
| I04 || 0XXXXX || MD33<br />
|-<br />
| I03 || 1XXXXX || MD33<br />
|-<br />
| I02 || 2XXXXX || MD33<br />
|-<br />
| I01 || 3XXXXX || MD33<br />
|-<br />
| I08 || 4XXXXX || MD33<br />
|-<br />
| I07 || 5XXXXX || MD33<br />
|-<br />
| I06 || 6XXXXX || MD33<br />
|-<br />
| I05 || 7XXXXX || MD33<br />
|-<br />
| I12 || 0XXXXX || MD34<br />
|-<br />
| I11 || 1XXXXX || MD34<br />
|-<br />
| I10 || 2XXXXX || MD34<br />
|-<br />
| I09 || 3XXXXX || MD34<br />
|-<br />
| I16 || 4XXXXX || MD34<br />
|-<br />
| I15 || 5XXXXX || MD34<br />
|-<br />
| I14 || 6XXXXX || MD34<br />
|-<br />
| I13 || 7XXXXX || MD34<br />
|-<br />
| J04 || 0XXXXX || MD35<br />
|-<br />
| J03 || 1XXXXX || MD35<br />
|-<br />
| J02 || 2XXXXX || MD35<br />
|-<br />
| J01 || 3XXXXX || MD35<br />
|-<br />
| J08 || 4XXXXX || MD35<br />
|-<br />
| J07 || 5XXXXX || MD35<br />
|-<br />
| J06 || 6XXXXX || MD35<br />
|-<br />
| J05 || 7XXXXX || MD35<br />
|-<br />
| J12 || 0XXXXX || MD36<br />
|-<br />
| J11 || 1XXXXX || MD36<br />
|-<br />
| J10 || 2XXXXX || MD36<br />
|-<br />
| J09 || 3XXXXX || MD36<br />
|-<br />
| J16 || 4XXXXX || MD36<br />
|-<br />
| J15 || 5XXXXX || MD36<br />
|-<br />
| J14 || 6XXXXX || MD36<br />
|-<br />
| J13 || 7XXXXX || MD36<br />
|-<br />
| K04 || 0XXXXX || MD37<br />
|-<br />
| K03 || 1XXXXX || MD37<br />
|-<br />
| K02 || 2XXXXX || MD37<br />
|-<br />
| K01 || 3XXXXX || MD37<br />
|-<br />
| K08 || 4XXXXX || MD37<br />
|-<br />
| K07 || 5XXXXX || MD37<br />
|-<br />
| K06 || 6XXXXX || MD37<br />
|-<br />
| K05 || 7XXXXX || MD37<br />
|-<br />
| K12 || 0XXXXX || MD38<br />
|-<br />
| K11 || 1XXXXX || MD38<br />
|-<br />
| K10 || 2XXXXX || MD38<br />
|-<br />
| K09 || 3XXXXX || MD38<br />
|-<br />
| K16 || 4XXXXX || MD38<br />
|-<br />
| K15 || 5XXXXX || MD38<br />
|-<br />
| K14 || 6XXXXX || MD38<br />
|-<br />
| K13 || 7XXXXX || MD38<br />
|}<br />
<br />
===MS650-BA===<br />
<br />
Because I did not have an MS650-BA to test, I do not have as much information on this module as on the MS650-AA. Presumably, the MS650-BA has 4 ranks of 4MB in 1MBxX DRAMs, meaning there is no need to have 4 banks in each rank like the 256kx1 DRAMs on the MS650-AA.<br />
<br />
==External Links==<br />
<br />
* [https://youtu.be/eDMhdAEFEgc Youtube - KA650 Memory Troubleshooting]<br />
<br />
==References==<br />
<br />
<div id="KA650-print-set">[1] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="KA650-technical-manual">[2] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div></div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_Main_Memory_System&diff=21870
KA650 Main Memory System
2019-11-24T17:05:29Z
<p>Jzatarski: added some linking, reformatted memory cycles section</p>
<hr />
<div>This page contains notes on troubleshooting, repair, and theory of operation of the [[DEC KA650]]/[[MS650]] memory subsystem.<br />
<br />
==Overview==<br />
<br />
The MS650-AA and MS650-BA memory module are intended to be used with the [[DEC KA650]] [[VAX]] [[CPU]], as the name might suggest. These quad width cards contain 8MB and 16MB of RAM for the VAX, respectively, complete with [[ECC]].<br />
<br />
==Theory of Operation==<br />
<br />
===Memory Controller General Architecture and Organization===<br />
<br />
====Memory Control Signals Provided by the CMCTL====<br />
The CMCTL IC is the [[DRAM]] controller for the KA650 CPU. It has 10 address line outputs, 39 memory data I/O lines (MD), 4 CAS outputs, 4 RAS outputs, a WE pin, and an SE pin. Also available to the RAM card are the inverse of the 20th and 21st address lines (XA20 & XA21), which are used as bank selection when using 256kxX DRAMs. The data lines are provided to the RAM cards through a 50 conductor ribbon cable, while the rest of the control lines are provided through the CD interconnect on the backplane. [[#KA650-print-set|[1]]]<br />
<br />
The 10 address lines carry the row address on the rising edge of a RAS line, followed by the column address on the rising edge of a CAS line.<br />
<br />
The 39 data I/O lines carry the 32 data and 7 ECC bits for the RAM.<br />
<br />
The 4 CAS (Column Address Strobe) lines allow strobing the column address on up to 4 separate memory modules.<br />
<br />
The 4 RAS (Row Address Strobe) lines allow selection of up to 4 banks on a single memory module.<br />
<br />
The WE (Write Enable) pin indicates that the CMCTL is writing to memory, rather than reading.<br />
<br />
The SE (Strobe Enable?) pin seems to indicate that the CMCTL is refreshing memory. This is necessary for the 8MB card to correctly strobe the RAS lines of each bank during a refresh cycle, due to the extra RAS gating circuitry necessary on cards with 256kxX DRAMs.<br />
<br />
The XA20 and XA21 lines are the inverse of the latched address lines from the CDAL bus.<br />
<br />
Note that many of the above control lines are inverse logic from what is normally used to drive DRAMs; in particular, CAS, RAS, and WE lines are inverted from the normal JEDEC DRAM convention of active low /RAS, /CAS, and /WE.<br />
<br />
====Memory Ranks & Banks====<br />
<br />
Due to the 10 bit address bus using conventional multiplexed row and column DRAM addressing, an effective 20 bit address is formed. This allows the CMCTL to address up to 1MWord per rank.<br />
<br />
By strobing different pairings of RAS and CAS (RAS0+CAS0 is one rank, while RAS0+CAS1 is another rank, while RAS1+CAS0 is yet another rank), the CMCTL supports up to 16 ranks of RAM, each 1Mx39. Each rank is thus 4MB of memory once ECC overhead is accounted for. This puts a 64MB cap on the maximum amount of memory the CMCTL can address (16 ranks of 4MB).<br />
<br />
When 256kxX DRAMs are used in place of 1MxX DRAMs, each 1Mx39 rank is further divided into 4 banks of 256kx39. Each bank is selected by XA20 and XA21, which are provided to the RAM cards via the CD interconnect. These address bits appear to only be valid on the rising edge of RAS. Before CAS has strobed, the bits have generally already changed since these are derived from the CDAL bus of the VAX CPU. These bits are used to gate the /RAS lines to the DRAMs ensuring that only the selected bank is addressed. The /CAS line for the card is not affected.<br />
<br />
The MS650-AA card contains 312 256kx1 ZIP DRAMs, organized into 8 banks of 256kx39. As previously mentioned, one memory rank as addressed by the CMCTL memory controller consists of 4 banks, making up a total of 1MWord of memory per rank. Each DRAM on the card corresponds to one bit of the 39 bit word within a 1MB address region of the VAX.<br />
<br />
===Addressing===<br />
<br />
The CMCTL appears to convert 32 bit VAX addresses into DRAM addressing as follows:<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
| A21 || A20 || A19 || A18 || A17 || A16 || A15 || A14 || A13 || A12 || A11 || A10 || A09 || A08 || A07 || A06 || A05 || A04 || A03 || A02<br />
|-<br />
| width=2.5% | R09 <br />
| width=2.5% | <br />
| width=2.5% | R08<br />
| width=2.5% | R07<br />
| width=2.5% | R06<br />
| width=2.5% | R05<br />
| width=2.5% | R04<br />
| width=2.5% | R03<br />
| width=2.5% | R02<br />
| width=2.5% | R01<br />
| width=2.5% | R00<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
|-<br />
| width=2.5% | <br />
| width=2.5% | C09<br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | C08<br />
| width=2.5% | C07<br />
| width=2.5% | C06<br />
| width=2.5% | C05<br />
| width=2.5% | C04<br />
| width=2.5% | C03<br />
| width=2.5% | C02<br />
| width=2.5% | C01<br />
| width=2.5% | C00<br />
|}<br />
<br />
Axx are VAX address lines<br />
Rxx are DRAM row address bits<br />
Cxx are DRAM column address bits<br />
<br />
This addressing scheme is used to ensure that 256kxX DRAMs (which use only 9 bit row and column addresses) are still supported for use with the CMCTL.<br />
<br />
It is, of course, still up to the CMCTL to determine which ranks are selected by the upper bits of a given physical address. This is determined by the MEMCSR0-15 registers, which seem to specify whether or not a bank is present, as well as what base address it resides at. It may perform other functions, but it does not seem to be documented in available documentation.<br />
<br />
===CAS and RAS Signals===<br />
<br />
Each 16MB or 8MB memory card for the KA650 uses one CAS line in its entirety. This is why a maximum of 4 cards may be used in a KA650 system. Each RAM card uses the first CAS line, and passes the remaining lines on to the next card, shifted down one bit. So for example, the first card gets CAS0 CAS1 CAS2 CAS3, in that order. It uses CAS0 and passes CAS1 CAS2 and CAS3 on to the next card, in that order. The next card uses CAS1 and passes on CAS2 and CAS3. This repeats until 4 cards have used up all of the available CAS lines.<br />
<br />
The CAS line is not gated in any way on the MS650-AA. The CAS line is simply buffered, inverted to match the polarity of the DRAMs, and distributed to all DRAMs on the card (likely with some hierarchical buffering methodology).<br />
<br />
RAS lines, on the other hand, are shared between all the cards in the system. The first rank of DRAMs on the card are address by RAS0, the second by RAS1, etc. As previously mentioned, the RAS lines to each bank within a rank are gated on or off by decoding circuitry based on the state of XA20/XA21.<br />
<br />
===Refresh===<br />
<br />
DRAMs are built using one tiny MOS capacitor for each bit. These capacitors leak slightly and need to be periodically refreshed. DRAM rows are refreshed by simply addressing a row. Any row access refreshes that row, no column needs to be strobed for a refresh.<br />
<br />
As such, during refresh cycles, the CMCTL places a row address to be refreshed on the address bus, asserts SE, and asserts all RAS lines for several clock cycles. The purpose of the SE signal is so that RAM cards with 256kxX DRAMs do not gate any of the /RAS lines going to the DRAMs, or else only whatever DRAM bank is (randomly) addressed by XA20 and XA21 would be refreshed.<br />
<br />
===ECC===<br />
<br />
The ECC supported by the CMCTL has the ability to detect and correct single data bit errors, detect single ECC bit errors, and detect double-bit data errors. [[#KA650-technical-manual|[2]]]<br />
<br />
[[ECC]] is generally based on producing parity bits of various collections of data bits. Since parity is based around the simple XOR, it is a linear operation in a manner of speaking. Luckily this means we can determine the ECC equations based on a number of sample data patterns and the respective ECC bits, such as the ECC produced for 0 data, and data with only one bit in the word set. By comparing the ECC for each test pattern to that of 0, we can determine which ECC bits each bit in the data word affects.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| bit || colspan=8 | data || ECC<br />
|-<br />
| || MSB || colspan = 6 | || LSB ||<br />
|-<br />
| - || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0111100<br />
|-<br />
| 0 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 1100100<br />
|-<br />
| 1 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0100000<br />
|-<br />
| 2 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0100110<br />
|-<br />
| 3 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 1100010<br />
|-<br />
| 4 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0100011<br />
|-<br />
| 5 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 1100111<br />
|-<br />
| 6 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 1100001<br />
|-<br />
| 7 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0100101<br />
|-<br />
| 8 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 1010100<br />
|-<br />
| 9 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0010000<br />
|-<br />
| 10 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0010110<br />
|-<br />
| 11 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 1010010<br />
|-<br />
| 12 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0010011<br />
|-<br />
| 13 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 1010111<br />
|-<br />
| 14 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 1010001<br />
|-<br />
| 15 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0010101<br />
|-<br />
| 16 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 1001100<br />
|-<br />
| 17 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0001000<br />
|-<br />
| 18 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0001110<br />
|-<br />
| 19 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 1001010<br />
|-<br />
| 20 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001011<br />
|-<br />
| 21 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001111<br />
|-<br />
| 22 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001001<br />
|-<br />
| 23 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001101<br />
|-<br />
| 24 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000100<br />
|-<br />
| 25 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000000<br />
|-<br />
| 26 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000110<br />
|-<br />
| 27 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000010<br />
|-<br />
| 28 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000011<br />
|-<br />
| 29 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000111<br />
|-<br />
| 30 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000001<br />
|-<br />
| 31 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000101<br />
|}<br />
<br />
<br />
The results of this are depicted below. The basic result is that toggling one of the bits that belongs to the ECC bit group will result in that ECC bit toggling as well.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| ECC bit || colspan=3 | MSB || colspan=26 | || colspan=3 | LSB<br />
|-<br />
|MD32<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|-<br />
|MD33<br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
|-<br />
|MD34<br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
|-<br />
|MD35<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD36<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD37<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|-<br />
|MD38<br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
|}<br />
<br />
An interesting and potentially useful point to note is that flipping bit 28 happens to flip all of the ECC bits together. Another interesting point is that inverting the entire data word produces the same ECC.<br />
<br />
From this information, we can derive some data patterns that produce useful ECC combinations, such as ECC of all zeroes, all ones, only one bit set, and only one bit clear. Looking at the table above, we got lucky and examples of many of these combinations were found by chance. In particular, we happened upon data combinations that produced every possibility of 1 ECC bit set. These, combined with the fact that we can toggle bit 28 to get the inverse ECC bits, gives us a set of data patterns which produce ECC with only one bit clear. From here, we only need to derive a combination which produces all-zero ECC, and from that, derive all-one ECC.<br />
<br />
Starting with the ECC for bit 31 set, we can toggle single bits at a time until we find a combination that produces the ECC we want.<br />
<nowiki><br />
31 1000 0000 0000 0000 0000 0000 0000 0000 1000101<br />
1000 0000 0000 0000 0000 0000 0000 0001 0011101<br />
1000 0000 0000 0000 0000 0010 0000 0001 0110001<br />
1000 0000 1000 0000 0000 0010 0000 0001 0000000 <--<br />
1001 0000 1000 0000 0000 0010 0000 0001 1111111 <--<br />
</nowiki><br />
<br />
The summary of these useful ECC combinations is tabulated below (data in hex, ECC in binary)<br />
<br />
useful ECC combinations:<br />
<br />
{| border=1 style="text-align:center"<br />
| ECC (binary) || data (hex)<br />
|-<br />
| 0000000 || 80800201<br />
|-<br />
| 0000001 || 40000000<br />
|-<br />
| 0000010 || 08000000<br />
|-<br />
| 0000100 || 01000000<br />
|-<br />
| 0001000 || 00020000<br />
|-<br />
| 0010000 || 00000200<br />
|-<br />
| 0100000 || 00000002<br />
|-<br />
| 1000000 || 02000000<br />
|-<br />
| 1111111 || 90800201<br />
|-<br />
| 1111110 || 50000000<br />
|-<br />
| 1111101 || 18000000<br />
|-<br />
| 1111011 || 11000000<br />
|-<br />
| 1110111 || 10020000<br />
|-<br />
| 1101111 || 10000200<br />
|-<br />
| 1011111 || 10000002<br />
|-<br />
| 0111111 || 12000000<br />
|}<br />
<br />
===KA650 Memory Bus Cycles===<br />
<br />
The memory cycles detailed below were captured on an HP 16700A logic analysis system. Memory data and ECC bits were captured, as well as memory address, XA20 and XA21 (inverted back to positive logic by the logic analyzer), the 4 CAS lines, the 4 RAS lines, the WE line, the SE line, the MCLK lines for timing reference. Additionally, the /CAS (DUTCAS), /RAS (DUTRAS), and data line (DUTDATA) of a DRAM located at 0x0XXXXX, bit 0 were captured to show the differences between a selected DRAM and one that was not selected.<br />
<br />
[[File:MS650-AA-Longword-write-same-rank-bank-cycle.png|thumb|none|Longword write cycle]]<br />
<br />
During a longword write cycle, the CMCTL first places the row address onto the memory address bus. Next, it asserts the RAS signal, causing the DRAMs to latch the row address. It then asserts the write enable signal and places the column address on the address bus, then asserts the CAS signal. Lastly, the data and ECC bits are placed on the bus, and some time later CAS deasserts, followed by RAS. On the MS650-AA RAM module, XA20 and XA21 are decoded to determine which bank is selected. Since the DUT being probed here is at address 0x0XXXXX, it is selected during this write.<br />
<br />
[[File:MS650-AA-Longword-write-diff-rank-same-bank-cycle.png|thumb|none|Longword write cycle to a different rank]]<br />
<br />
The CMCTL will assert only the RAS line for the rank which is selected based on the memory address the VAX CPU is accessing. As shown in the next capture, when an address in 0x1XXXXX is written, RAS2 is asserted instead, and thus the DUT being probed was not selected.<br />
<br />
[[File:MS650-AA-Longword-write-same-rank-diff-bank-cycle.png|thumb|none|Longword write cycle to a different bank]]<br />
<br />
Likewise, the MS650-AA decoding circuitry will only allow the RAS line for the bank selected by XA20 and XA21 to be asserted, while ensuring the RAS lines for the other banks are gated off.<br />
<br />
[[File:MS650-AA-byte-write-cycle.png|thumb|none|Byte write cycle]]<br />
<br />
During a byte write cycle, the CMCTL must first read the entire 39 bit word from the MS650, modify the byte which is being written, recalculate the ECC bits, and write the entire 39 bit word back to the MS650. Due to this, both a read and write cycle can be seen within a byte write cycle. Note that the RAS line stays asserted throughout both the read and write parts of the cycle.<br />
<br />
[[File:MS650-AA-qword-write-cycle.png|thumb|none|Quadword write cycle]]<br />
<br />
During a quadword write cycle, two 39 bit words must be written to the MS650. Note that RAS actually cycles twice during this cycle.<br />
<br />
[[File:MS650-AA-read-cycle.png|thumb|none|read cycle]]<br />
<br />
Any read cycle longword or smaller will appear to have the same cycle. Since the MS650 must be read or written as a full 39 bit cycle, there is no effective difference between a byte, word, or longword read. A quadword read, of course, involves reading two 39 bit words, and would thus result in a double cycle similar to the quadword write.<br />
<br />
[[File:MS650-AA-refresh-cycle.png|thumb|none|refresh cycle]]<br />
<br />
Lastly, during a refresh cycle, the SE signal is asserted to force an MS650-AA to allow all banks to be refreshed at once. This would not be necessary for the 1MxX DRAMs on an MS650-BA. Similarly, the CMCTL asserts all RAS lines to load the row to be refreshed into every DRAM connected to the KA650. There is no assertion of CAS since there is no need to actually access a specific location, just to refresh a given row.<br />
<br />
==KA650 VAX Firmware Memory Tests==<br />
<br />
Many of the tests built in to the firmware of the VAX can be quite thorough, if used properly. The tests can be accessed by the TEST command in the monitor, abbreviated to 't'.<br />
<br />
The tests report diagnostic information upon failure, encoded simply as a number of values in registers and memory locations on the stack. With the proper documentation, these values could be decoded to determine the problem. Lacking that documentation, I was able to reverse engineer enough of one test that was failing to understand it's output.<br />
<br />
===TEST 48: MEM_Addr_shrts===<br />
<br />
This test is normally used to check for shorted address lines. It will fill the memory with a pattern first, then it will check each word in order to see if it is still the same pattern. After checking a word, it will check the CMCTL status register to ensure there were no detected errors. Then it will replace the word with another pattern (usually mostly an inverse of the first pattern).<br />
<br />
If any address line is shorted, when the test writes the second pattern, it will affect another location in memory. When that location is encountered, it will read as the wrong data thus showing the issue. However, the test is also capable of detecting stuck bits the way it is designed, and this test happened to find all DRAM errors in my case.<br />
<br />
The output when the test encounters an error looks like the following:<br />
<br />
<nowiki><br />
>>>t 48<br />
<br />
<br />
?48 2 08 FF 00 0002<br />
<br />
P1=00000000 P2=04000000 P3=00000004 P4=00031000 P5=AAAAAAAA<br />
P6=55555555 P7=00000043 P8=200C5875 P9=00000000 P10=2005311F<br />
r0=45555555 r1=000C5860 r2=45555555 r3=00000004 r4=0000006B<br />
r5=AAAAAAAA r6=20080140 r7=20080144 r8=00000000 ERF=80000000<br />
<br />
Normal operation not possible.<br />
<br />
>>><br />
</nowiki><br />
<br />
I figured out the meaning of some of these registers for this test. First of all, P10 indicates an address where presumably DEC personnel would check a source listing to find out the exact meaning of the rest of the values shown. The meanings of the registers I have found are only valid for this routine, located near 2005311F.<br />
<br />
{| border=1 style="text-align:center"<br />
| register || description<br />
|-<br />
| r0 || contents of memory at address being tested<br />
|-<br />
| r1 || address being tested<br />
|-<br />
| r2 || expected pattern from memory being tested<br />
|-<br />
| r5 || pattern to replace location with<br />
|-<br />
| r6 || address of CMCTL MEMCSR16 (a diagnostic register)<br />
|-<br />
| P8 || contents of MEMCSR16<br />
|}<br />
<br />
==MEMCSR16 Register==<br />
<br />
The MEMCSR16 register gives us information on what kind of memory failure<br />
occurred. The bit meanings are as follows, according to the KA650 technical manual:<br />
<br />
{| border=1 style="text-align:center"<br />
| bits || description<br />
|-<br />
| <31> || set if uncorrectable error occurred<br />
|-<br />
| <30> || set if multiple uncorrectable errors occurred<br />
|-<br />
| <29> || set if correctable error occurred<br />
|-<br />
| <28:9> || page address where error occurred (pages are 512 bytes)<br />
|-<br />
| <8> || set if error ocurred during DMA<br />
|-<br />
| <7> || set if CDAL bus parity error occurred<br />
|-<br />
| <6:0> || error syndrome: a unique combination is produced here for each possible single bit error<br />
|}<br />
<br />
writing 1s to bits 31, 30, 29, 8, or 7 of MEMCSR16 resets those bits. bits 28:9 and 6:0 are read only.<br />
<br />
The MEMCSR registers can be read with test 9c.<br />
<br />
===Error Syndrome Field===<br />
<br />
The error syndrome is particularly useful for troubleshooting memory errors as it can tell us exactly which bit had the error. A list of the syndromes and the corresponding bit error is given below.<br />
<br />
{| border=1 style="text-align:center"<br />
| syndrome || bit position or error description<br />
|-<br />
| 0000000 || no error<br />
|-<br />
| 0000001 || 32<br />
|-<br />
| 0000010 || 33<br />
|-<br />
| 0000100 || 34<br />
|-<br />
| 0000111 || result of incorrect check bits written on CDAL parity error<br />
|-<br />
| 0001000 || 35<br />
|-<br />
| 0010000 || 36<br />
|-<br />
| 0011001 || 7<br />
|-<br />
| 0011010 || 2<br />
|-<br />
| 0011100 || 1<br />
|-<br />
| 0011111 || 4<br />
|-<br />
| 0100000 || 37<br />
|-<br />
| 0101001 || 15<br />
|-<br />
| 0101010 || 10<br />
|-<br />
| 0101100 || 9<br />
|-<br />
| 0101111 || 12<br />
|-<br />
| 0110001 || 23<br />
|-<br />
| 0110010 || 18<br />
|-<br />
| 0110100 || 17<br />
|-<br />
| 0110111 || 20<br />
|-<br />
| 0111000 || 24<br />
|-<br />
| 0111011 || 29<br />
|-<br />
| 0111101 || 30<br />
|-<br />
| 0111110 || 27<br />
|-<br />
| 1000000 || 38<br />
|-<br />
| 1011000 || 0<br />
|-<br />
| 1011011 || 5<br />
|-<br />
| 1011101 || 6<br />
|-<br />
| 1011110 || 3<br />
|-<br />
| 1101000 || 8<br />
|-<br />
| 1101011 || 13<br />
|-<br />
| 1101101 || 14<br />
|-<br />
| 1101110 || 11<br />
|-<br />
| 1110000 || 16<br />
|-<br />
| 1110011 || 21<br />
|-<br />
| 1110101 || 22<br />
|-<br />
| 1110110 || 19<br />
|-<br />
| 1111001 || 31<br />
|-<br />
| 1111010 || 26<br />
|-<br />
| 1111100 || 25<br />
|-<br />
| 1111111 || 28<br />
|-<br />
| other || multibit error<br />
|}<br />
<br />
==Troubleshooting==<br />
<br />
We now have all of the information necessary to narrow down which bits in which address regions are bad. However, that doesn't do any good for repair unless we also know which physical DRAMs that bit and region correspond to.<br />
<br />
===MS650-AA===<br />
<br />
Shown below is a diagram of the MS650-AA RAM card, broken up into 11 columns and 37 rows. Each spot in this grid contains up to 1 DRAM, but some locations contain other circuitry instead.<br />
<br />
<nowiki><br />
<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
--------------------------------------------------------------------------------<br />
01 | ooooooooooooooooooooooooo |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 01<br />
| --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
08 | --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 08<br />
|-------------------------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
09 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 09<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
16 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 16<br />
17 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 17<br />
18 |DDDDDDD|TTTTTTT TTTTTTTTT TTTTTTTT |DDDDDDDDDDDDD|TTTTTTTT TTTTTTTTT TTTTTTTT | 18<br />
19 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 19<br />
20 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 20<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
32 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 32<br />
33 |DDDDDDD-----------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 33<br />
36 |DDDDDDD| PPPPPPP TTTTT TTTTT |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 35<br />
37 |-------- TTTTTTT TTTTTTT --------DDDDDDDDDDDDDD-------DDDDDDDDDDDDDD| 37<br />
| -------------- --------------| <br />
| ___- - ___- |<br />
| | | || | | |<br />
-------------------- ----------------------------------------------------------<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
<br />
-----------------------------------------------<br />
| D DRAMS |<br />
| T TTL IC |<br />
| B some kind of DEC custom fast data buffer? |<br />
| P PAL16L8 |<br />
| o data connector |<br />
| | border |<br />
| - border |<br />
-----------------------------------------------<br />
<br />
</nowiki><br />
<br />
The MS650-AA RAM card uses two RAS lines. During normal initialization of the VAX, the rank connected to RAS0 will be first in memory, followed by the rank connected to RAS1. Presumably, the MS650-BA card would have 4 ranks.<br />
<br />
RAS0 - first 4MB<br />
RAS1 - second 4MB<br />
<br />
Based on the bit with the error, as well as the memory region where the error occurred, the specific DRAM with the failure can be found and replaced.<br />
<br />
Below is a list of the DRAMs sorted by memory region and bit, showing the grid location of the DRAM IC.<br />
<br />
By using the built in tests, along with MEMCSR16, and perhaps some manual DEPOSIT and EXAMINE testing, the bad DRAM should be possible to locate and then, using this table, the DRAM can be replaced.<br />
<br />
{| border=1 style="text-align:center"<br />
| DRAM || Address || data bit<br />
|-<br />
| A12 || 0XXXXX || MD00<br />
|-<br />
| A11 || 1XXXXX || MD00<br />
|-<br />
| A10 || 2XXXXX || MD00<br />
|-<br />
| A09 || 3XXXXX || MD00<br />
|-<br />
| A16 || 4XXXXX || MD00<br />
|-<br />
| A15 || 5XXXXX || MD00<br />
|-<br />
| A14 || 6XXXXX || MD00<br />
|-<br />
| A13 || 7XXXXX || MD00<br />
|-<br />
| A24 || 0XXXXX || MD01<br />
|-<br />
| A23 || 1XXXXX || MD01<br />
|-<br />
| A22 || 2XXXXX || MD01<br />
|-<br />
| A21 || 3XXXXX || MD01<br />
|-<br />
| A20 || 4XXXXX || MD01<br />
|-<br />
| A19 || 5XXXXX || MD01<br />
|-<br />
| A18 || 6XXXXX || MD01<br />
|-<br />
| A17 || 7XXXXX || MD01<br />
|-<br />
| A32 || 0XXXXX || MD02<br />
|-<br />
| A31 || 1XXXXX || MD02<br />
|-<br />
| A30 || 2XXXXX || MD02<br />
|-<br />
| A29 || 3XXXXX || MD02<br />
|-<br />
| A28 || 4XXXXX || MD02<br />
|-<br />
| A27 || 5XXXXX || MD02<br />
|-<br />
| A26 || 6XXXXX || MD02<br />
|-<br />
| A25 || 7XXXXX || MD02<br />
|-<br />
| B12 || 0XXXXX || MD03<br />
|-<br />
| B11 || 1XXXXX || MD03<br />
|-<br />
| B10 || 2XXXXX || MD03<br />
|-<br />
| B09 || 3XXXXX || MD03<br />
|-<br />
| A36 || 4XXXXX || MD03<br />
|-<br />
| A35 || 5XXXXX || MD03<br />
|-<br />
| A34 || 6XXXXX || MD03<br />
|-<br />
| A33 || 7XXXXX || MD03<br />
|-<br />
| B24 || 0XXXXX || MD04<br />
|-<br />
| B23 || 1XXXXX || MD04<br />
|-<br />
| B22 || 2XXXXX || MD04<br />
|-<br />
| B21 || 3XXXXX || MD04<br />
|-<br />
| B16 || 4XXXXX || MD04<br />
|-<br />
| B15 || 5XXXXX || MD04<br />
|-<br />
| B14 || 6XXXXX || MD04<br />
|-<br />
| B13 || 7XXXXX || MD04<br />
|-<br />
| B32 || 0XXXXX || MD05<br />
|-<br />
| B31 || 1XXXXX || MD05<br />
|-<br />
| B30 || 2XXXXX || MD05<br />
|-<br />
| B29 || 3XXXXX || MD05<br />
|-<br />
| B28 || 4XXXXX || MD05<br />
|-<br />
| B27 || 5XXXXX || MD05<br />
|-<br />
| B26 || 6XXXXX || MD05<br />
|-<br />
| B25 || 7XXXXX || MD05<br />
|-<br />
| C12 || 0XXXXX || MD06<br />
|-<br />
| C11 || 1XXXXX || MD06<br />
|-<br />
| C10 || 2XXXXX || MD06<br />
|-<br />
| C09 || 3XXXXX || MD06<br />
|-<br />
| C16 || 4XXXXX || MD06<br />
|-<br />
| C15 || 5XXXXX || MD06<br />
|-<br />
| C14 || 6XXXXX || MD06<br />
|-<br />
| C13 || 7XXXXX || MD06<br />
|-<br />
| C24 || 0XXXXX || MD07<br />
|-<br />
| C23 || 1XXXXX || MD07<br />
|-<br />
| C22 || 2XXXXX || MD07<br />
|-<br />
| C21 || 3XXXXX || MD07<br />
|-<br />
| E20 || 4XXXXX || MD07<br />
|-<br />
| D20 || 5XXXXX || MD07<br />
|-<br />
| C20 || 6XXXXX || MD07<br />
|-<br />
| B20 || 7XXXXX || MD07<br />
|-<br />
| C32 || 0XXXXX || MD08<br />
|-<br />
| C31 || 1XXXXX || MD08<br />
|-<br />
| C30 || 2XXXXX || MD08<br />
|-<br />
| C29 || 3XXXXX || MD08<br />
|-<br />
| C28 || 4XXXXX || MD08<br />
|-<br />
| C27 || 5XXXXX || MD08<br />
|-<br />
| C26 || 6XXXXX || MD08<br />
|-<br />
| C25 || 7XXXXX || MD08<br />
|-<br />
| D32 || 0XXXXX || MD09<br />
|-<br />
| D31 || 1XXXXX || MD09<br />
|-<br />
| D30 || 2XXXXX || MD09<br />
|-<br />
| D29 || 3XXXXX || MD09<br />
|-<br />
| D28 || 4XXXXX || MD09<br />
|-<br />
| D27 || 5XXXXX || MD09<br />
|-<br />
| D26 || 6XXXXX || MD09<br />
|-<br />
| D25 || 7XXXXX || MD09<br />
|-<br />
| D24 || 0XXXXX || MD10<br />
|-<br />
| D23 || 1XXXXX || MD10<br />
|-<br />
| D22 || 2XXXXX || MD10<br />
|-<br />
| D21 || 3XXXXX || MD10<br />
|-<br />
| D16 || 4XXXXX || MD10<br />
|-<br />
| D15 || 5XXXXX || MD10<br />
|-<br />
| D14 || 6XXXXX || MD10<br />
|-<br />
| D13 || 7XXXXX || MD10<br />
|-<br />
| D12 || 0XXXXX || MD11<br />
|-<br />
| D11 || 1XXXXX || MD11<br />
|-<br />
| D10 || 2XXXXX || MD11<br />
|-<br />
| D09 || 3XXXXX || MD11<br />
|-<br />
| E16 || 4XXXXX || MD11<br />
|-<br />
| E15 || 5XXXXX || MD11<br />
|-<br />
| E14 || 6XXXXX || MD11<br />
|-<br />
| E13 || 7XXXXX || MD11<br />
|-<br />
| E12 || 0XXXXX || MD12<br />
|-<br />
| E11 || 1XXXXX || MD12<br />
|-<br />
| E10 || 2XXXXX || MD12<br />
|-<br />
| E09 || 3XXXXX || MD12<br />
|-<br />
| E28 || 4XXXXX || MD12<br />
|-<br />
| E27 || 5XXXXX || MD12<br />
|-<br />
| E26 || 6XXXXX || MD12<br />
|-<br />
| E25 || 7XXXXX || MD12<br />
|-<br />
| E24 || 0XXXXX || MD13<br />
|-<br />
| E23 || 1XXXXX || MD13<br />
|-<br />
| E22 || 2XXXXX || MD13<br />
|-<br />
| E21 || 3XXXXX || MD13<br />
|-<br />
| F16 || 4XXXXX || MD13<br />
|-<br />
| F15 || 5XXXXX || MD13<br />
|-<br />
| F14 || 6XXXXX || MD13<br />
|-<br />
| F13 || 7XXXXX || MD13<br />
|-<br />
| E32 || 0XXXXX || MD14<br />
|-<br />
| E31 || 1XXXXX || MD14<br />
|-<br />
| E30 || 2XXXXX || MD14<br />
|-<br />
| E29 || 3XXXXX || MD14<br />
|-<br />
| F20 || 4XXXXX || MD14<br />
|-<br />
| F19 || 5XXXXX || MD14<br />
|-<br />
| F18 || 6XXXXX || MD14<br />
|-<br />
| F17 || 7XXXXX || MD14<br />
|-<br />
| F32 || 0XXXXX || MD15<br />
|-<br />
| F31 || 1XXXXX || MD15<br />
|-<br />
| F30 || 2XXXXX || MD15<br />
|-<br />
| F29 || 3XXXXX || MD15<br />
|-<br />
| F28 || 4XXXXX || MD15<br />
|-<br />
| F27 || 5XXXXX || MD15<br />
|-<br />
| F26 || 6XXXXX || MD15<br />
|-<br />
| F25 || 7XXXXX || MD15<br />
|-<br />
| F24 || 0XXXXX || MD16<br />
|-<br />
| F23 || 1XXXXX || MD16<br />
|-<br />
| F22 || 2XXXXX || MD16<br />
|-<br />
| F21 || 3XXXXX || MD16<br />
|-<br />
| F36 || 4XXXXX || MD16<br />
|-<br />
| F35 || 5XXXXX || MD16<br />
|-<br />
| F34 || 6XXXXX || MD16<br />
|-<br />
| F33 || 7XXXXX || MD16<br />
|-<br />
| G32 || 0XXXXX || MD17<br />
|-<br />
| G31 || 1XXXXX || MD17<br />
|-<br />
| G30 || 2XXXXX || MD17<br />
|-<br />
| G29 || 3XXXXX || MD17<br />
|-<br />
| G36 || 4XXXXX || MD17<br />
|-<br />
| G35 || 5XXXXX || MD17<br />
|-<br />
| G34 || 6XXXXX || MD17<br />
|-<br />
| G33 || 7XXXXX || MD17<br />
|-<br />
| G24 || 0XXXXX || MD18<br />
|-<br />
| G23 || 1XXXXX || MD18<br />
|-<br />
| G22 || 2XXXXX || MD18<br />
|-<br />
| G21 || 3XXXXX || MD18<br />
|-<br />
| G28 || 4XXXXX || MD18<br />
|-<br />
| G27 || 5XXXXX || MD18<br />
|-<br />
| G26 || 6XXXXX || MD18<br />
|-<br />
| G25 || 7XXXXX || MD18<br />
|-<br />
| H32 || 0XXXXX || MD19<br />
|-<br />
| H31 || 1XXXXX || MD19<br />
|-<br />
| H30 || 2XXXXX || MD19<br />
|-<br />
| H29 || 3XXXXX || MD19<br />
|-<br />
| G20 || 4XXXXX || MD19<br />
|-<br />
| G19 || 5XXXXX || MD19<br />
|-<br />
| G18 || 6XXXXX || MD19<br />
|-<br />
| G17 || 7XXXXX || MD19<br />
|-<br />
| H24 || 0XXXXX || MD20<br />
|-<br />
| H23 || 1XXXXX || MD20<br />
|-<br />
| H22 || 2XXXXX || MD20<br />
|-<br />
| H21 || 3XXXXX || MD20<br />
|-<br />
| K37 || 4XXXXX || MD20<br />
|-<br />
| J37 || 5XXXXX || MD20<br />
|-<br />
| H37 || 6XXXXX || MD20<br />
|-<br />
| G37 || 7XXXXX || MD20<br />
|-<br />
| I32 || 0XXXXX || MD21<br />
|-<br />
| I31 || 1XXXXX || MD21<br />
|-<br />
| I30 || 2XXXXX || MD21<br />
|-<br />
| I29 || 3XXXXX || MD21<br />
|-<br />
| H36 || 4XXXXX || MD21<br />
|-<br />
| H35 || 5XXXXX || MD21<br />
|-<br />
| H34 || 6XXXXX || MD21<br />
|-<br />
| H33 || 7XXXXX || MD21<br />
|-<br />
| I24 || 0XXXXX || MD22<br />
|-<br />
| I23 || 1XXXXX || MD22<br />
|-<br />
| I22 || 2XXXXX || MD22<br />
|-<br />
| I21 || 3XXXXX || MD22<br />
|-<br />
| H28 || 4XXXXX || MD22<br />
|-<br />
| H27 || 5XXXXX || MD22<br />
|-<br />
| H26 || 6XXXXX || MD22<br />
|-<br />
| H25 || 7XXXXX || MD22<br />
|-<br />
| J32 || 0XXXXX || MD23<br />
|-<br />
| J31 || 1XXXXX || MD23<br />
|-<br />
| J30 || 2XXXXX || MD23<br />
|-<br />
| J29 || 3XXXXX || MD23<br />
|-<br />
| I36 || 4XXXXX || MD23<br />
|-<br />
| I35 || 5XXXXX || MD23<br />
|-<br />
| I34 || 6XXXXX || MD23<br />
|-<br />
| I33 || 7XXXXX || MD23<br />
|-<br />
| J24 || 0XXXXX || MD24<br />
|-<br />
| J23 || 1XXXXX || MD24<br />
|-<br />
| J22 || 2XXXXX || MD24<br />
|-<br />
| J21 || 3XXXXX || MD24<br />
|-<br />
| I28 || 4XXXXX || MD24<br />
|-<br />
| I27 || 5XXXXX || MD24<br />
|-<br />
| I26 || 6XXXXX || MD24<br />
|-<br />
| I25 || 7XXXXX || MD24<br />
|-<br />
| K32 || 0XXXXX || MD25<br />
|-<br />
| K31 || 1XXXXX || MD25<br />
|-<br />
| K30 || 2XXXXX || MD25<br />
|-<br />
| K29 || 3XXXXX || MD25<br />
|-<br />
| J36 || 4XXXXX || MD25<br />
|-<br />
| J35 || 5XXXXX || MD25<br />
|-<br />
| J34 || 6XXXXX || MD25<br />
|-<br />
| J33 || 7XXXXX || MD25<br />
|-<br />
| K24 || 0XXXXX || MD26<br />
|-<br />
| K23 || 1XXXXX || MD26<br />
|-<br />
| K22 || 2XXXXX || MD26<br />
|-<br />
| K21 || 3XXXXX || MD26<br />
|-<br />
| J28 || 4XXXXX || MD26<br />
|-<br />
| J27 || 5XXXXX || MD26<br />
|-<br />
| J26 || 6XXXXX || MD26<br />
|-<br />
| J25 || 7XXXXX || MD26<br />
|-<br />
| K20 || 0XXXXX || MD27<br />
|-<br />
| J20 || 1XXXXX || MD27<br />
|-<br />
| I20 || 2XXXXX || MD27<br />
|-<br />
| H20 || 3XXXXX || MD27<br />
|-<br />
| K36 || 4XXXXX || MD27<br />
|-<br />
| K35 || 5XXXXX || MD27<br />
|-<br />
| K34 || 6XXXXX || MD27<br />
|-<br />
| K33 || 7XXXXX || MD27<br />
|-<br />
| F12 || 0XXXXX || MD28<br />
|-<br />
| F11 || 1XXXXX || MD28<br />
|-<br />
| F10 || 2XXXXX || MD28<br />
|-<br />
| F09 || 3XXXXX || MD28<br />
|-<br />
| K28 || 4XXXXX || MD28<br />
|-<br />
| K26 || 6XXXXX || MD28<br />
|-<br />
| K27 || 5XXXXX || MD28<br />
|-<br />
| K25 || 7XXXXX || MD28<br />
|-<br />
| G12 || 0XXXXX || MD29<br />
|-<br />
| G11 || 1XXXXX || MD29<br />
|-<br />
| G10 || 2XXXXX || MD29<br />
|-<br />
| G09 || 3XXXXX || MD29<br />
|-<br />
| G16 || 4XXXXX || MD29<br />
|-<br />
| G15 || 5XXXXX || MD29<br />
|-<br />
| G14 || 6XXXXX || MD29<br />
|-<br />
| G13 || 7XXXXX || MD29<br />
|-<br />
| G04 || 0XXXXX || MD30<br />
|-<br />
| G03 || 1XXXXX || MD30<br />
|-<br />
| G02 || 2XXXXX || MD30<br />
|-<br />
| G01 || 3XXXXX || MD30<br />
|-<br />
| G08 || 4XXXXX || MD30<br />
|-<br />
| G07 || 5XXXXX || MD30<br />
|-<br />
| G06 || 6XXXXX || MD30<br />
|-<br />
| G05 || 7XXXXX || MD30<br />
|-<br />
| H04 || 0XXXXX || MD31<br />
|-<br />
| H03 || 1XXXXX || MD31<br />
|-<br />
| H02 || 2XXXXX || MD31<br />
|-<br />
| H01 || 3XXXXX || MD31<br />
|-<br />
| H08 || 4XXXXX || MD31<br />
|-<br />
| H07 || 5XXXXX || MD31<br />
|-<br />
| H06 || 6XXXXX || MD31<br />
|-<br />
| H05 || 7XXXXX || MD31<br />
|-<br />
| H12 || 0XXXXX || MD32<br />
|-<br />
| H11 || 1XXXXX || MD32<br />
|-<br />
| H10 || 2XXXXX || MD32<br />
|-<br />
| H09 || 3XXXXX || MD32<br />
|-<br />
| H16 || 4XXXXX || MD32<br />
|-<br />
| H15 || 5XXXXX || MD32<br />
|-<br />
| H14 || 6XXXXX || MD32<br />
|-<br />
| H13 || 7XXXXX || MD32<br />
|-<br />
| I04 || 0XXXXX || MD33<br />
|-<br />
| I03 || 1XXXXX || MD33<br />
|-<br />
| I02 || 2XXXXX || MD33<br />
|-<br />
| I01 || 3XXXXX || MD33<br />
|-<br />
| I08 || 4XXXXX || MD33<br />
|-<br />
| I07 || 5XXXXX || MD33<br />
|-<br />
| I06 || 6XXXXX || MD33<br />
|-<br />
| I05 || 7XXXXX || MD33<br />
|-<br />
| I12 || 0XXXXX || MD34<br />
|-<br />
| I11 || 1XXXXX || MD34<br />
|-<br />
| I10 || 2XXXXX || MD34<br />
|-<br />
| I09 || 3XXXXX || MD34<br />
|-<br />
| I16 || 4XXXXX || MD34<br />
|-<br />
| I15 || 5XXXXX || MD34<br />
|-<br />
| I14 || 6XXXXX || MD34<br />
|-<br />
| I13 || 7XXXXX || MD34<br />
|-<br />
| J04 || 0XXXXX || MD35<br />
|-<br />
| J03 || 1XXXXX || MD35<br />
|-<br />
| J02 || 2XXXXX || MD35<br />
|-<br />
| J01 || 3XXXXX || MD35<br />
|-<br />
| J08 || 4XXXXX || MD35<br />
|-<br />
| J07 || 5XXXXX || MD35<br />
|-<br />
| J06 || 6XXXXX || MD35<br />
|-<br />
| J05 || 7XXXXX || MD35<br />
|-<br />
| J12 || 0XXXXX || MD36<br />
|-<br />
| J11 || 1XXXXX || MD36<br />
|-<br />
| J10 || 2XXXXX || MD36<br />
|-<br />
| J09 || 3XXXXX || MD36<br />
|-<br />
| J16 || 4XXXXX || MD36<br />
|-<br />
| J15 || 5XXXXX || MD36<br />
|-<br />
| J14 || 6XXXXX || MD36<br />
|-<br />
| J13 || 7XXXXX || MD36<br />
|-<br />
| K04 || 0XXXXX || MD37<br />
|-<br />
| K03 || 1XXXXX || MD37<br />
|-<br />
| K02 || 2XXXXX || MD37<br />
|-<br />
| K01 || 3XXXXX || MD37<br />
|-<br />
| K08 || 4XXXXX || MD37<br />
|-<br />
| K07 || 5XXXXX || MD37<br />
|-<br />
| K06 || 6XXXXX || MD37<br />
|-<br />
| K05 || 7XXXXX || MD37<br />
|-<br />
| K12 || 0XXXXX || MD38<br />
|-<br />
| K11 || 1XXXXX || MD38<br />
|-<br />
| K10 || 2XXXXX || MD38<br />
|-<br />
| K09 || 3XXXXX || MD38<br />
|-<br />
| K16 || 4XXXXX || MD38<br />
|-<br />
| K15 || 5XXXXX || MD38<br />
|-<br />
| K14 || 6XXXXX || MD38<br />
|-<br />
| K13 || 7XXXXX || MD38<br />
|}<br />
<br />
===MS650-BA===<br />
<br />
Because I did not have an MS650-BA to test, I do not have as much information on this module as on the MS650-AA. Presumably, the MS650-BA has 4 ranks of 4MB in 1MBxX DRAMs, meaning there is no need to have 4 banks in each rank like the 256kx1 DRAMs on the MS650-AA.<br />
<br />
==References==<br />
<br />
<div id="KA650-print-set">[1] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="KA650-technical-manual">[2] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div></div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_Main_Memory_System&diff=21869
KA650 Main Memory System
2019-11-24T15:30:34Z
<p>Jzatarski: </p>
<hr />
<div>This page contains notes on troubleshooting, repair, and theory of operation of the DEC KA650/MS650 memory subsystem.<br />
<br />
==Overview==<br />
<br />
The MS650-AA and MS650-BA memory module are intended to be used with the DEC KA650 VAX CPU, as the name might suggest. These quad width cards contain 8MB and 16MB of RAM for the VAX, respectively, complete with ECC.<br />
<br />
==Theory of Operation==<br />
<br />
===Memory Controller General Architecture and Organization===<br />
<br />
====Memory Control Signals Provided by the CMCTL====<br />
The CMCTL IC is the DRAM controller for the KA650 CPU. It has 10 address line outputs, 39 memory data I/O lines (MD), 4 CAS outputs, 4 RAS outputs, a WE pin, and an SE pin. Also available to the RAM card are the inverse of the 20th and 21st address lines (XA20 & XA21), which are used as bank selection when using 256kxX DRAMs. The data lines are provided to the RAM cards through a 50 conductor ribbon cable, while the rest of the control lines are provided through the CD interconnect on the backplane.<br />
<br />
The 10 address lines carry the row address on the rising edge of a RAS line, followed by the column address on the rising edge of a CAS line.<br />
<br />
The 39 data I/O lines carry the 32 data and 7 ECC bits for the RAM.<br />
<br />
The 4 CAS (Column Address Strobe) lines allow strobing the column address on up to 4 separate memory modules.<br />
<br />
The 4 RAS (Row Address Strobe) lines allow selection of up to 4 banks on a single memory module.<br />
<br />
The WE (Write Enable) pin indicates that the CMCTL is writing to memory, rather than reading.<br />
<br />
The SE (Strobe Enable?) pin seems to indicate that the CMCTL is refreshing memory. This is necessary for the 8MB card to correctly strobe the RAS lines of each rank during a refresh cycle, due to the extra RAS gating circuitry necessary on cards with 256kxX DRAMs.<br />
<br />
The XA20 and XA21 lines are the inverse of the latched address lines from the CDAL bus.<br />
<br />
Note that many of the above control lines are inverse logic from what is normally used to drive DRAMs; in particular, CAS, RAS, and WE lines are inverted from the normal JEDEC DRAM convention of active low /RAS, /CAS, and /WE.<br />
<br />
====Memory Ranks & Banks====<br />
<br />
Due to the 10 bit address bus using conventional multiplexed row and column DRAM addressing, an effective 20 bit address is formed. This allows the CMCTL to address up to 1MWord per rank.<br />
<br />
By strobing different pairings of RAS and CAS (RAS0+CAS0 is one rank, while RAS0+CAS1 is another rank, while RAS1+CAS0 is yet another rank), the CMCTL supports up to 16 ranks of RAM, each 1Mx39. Each rank is thus 4MB of memory once ECC overhead is accounted for. This puts a 64MB cap on the maximum amount of memory the CMCTL can address (16 ranks of 4MB).<br />
<br />
When 256kxX DRAMs are used in place of 1MxX DRAMs, each 1Mx39 rank is further divided into 4 banks of 256kx39. Each bank is selected by XA20 and XA21, which are provided to the RAM cards via the CD interconnect. These address bits appear to only be valid on the rising edge of RAS. Before CAS has strobed, the bits have generally already changed since these are derived from the CDAL bus of the VAX CPU. These bits are used to gate the /RAS lines to the DRAMs ensuring that only the selected bank is addressed. The /CAS line for the card is not affected.<br />
<br />
The MS650-AA card contains 312 256kx1 ZIP DRAMs, organized into 8 banks of 256kx39. As previously mentioned, one memory rank as addressed by the CMCTL memory controller consists of 4 banks, making up a total of 1MWord of memory per rank. Each DRAM on the card corresponds to one bit of the 39 bit word within a 1MB address region of the VAX.<br />
<br />
===Addressing===<br />
<br />
The CMCTL appears to convert 32 bit VAX addresses into DRAM addressing as follows:<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
| A21 || A20 || A19 || A18 || A17 || A16 || A15 || A14 || A13 || A12 || A11 || A10 || A09 || A08 || A07 || A06 || A05 || A04 || A03 || A02<br />
|-<br />
| width=2.5% | R09 <br />
| width=2.5% | <br />
| width=2.5% | R08<br />
| width=2.5% | R07<br />
| width=2.5% | R06<br />
| width=2.5% | R05<br />
| width=2.5% | R04<br />
| width=2.5% | R03<br />
| width=2.5% | R02<br />
| width=2.5% | R01<br />
| width=2.5% | R00<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
|-<br />
| width=2.5% | <br />
| width=2.5% | C09<br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | C08<br />
| width=2.5% | C07<br />
| width=2.5% | C06<br />
| width=2.5% | C05<br />
| width=2.5% | C04<br />
| width=2.5% | C03<br />
| width=2.5% | C02<br />
| width=2.5% | C01<br />
| width=2.5% | C00<br />
|}<br />
<br />
Axx are VAX address lines<br />
Rxx are DRAM row address bits<br />
Cxx are DRAM column address bits<br />
<br />
This addressing scheme is used to ensure that 256kxX DRAMs (which use only 9 bit row and column addresses) are still supported for use with the CMCTL.<br />
<br />
It is, of course, still up to the CMCTL to determine which ranks are selected by the upper bits of a given physical address. This is determined by the MEMCSR0-15 registers, which seem to specify whether or not a bank is present, as well as what base address it resides at. It may perform other functions, but it does not seem to be documented in available documentation.<br />
<br />
===CAS and RAS Signals===<br />
<br />
Each 16MB or 8MB memory card for the KA650 uses one CAS line in its entirety. This is why a maximum of 4 cards may be used in a KA650 system. Each RAM card uses the first CAS line, and passes the remaining lines on to the next card, shifted down one bit. So for example, the first card gets CAS0 CAS1 CAS2 CAS3, in that order. It uses CAS0 and passes CAS1 CAS2 and CAS3 on to the next card, in that order. The next card uses CAS1 and passes on CAS2 and CAS3. This repeats until 4 cards have used up all of the available CAS lines.<br />
<br />
The CAS line is not gated in any way on the MS650-AA. The CAS line is simply buffered, inverted to match the polarity of the DRAMs, and distributed to all DRAMs on the card (likely with some hierarchical buffering methodology).<br />
<br />
===Refresh===<br />
<br />
DRAMs are built using one tiny MOS capacitor for each bit. These capacitors leak slightly and need to be periodically refreshed. DRAM rows are refreshed by simply addressing a row. Any row access refreshes that row, no column needs to be strobed for a refresh.<br />
<br />
As such, during refresh cycles, the CMCTL places a row address to be refreshed on the address bus, asserts SE, and asserts all RAS lines for several clock cycles. The purpose of the SE signal is so that RAM cards with 256kxX DRAMs do not gate any of the /RAS lines going to the DRAMs, or else only whatever DRAM bank is (randomly) addressed by XA20 and XA21 would be refreshed.<br />
<br />
===ECC===<br />
<br />
The ECC supported by the CMCTL, according to the KA650 technical manual, has the ability to detect and correct single data bit errors, detect single ECC bit errors, and detect double-bit data errors.<br />
<br />
ECC is generally based on producing parity bits of various collections of data bits. Since parity is based around the simple XOR, it is a linear operation in a manner of speaking. Luckily this means we can determine the ECC equations based on a number of sample data patterns and the respective ECC bits, such as the ECC produced for 0 data, and data with only one bit in the word set. By comparing the ECC for each test pattern to that of 0, we can determine which ECC bits each bit in the data word affects.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| bit || colspan=8 | data || ECC<br />
|-<br />
| || MSB || colspan = 6 | || LSB ||<br />
|-<br />
| - || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0111100<br />
|-<br />
| 0 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 1100100<br />
|-<br />
| 1 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0100000<br />
|-<br />
| 2 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0100110<br />
|-<br />
| 3 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 1100010<br />
|-<br />
| 4 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0100011<br />
|-<br />
| 5 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 1100111<br />
|-<br />
| 6 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 1100001<br />
|-<br />
| 7 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0100101<br />
|-<br />
| 8 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 1010100<br />
|-<br />
| 9 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0010000<br />
|-<br />
| 10 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0010110<br />
|-<br />
| 11 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 1010010<br />
|-<br />
| 12 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0010011<br />
|-<br />
| 13 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 1010111<br />
|-<br />
| 14 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 1010001<br />
|-<br />
| 15 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0010101<br />
|-<br />
| 16 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 1001100<br />
|-<br />
| 17 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0001000<br />
|-<br />
| 18 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0001110<br />
|-<br />
| 19 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 1001010<br />
|-<br />
| 20 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001011<br />
|-<br />
| 21 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001111<br />
|-<br />
| 22 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001001<br />
|-<br />
| 23 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001101<br />
|-<br />
| 24 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000100<br />
|-<br />
| 25 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000000<br />
|-<br />
| 26 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000110<br />
|-<br />
| 27 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000010<br />
|-<br />
| 28 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000011<br />
|-<br />
| 29 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000111<br />
|-<br />
| 30 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000001<br />
|-<br />
| 31 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000101<br />
|}<br />
<br />
<br />
The results of this are depicted below. The basic result is that toggling one of the bits that belongs to the ECC bit group will result in that ECC bit toggling as well.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| ECC bit || colspan=3 | MSB || colspan=26 | || colspan=3 | LSB<br />
|-<br />
|MD32<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|-<br />
|MD33<br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
|-<br />
|MD34<br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
|-<br />
|MD35<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD36<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD37<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|-<br />
|MD38<br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
|}<br />
<br />
An interesting and potentially useful point to note is that flipping bit 28 happens to flip all of the ECC bits together. Another interesting point is that inverting the entire data word produces the same ECC.<br />
<br />
From this information, we can derive some data patterns that produce useful ECC combinations, such as ECC of all zeroes, all ones, only one bit set, and only one bit clear. Looking at the table above, we got lucky and examples of many of these combinations were found by chance. In particular, we happened upon data combinations that produced every possibility of 1 ECC bit set. These, combined with the fact that we can toggle bit 28 to get the inverse ECC bits, gives us a set of data patterns which produce ECC with only one bit clear. From here, we only need to derive a combination which produces all-zero ECC, and from that, derive all-one ECC.<br />
<br />
Starting with the ECC for bit 31 set, we can toggle single bits at a time until we find a combination that produces the ECC we want.<br />
<nowiki><br />
31 1000 0000 0000 0000 0000 0000 0000 0000 1000101<br />
1000 0000 0000 0000 0000 0000 0000 0001 0011101<br />
1000 0000 0000 0000 0000 0010 0000 0001 0110001<br />
1000 0000 1000 0000 0000 0010 0000 0001 0000000 <--<br />
1001 0000 1000 0000 0000 0010 0000 0001 1111111 <--<br />
</nowiki><br />
<br />
The summary of these useful ECC combinations is tabulated below (data in hex, ECC in binary)<br />
<br />
useful ECC combinations:<br />
<br />
{| border=1 style="text-align:center"<br />
| ECC (binary) || data (hex)<br />
|-<br />
| 0000000 || 80800201<br />
|-<br />
| 0000001 || 40000000<br />
|-<br />
| 0000010 || 08000000<br />
|-<br />
| 0000100 || 01000000<br />
|-<br />
| 0001000 || 00020000<br />
|-<br />
| 0010000 || 00000200<br />
|-<br />
| 0100000 || 00000002<br />
|-<br />
| 1000000 || 02000000<br />
|-<br />
| 1111111 || 90800201<br />
|-<br />
| 1111110 || 50000000<br />
|-<br />
| 1111101 || 18000000<br />
|-<br />
| 1111011 || 11000000<br />
|-<br />
| 1110111 || 10020000<br />
|-<br />
| 1101111 || 10000200<br />
|-<br />
| 1011111 || 10000002<br />
|-<br />
| 0111111 || 12000000<br />
|}<br />
<br />
===KA650 Memory Bus Cycles===<br />
<br />
[[File:MS650-AA-Longword-write-same-rank-bank-cycle.png|200px|thumb|left|Longword write cycle]]<br />
<br />
During a longword write cycle, the CMCTL first places the row address onto the memory address bus. Next, it asserts the RAS signal, causing the DRAMs to latch the row address. It then asserts the write enable signal and places the column address on the address bus, then asserts the CAS signal. Lastly, the data and ECC bits are placed on the bus, and some time later CAS deasserts, followed by RAS. On the MS650-AA RAM module, XA20 and XA21 are decoded to determine which bank is selected.<br />
<br />
[[File:MS650-AA-Longword-write-diff-rank-same-bank-cycle.png|200px|thumb|left|Longword write cycle to a different rank]]<br />
<br />
The CMCTL will assert only the RAS line for the rank which is selected based on the memory address the VAX CPU is accessing.<br />
<br />
[[File:MS650-AA-Longword-write-same-rank-diff-bank-cycle.png|200px|thumb|left|Longword write cycle to a different bank]]<br />
<br />
Likewise, the MS650-AA decoding circuitry will only allow the RAS line for the bank selected by XA20 and XA21 to be asserted, while ensuring the RAS lines for the other banks are gated off.<br />
<br />
[[File:MS650-AA-byte-write-cycle.png|200px|thumb|left|Byte write cycle]]<br />
<br />
During a byte write cycle, the CMCTL must first read the entire 39 bit word from the MS650, modify the byte which is being written, recalculate the ECC bits, and write the entire 39 bit word back to the MS650. Due to this, both a read and write cycle can be seen within a byte write cycle. Note that the RAS line stays asserted throughout both the read and write parts of the cycle.<br />
<br />
[[File:MS650-AA-qword-write-cycle.png|200px|thumb|left|Quadword write cycle]]<br />
<br />
During a quadword write cycle, two 39 bit words must be written to the MS650. Note that RAS actually cycles twice during this cycle.<br />
<br />
[[File:MS650-AA-read-cycle.png|200px|thumb|left|read cycle]]<br />
<br />
Any read cycle longword or smaller will appear to have the same cycle. Since the MS650 must be read or written as a full 39 bit cycle, there is no effective difference between a byte, word, or longword read. A quadword read, of course, involves reading two 39 bit words, and would thus result in a double cycle similar to the quadword write.<br />
<br />
[[File:MS650-AA-refresh-cycle.png|200px|thumb|left|refresh cycle]]<br />
<br />
Lastly, during a refresh cycle, the SE signal is asserted to force an MS650-AA to allow all banks to be refreshed at once. This would not be necessary for the 1MxX DRAMs on an MS650-BA. Similarly, the CMCTL asserts all RAS lines to load the row to be refreshed into every DRAM connected to the KA650. There is no assertion of CAS since there is no need to actually access a specific location, just to refresh a given row.<br />
<br />
==KA650 VAX Firmware Memory Tests==<br />
<br />
Many of the tests built in to the firmware of the VAX can be quite thorough, if used properly. The tests can be accessed by the TEST command in the monitor, abbreviated to 't'.<br />
<br />
The tests report diagnostic information upon failure, encoded simply as a number of values in registers and memory locations on the stack. With the proper documentation, these values could be decoded to determine the problem. Lacking that documentation, I was able to reverse engineer enough of one test that was failing to understand it's output.<br />
<br />
===TEST 48: MEM_Addr_shrts===<br />
<br />
This test is normally used to check for shorted address lines. It will fill the memory with a pattern first, then it will check each word in order to see if it is still the same pattern. After checking a word, it will check the CMCTL status register to ensure there were no detected errors. Then it will replace the word with another pattern (usually mostly an inverse of the first pattern).<br />
<br />
If any address line is shorted, when the test writes the second pattern, it will affect another location in memory. When that location is encountered, it will read as the wrong data thus showing the issue. However, the test is also capable of detecting stuck bits the way it is designed, and this test happened to find all DRAM errors in my case.<br />
<br />
The output when the test encounters an error looks like the following:<br />
<br />
<nowiki><br />
>>>t 48<br />
<br />
<br />
?48 2 08 FF 00 0002<br />
<br />
P1=00000000 P2=04000000 P3=00000004 P4=00031000 P5=AAAAAAAA<br />
P6=55555555 P7=00000043 P8=200C5875 P9=00000000 P10=2005311F<br />
r0=45555555 r1=000C5860 r2=45555555 r3=00000004 r4=0000006B<br />
r5=AAAAAAAA r6=20080140 r7=20080144 r8=00000000 ERF=80000000<br />
<br />
Normal operation not possible.<br />
<br />
>>><br />
</nowiki><br />
<br />
I figured out the meaning of some of these registers for this test. First of all, P10 indicates an address where presumably DEC personnel would check a source listing to find out the exact meaning of the rest of the values shown. The meanings of the registers I have found are only valid for this routine, located near 2005311F.<br />
<br />
{| border=1 style="text-align:center"<br />
| register || description<br />
|-<br />
| r0 || contents of memory at address being tested<br />
|-<br />
| r1 || address being tested<br />
|-<br />
| r2 || expected pattern from memory being tested<br />
|-<br />
| r5 || pattern to replace location with<br />
|-<br />
| r6 || address of CMCTL MEMCSR16 (a diagnostic register)<br />
|-<br />
| P8 || contents of MEMCSR16<br />
|}<br />
<br />
==MEMCSR16 Register==<br />
<br />
The MEMCSR16 register gives us information on what kind of memory failure<br />
occurred. The bit meanings are as follows, according to the KA650 technical manual:<br />
<br />
{| border=1 style="text-align:center"<br />
| bits || description<br />
|-<br />
| <31> || set if uncorrectable error occurred<br />
|-<br />
| <30> || set if multiple uncorrectable errors occurred<br />
|-<br />
| <29> || set if correctable error occurred<br />
|-<br />
| <28:9> || page address where error occurred (pages are 512 bytes)<br />
|-<br />
| <8> || set if error ocurred during DMA<br />
|-<br />
| <7> || set if CDAL bus parity error occurred<br />
|-<br />
| <6:0> || error syndrome: a unique combination is produced here for each possible single bit error<br />
|}<br />
<br />
writing 1s to bits 31, 30, 29, 8, or 7 of MEMCSR16 resets those bits. bits 28:9 and 6:0 are read only.<br />
<br />
The MEMCSR registers can be read with test 9c.<br />
<br />
===Error Syndrome Field===<br />
<br />
The error syndrome is particularly useful for troubleshooting memory errors as it can tell us exactly which bit had the error. A list of the syndromes and the corresponding bit error is given below.<br />
<br />
{| border=1 style="text-align:center"<br />
| syndrome || bit position or error description<br />
|-<br />
| 0000000 || no error<br />
|-<br />
| 0000001 || 32<br />
|-<br />
| 0000010 || 33<br />
|-<br />
| 0000100 || 34<br />
|-<br />
| 0000111 || result of incorrect check bits written on CDAL parity error<br />
|-<br />
| 0001000 || 35<br />
|-<br />
| 0010000 || 36<br />
|-<br />
| 0011001 || 7<br />
|-<br />
| 0011010 || 2<br />
|-<br />
| 0011100 || 1<br />
|-<br />
| 0011111 || 4<br />
|-<br />
| 0100000 || 37<br />
|-<br />
| 0101001 || 15<br />
|-<br />
| 0101010 || 10<br />
|-<br />
| 0101100 || 9<br />
|-<br />
| 0101111 || 12<br />
|-<br />
| 0110001 || 23<br />
|-<br />
| 0110010 || 18<br />
|-<br />
| 0110100 || 17<br />
|-<br />
| 0110111 || 20<br />
|-<br />
| 0111000 || 24<br />
|-<br />
| 0111011 || 29<br />
|-<br />
| 0111101 || 30<br />
|-<br />
| 0111110 || 27<br />
|-<br />
| 1000000 || 38<br />
|-<br />
| 1011000 || 0<br />
|-<br />
| 1011011 || 5<br />
|-<br />
| 1011101 || 6<br />
|-<br />
| 1011110 || 3<br />
|-<br />
| 1101000 || 8<br />
|-<br />
| 1101011 || 13<br />
|-<br />
| 1101101 || 14<br />
|-<br />
| 1101110 || 11<br />
|-<br />
| 1110000 || 16<br />
|-<br />
| 1110011 || 21<br />
|-<br />
| 1110101 || 22<br />
|-<br />
| 1110110 || 19<br />
|-<br />
| 1111001 || 31<br />
|-<br />
| 1111010 || 26<br />
|-<br />
| 1111100 || 25<br />
|-<br />
| 1111111 || 28<br />
|-<br />
| other || multibit error<br />
|}<br />
<br />
==Troubleshooting==<br />
<br />
We now have all of the information necessary to narrow down which bits in which address regions are bad. However, that doesn't do any good for repair unless we also know which physical DRAMs that bit and region correspond to.<br />
<br />
===MS650-AA===<br />
<br />
Shown below is a diagram of the MS650-AA RAM card, broken up into 11 columns and 37 rows. Each spot in this grid contains up to 1 DRAM, but some locations contain other circuitry instead.<br />
<br />
<nowiki><br />
<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
--------------------------------------------------------------------------------<br />
01 | ooooooooooooooooooooooooo |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 01<br />
| --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
08 | --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 08<br />
|-------------------------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
09 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 09<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
16 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 16<br />
17 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 17<br />
18 |DDDDDDD|TTTTTTT TTTTTTTTT TTTTTTTT |DDDDDDDDDDDDD|TTTTTTTT TTTTTTTTT TTTTTTTT | 18<br />
19 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 19<br />
20 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 20<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
32 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 32<br />
33 |DDDDDDD-----------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 33<br />
36 |DDDDDDD| PPPPPPP TTTTT TTTTT |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 35<br />
37 |-------- TTTTTTT TTTTTTT --------DDDDDDDDDDDDDD-------DDDDDDDDDDDDDD| 37<br />
| -------------- --------------| <br />
| ___- - ___- |<br />
| | | || | | |<br />
-------------------- ----------------------------------------------------------<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
<br />
-----------------------------------------------<br />
| D DRAMS |<br />
| T TTL IC |<br />
| B some kind of DEC custom fast data buffer? |<br />
| P PAL16L8 |<br />
| o data connector |<br />
| | border |<br />
| - border |<br />
-----------------------------------------------<br />
<br />
</nowiki><br />
<br />
The MS650-AA RAM card uses two RAS lines. During normal initialization of the VAX, the rank connected to RAS0 will be first in memory, followed by the rank connected to RAS1. Presumably, the MS650-BA card would have 4 ranks.<br />
<br />
RAS0 - first 4MB<br />
RAS1 - second 4MB<br />
<br />
Based on the bit with the error, as well as the memory region where the error occurred, the specific DRAM with the failure can be found and replaced.<br />
<br />
Below is a list of the DRAMs sorted by memory region and bit, showing the grid location of the DRAM IC.<br />
<br />
By using the built in tests, along with MEMCSR16, and perhaps some manual DEPOSIT and EXAMINE testing, the bad DRAM should be possible to locate and then, using this table, the DRAM can be replaced.<br />
<br />
{| border=1 style="text-align:center"<br />
| DRAM || Address || data bit<br />
|-<br />
| A12 || 0XXXXX || MD00<br />
|-<br />
| A11 || 1XXXXX || MD00<br />
|-<br />
| A10 || 2XXXXX || MD00<br />
|-<br />
| A09 || 3XXXXX || MD00<br />
|-<br />
| A16 || 4XXXXX || MD00<br />
|-<br />
| A15 || 5XXXXX || MD00<br />
|-<br />
| A14 || 6XXXXX || MD00<br />
|-<br />
| A13 || 7XXXXX || MD00<br />
|-<br />
| A24 || 0XXXXX || MD01<br />
|-<br />
| A23 || 1XXXXX || MD01<br />
|-<br />
| A22 || 2XXXXX || MD01<br />
|-<br />
| A21 || 3XXXXX || MD01<br />
|-<br />
| A20 || 4XXXXX || MD01<br />
|-<br />
| A19 || 5XXXXX || MD01<br />
|-<br />
| A18 || 6XXXXX || MD01<br />
|-<br />
| A17 || 7XXXXX || MD01<br />
|-<br />
| A32 || 0XXXXX || MD02<br />
|-<br />
| A31 || 1XXXXX || MD02<br />
|-<br />
| A30 || 2XXXXX || MD02<br />
|-<br />
| A29 || 3XXXXX || MD02<br />
|-<br />
| A28 || 4XXXXX || MD02<br />
|-<br />
| A27 || 5XXXXX || MD02<br />
|-<br />
| A26 || 6XXXXX || MD02<br />
|-<br />
| A25 || 7XXXXX || MD02<br />
|-<br />
| B12 || 0XXXXX || MD03<br />
|-<br />
| B11 || 1XXXXX || MD03<br />
|-<br />
| B10 || 2XXXXX || MD03<br />
|-<br />
| B09 || 3XXXXX || MD03<br />
|-<br />
| A36 || 4XXXXX || MD03<br />
|-<br />
| A35 || 5XXXXX || MD03<br />
|-<br />
| A34 || 6XXXXX || MD03<br />
|-<br />
| A33 || 7XXXXX || MD03<br />
|-<br />
| B24 || 0XXXXX || MD04<br />
|-<br />
| B23 || 1XXXXX || MD04<br />
|-<br />
| B22 || 2XXXXX || MD04<br />
|-<br />
| B21 || 3XXXXX || MD04<br />
|-<br />
| B16 || 4XXXXX || MD04<br />
|-<br />
| B15 || 5XXXXX || MD04<br />
|-<br />
| B14 || 6XXXXX || MD04<br />
|-<br />
| B13 || 7XXXXX || MD04<br />
|-<br />
| B32 || 0XXXXX || MD05<br />
|-<br />
| B31 || 1XXXXX || MD05<br />
|-<br />
| B30 || 2XXXXX || MD05<br />
|-<br />
| B29 || 3XXXXX || MD05<br />
|-<br />
| B28 || 4XXXXX || MD05<br />
|-<br />
| B27 || 5XXXXX || MD05<br />
|-<br />
| B26 || 6XXXXX || MD05<br />
|-<br />
| B25 || 7XXXXX || MD05<br />
|-<br />
| C12 || 0XXXXX || MD06<br />
|-<br />
| C11 || 1XXXXX || MD06<br />
|-<br />
| C10 || 2XXXXX || MD06<br />
|-<br />
| C09 || 3XXXXX || MD06<br />
|-<br />
| C16 || 4XXXXX || MD06<br />
|-<br />
| C15 || 5XXXXX || MD06<br />
|-<br />
| C14 || 6XXXXX || MD06<br />
|-<br />
| C13 || 7XXXXX || MD06<br />
|-<br />
| C24 || 0XXXXX || MD07<br />
|-<br />
| C23 || 1XXXXX || MD07<br />
|-<br />
| C22 || 2XXXXX || MD07<br />
|-<br />
| C21 || 3XXXXX || MD07<br />
|-<br />
| E20 || 4XXXXX || MD07<br />
|-<br />
| D20 || 5XXXXX || MD07<br />
|-<br />
| C20 || 6XXXXX || MD07<br />
|-<br />
| B20 || 7XXXXX || MD07<br />
|-<br />
| C32 || 0XXXXX || MD08<br />
|-<br />
| C31 || 1XXXXX || MD08<br />
|-<br />
| C30 || 2XXXXX || MD08<br />
|-<br />
| C29 || 3XXXXX || MD08<br />
|-<br />
| C28 || 4XXXXX || MD08<br />
|-<br />
| C27 || 5XXXXX || MD08<br />
|-<br />
| C26 || 6XXXXX || MD08<br />
|-<br />
| C25 || 7XXXXX || MD08<br />
|-<br />
| D32 || 0XXXXX || MD09<br />
|-<br />
| D31 || 1XXXXX || MD09<br />
|-<br />
| D30 || 2XXXXX || MD09<br />
|-<br />
| D29 || 3XXXXX || MD09<br />
|-<br />
| D28 || 4XXXXX || MD09<br />
|-<br />
| D27 || 5XXXXX || MD09<br />
|-<br />
| D26 || 6XXXXX || MD09<br />
|-<br />
| D25 || 7XXXXX || MD09<br />
|-<br />
| D24 || 0XXXXX || MD10<br />
|-<br />
| D23 || 1XXXXX || MD10<br />
|-<br />
| D22 || 2XXXXX || MD10<br />
|-<br />
| D21 || 3XXXXX || MD10<br />
|-<br />
| D16 || 4XXXXX || MD10<br />
|-<br />
| D15 || 5XXXXX || MD10<br />
|-<br />
| D14 || 6XXXXX || MD10<br />
|-<br />
| D13 || 7XXXXX || MD10<br />
|-<br />
| D12 || 0XXXXX || MD11<br />
|-<br />
| D11 || 1XXXXX || MD11<br />
|-<br />
| D10 || 2XXXXX || MD11<br />
|-<br />
| D09 || 3XXXXX || MD11<br />
|-<br />
| E16 || 4XXXXX || MD11<br />
|-<br />
| E15 || 5XXXXX || MD11<br />
|-<br />
| E14 || 6XXXXX || MD11<br />
|-<br />
| E13 || 7XXXXX || MD11<br />
|-<br />
| E12 || 0XXXXX || MD12<br />
|-<br />
| E11 || 1XXXXX || MD12<br />
|-<br />
| E10 || 2XXXXX || MD12<br />
|-<br />
| E09 || 3XXXXX || MD12<br />
|-<br />
| E28 || 4XXXXX || MD12<br />
|-<br />
| E27 || 5XXXXX || MD12<br />
|-<br />
| E26 || 6XXXXX || MD12<br />
|-<br />
| E25 || 7XXXXX || MD12<br />
|-<br />
| E24 || 0XXXXX || MD13<br />
|-<br />
| E23 || 1XXXXX || MD13<br />
|-<br />
| E22 || 2XXXXX || MD13<br />
|-<br />
| E21 || 3XXXXX || MD13<br />
|-<br />
| F16 || 4XXXXX || MD13<br />
|-<br />
| F15 || 5XXXXX || MD13<br />
|-<br />
| F14 || 6XXXXX || MD13<br />
|-<br />
| F13 || 7XXXXX || MD13<br />
|-<br />
| E32 || 0XXXXX || MD14<br />
|-<br />
| E31 || 1XXXXX || MD14<br />
|-<br />
| E30 || 2XXXXX || MD14<br />
|-<br />
| E29 || 3XXXXX || MD14<br />
|-<br />
| F20 || 4XXXXX || MD14<br />
|-<br />
| F19 || 5XXXXX || MD14<br />
|-<br />
| F18 || 6XXXXX || MD14<br />
|-<br />
| F17 || 7XXXXX || MD14<br />
|-<br />
| F32 || 0XXXXX || MD15<br />
|-<br />
| F31 || 1XXXXX || MD15<br />
|-<br />
| F30 || 2XXXXX || MD15<br />
|-<br />
| F29 || 3XXXXX || MD15<br />
|-<br />
| F28 || 4XXXXX || MD15<br />
|-<br />
| F27 || 5XXXXX || MD15<br />
|-<br />
| F26 || 6XXXXX || MD15<br />
|-<br />
| F25 || 7XXXXX || MD15<br />
|-<br />
| F24 || 0XXXXX || MD16<br />
|-<br />
| F23 || 1XXXXX || MD16<br />
|-<br />
| F22 || 2XXXXX || MD16<br />
|-<br />
| F21 || 3XXXXX || MD16<br />
|-<br />
| F36 || 4XXXXX || MD16<br />
|-<br />
| F35 || 5XXXXX || MD16<br />
|-<br />
| F34 || 6XXXXX || MD16<br />
|-<br />
| F33 || 7XXXXX || MD16<br />
|-<br />
| G32 || 0XXXXX || MD17<br />
|-<br />
| G31 || 1XXXXX || MD17<br />
|-<br />
| G30 || 2XXXXX || MD17<br />
|-<br />
| G29 || 3XXXXX || MD17<br />
|-<br />
| G36 || 4XXXXX || MD17<br />
|-<br />
| G35 || 5XXXXX || MD17<br />
|-<br />
| G34 || 6XXXXX || MD17<br />
|-<br />
| G33 || 7XXXXX || MD17<br />
|-<br />
| G24 || 0XXXXX || MD18<br />
|-<br />
| G23 || 1XXXXX || MD18<br />
|-<br />
| G22 || 2XXXXX || MD18<br />
|-<br />
| G21 || 3XXXXX || MD18<br />
|-<br />
| G28 || 4XXXXX || MD18<br />
|-<br />
| G27 || 5XXXXX || MD18<br />
|-<br />
| G26 || 6XXXXX || MD18<br />
|-<br />
| G25 || 7XXXXX || MD18<br />
|-<br />
| H32 || 0XXXXX || MD19<br />
|-<br />
| H31 || 1XXXXX || MD19<br />
|-<br />
| H30 || 2XXXXX || MD19<br />
|-<br />
| H29 || 3XXXXX || MD19<br />
|-<br />
| G20 || 4XXXXX || MD19<br />
|-<br />
| G19 || 5XXXXX || MD19<br />
|-<br />
| G18 || 6XXXXX || MD19<br />
|-<br />
| G17 || 7XXXXX || MD19<br />
|-<br />
| H24 || 0XXXXX || MD20<br />
|-<br />
| H23 || 1XXXXX || MD20<br />
|-<br />
| H22 || 2XXXXX || MD20<br />
|-<br />
| H21 || 3XXXXX || MD20<br />
|-<br />
| K37 || 4XXXXX || MD20<br />
|-<br />
| J37 || 5XXXXX || MD20<br />
|-<br />
| H37 || 6XXXXX || MD20<br />
|-<br />
| G37 || 7XXXXX || MD20<br />
|-<br />
| I32 || 0XXXXX || MD21<br />
|-<br />
| I31 || 1XXXXX || MD21<br />
|-<br />
| I30 || 2XXXXX || MD21<br />
|-<br />
| I29 || 3XXXXX || MD21<br />
|-<br />
| H36 || 4XXXXX || MD21<br />
|-<br />
| H35 || 5XXXXX || MD21<br />
|-<br />
| H34 || 6XXXXX || MD21<br />
|-<br />
| H33 || 7XXXXX || MD21<br />
|-<br />
| I24 || 0XXXXX || MD22<br />
|-<br />
| I23 || 1XXXXX || MD22<br />
|-<br />
| I22 || 2XXXXX || MD22<br />
|-<br />
| I21 || 3XXXXX || MD22<br />
|-<br />
| H28 || 4XXXXX || MD22<br />
|-<br />
| H27 || 5XXXXX || MD22<br />
|-<br />
| H26 || 6XXXXX || MD22<br />
|-<br />
| H25 || 7XXXXX || MD22<br />
|-<br />
| J32 || 0XXXXX || MD23<br />
|-<br />
| J31 || 1XXXXX || MD23<br />
|-<br />
| J30 || 2XXXXX || MD23<br />
|-<br />
| J29 || 3XXXXX || MD23<br />
|-<br />
| I36 || 4XXXXX || MD23<br />
|-<br />
| I35 || 5XXXXX || MD23<br />
|-<br />
| I34 || 6XXXXX || MD23<br />
|-<br />
| I33 || 7XXXXX || MD23<br />
|-<br />
| J24 || 0XXXXX || MD24<br />
|-<br />
| J23 || 1XXXXX || MD24<br />
|-<br />
| J22 || 2XXXXX || MD24<br />
|-<br />
| J21 || 3XXXXX || MD24<br />
|-<br />
| I28 || 4XXXXX || MD24<br />
|-<br />
| I27 || 5XXXXX || MD24<br />
|-<br />
| I26 || 6XXXXX || MD24<br />
|-<br />
| I25 || 7XXXXX || MD24<br />
|-<br />
| K32 || 0XXXXX || MD25<br />
|-<br />
| K31 || 1XXXXX || MD25<br />
|-<br />
| K30 || 2XXXXX || MD25<br />
|-<br />
| K29 || 3XXXXX || MD25<br />
|-<br />
| J36 || 4XXXXX || MD25<br />
|-<br />
| J35 || 5XXXXX || MD25<br />
|-<br />
| J34 || 6XXXXX || MD25<br />
|-<br />
| J33 || 7XXXXX || MD25<br />
|-<br />
| K24 || 0XXXXX || MD26<br />
|-<br />
| K23 || 1XXXXX || MD26<br />
|-<br />
| K22 || 2XXXXX || MD26<br />
|-<br />
| K21 || 3XXXXX || MD26<br />
|-<br />
| J28 || 4XXXXX || MD26<br />
|-<br />
| J27 || 5XXXXX || MD26<br />
|-<br />
| J26 || 6XXXXX || MD26<br />
|-<br />
| J25 || 7XXXXX || MD26<br />
|-<br />
| K20 || 0XXXXX || MD27<br />
|-<br />
| J20 || 1XXXXX || MD27<br />
|-<br />
| I20 || 2XXXXX || MD27<br />
|-<br />
| H20 || 3XXXXX || MD27<br />
|-<br />
| K36 || 4XXXXX || MD27<br />
|-<br />
| K35 || 5XXXXX || MD27<br />
|-<br />
| K34 || 6XXXXX || MD27<br />
|-<br />
| K33 || 7XXXXX || MD27<br />
|-<br />
| F12 || 0XXXXX || MD28<br />
|-<br />
| F11 || 1XXXXX || MD28<br />
|-<br />
| F10 || 2XXXXX || MD28<br />
|-<br />
| F09 || 3XXXXX || MD28<br />
|-<br />
| K28 || 4XXXXX || MD28<br />
|-<br />
| K26 || 6XXXXX || MD28<br />
|-<br />
| K27 || 5XXXXX || MD28<br />
|-<br />
| K25 || 7XXXXX || MD28<br />
|-<br />
| G12 || 0XXXXX || MD29<br />
|-<br />
| G11 || 1XXXXX || MD29<br />
|-<br />
| G10 || 2XXXXX || MD29<br />
|-<br />
| G09 || 3XXXXX || MD29<br />
|-<br />
| G16 || 4XXXXX || MD29<br />
|-<br />
| G15 || 5XXXXX || MD29<br />
|-<br />
| G14 || 6XXXXX || MD29<br />
|-<br />
| G13 || 7XXXXX || MD29<br />
|-<br />
| G04 || 0XXXXX || MD30<br />
|-<br />
| G03 || 1XXXXX || MD30<br />
|-<br />
| G02 || 2XXXXX || MD30<br />
|-<br />
| G01 || 3XXXXX || MD30<br />
|-<br />
| G08 || 4XXXXX || MD30<br />
|-<br />
| G07 || 5XXXXX || MD30<br />
|-<br />
| G06 || 6XXXXX || MD30<br />
|-<br />
| G05 || 7XXXXX || MD30<br />
|-<br />
| H04 || 0XXXXX || MD31<br />
|-<br />
| H03 || 1XXXXX || MD31<br />
|-<br />
| H02 || 2XXXXX || MD31<br />
|-<br />
| H01 || 3XXXXX || MD31<br />
|-<br />
| H08 || 4XXXXX || MD31<br />
|-<br />
| H07 || 5XXXXX || MD31<br />
|-<br />
| H06 || 6XXXXX || MD31<br />
|-<br />
| H05 || 7XXXXX || MD31<br />
|-<br />
| H12 || 0XXXXX || MD32<br />
|-<br />
| H11 || 1XXXXX || MD32<br />
|-<br />
| H10 || 2XXXXX || MD32<br />
|-<br />
| H09 || 3XXXXX || MD32<br />
|-<br />
| H16 || 4XXXXX || MD32<br />
|-<br />
| H15 || 5XXXXX || MD32<br />
|-<br />
| H14 || 6XXXXX || MD32<br />
|-<br />
| H13 || 7XXXXX || MD32<br />
|-<br />
| I04 || 0XXXXX || MD33<br />
|-<br />
| I03 || 1XXXXX || MD33<br />
|-<br />
| I02 || 2XXXXX || MD33<br />
|-<br />
| I01 || 3XXXXX || MD33<br />
|-<br />
| I08 || 4XXXXX || MD33<br />
|-<br />
| I07 || 5XXXXX || MD33<br />
|-<br />
| I06 || 6XXXXX || MD33<br />
|-<br />
| I05 || 7XXXXX || MD33<br />
|-<br />
| I12 || 0XXXXX || MD34<br />
|-<br />
| I11 || 1XXXXX || MD34<br />
|-<br />
| I10 || 2XXXXX || MD34<br />
|-<br />
| I09 || 3XXXXX || MD34<br />
|-<br />
| I16 || 4XXXXX || MD34<br />
|-<br />
| I15 || 5XXXXX || MD34<br />
|-<br />
| I14 || 6XXXXX || MD34<br />
|-<br />
| I13 || 7XXXXX || MD34<br />
|-<br />
| J04 || 0XXXXX || MD35<br />
|-<br />
| J03 || 1XXXXX || MD35<br />
|-<br />
| J02 || 2XXXXX || MD35<br />
|-<br />
| J01 || 3XXXXX || MD35<br />
|-<br />
| J08 || 4XXXXX || MD35<br />
|-<br />
| J07 || 5XXXXX || MD35<br />
|-<br />
| J06 || 6XXXXX || MD35<br />
|-<br />
| J05 || 7XXXXX || MD35<br />
|-<br />
| J12 || 0XXXXX || MD36<br />
|-<br />
| J11 || 1XXXXX || MD36<br />
|-<br />
| J10 || 2XXXXX || MD36<br />
|-<br />
| J09 || 3XXXXX || MD36<br />
|-<br />
| J16 || 4XXXXX || MD36<br />
|-<br />
| J15 || 5XXXXX || MD36<br />
|-<br />
| J14 || 6XXXXX || MD36<br />
|-<br />
| J13 || 7XXXXX || MD36<br />
|-<br />
| K04 || 0XXXXX || MD37<br />
|-<br />
| K03 || 1XXXXX || MD37<br />
|-<br />
| K02 || 2XXXXX || MD37<br />
|-<br />
| K01 || 3XXXXX || MD37<br />
|-<br />
| K08 || 4XXXXX || MD37<br />
|-<br />
| K07 || 5XXXXX || MD37<br />
|-<br />
| K06 || 6XXXXX || MD37<br />
|-<br />
| K05 || 7XXXXX || MD37<br />
|-<br />
| K12 || 0XXXXX || MD38<br />
|-<br />
| K11 || 1XXXXX || MD38<br />
|-<br />
| K10 || 2XXXXX || MD38<br />
|-<br />
| K09 || 3XXXXX || MD38<br />
|-<br />
| K16 || 4XXXXX || MD38<br />
|-<br />
| K15 || 5XXXXX || MD38<br />
|-<br />
| K14 || 6XXXXX || MD38<br />
|-<br />
| K13 || 7XXXXX || MD38<br />
|}<br />
<br />
===MS650-BA===<br />
<br />
Because I did not have an MS650-BA to test, I do not have as much information on this module as on the MS650-AA. Presumably, the MS650-BA has 4 ranks of 4MB in 1MBxX DRAMs, meaning there is no need to have 4 banks in each rank like the 256kx1 DRAMs on the MS650-AA.</div>
Jzatarski
https://gunkies.org/w/index.php?title=Talk:KA650_Main_Memory_System&diff=21866
Talk:KA650 Main Memory System
2019-11-24T06:25:16Z
<p>Jzatarski: Created page with "Not sure what category to put this in, anybody have ideas? ~~~~"</p>
<hr />
<div>Not sure what category to put this in, anybody have ideas? [[User:Jzatarski|Jzatarski]] ([[User talk:Jzatarski|talk]]) 07:25, 24 November 2019 (CET)</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_CPU&diff=21865
KA650 CPU
2019-11-24T06:20:01Z
<p>Jzatarski: add link to memory subsystem article</p>
<hr />
<div>{{InfoboxVAXCPU-Data<br />
| name = KA650<br />
| OS-support-VMS = V4.7A or later<br />
| OS-support-ULTRIX = ULTRIX V2.2<br />
| CPU-name-VMS = KA650<br />
| CPU-module = KA650<br />
| Module = M7620 [[#ref_3|[3]]]<br />
| Num-proc = 1<br />
| VMS-CPU = 10<br />
| VMS-XCPU = 1<br />
| SID = 0A000005<br />
| XSID = 01530101<br />
| CPU-chip = 78034 (CVAX) [[#ref_1|[1]]]<br />
| FPU-chip = 78132<br />
| CPU-technology = CMOS<br />
| CPU-cycle = 90ns [[#ref_4|[4]]]<br />
| Instruction-buffer = 12 bytes [[#ref_1|[1]]]<br />
| Translation-buffer = 28 entries [[#ref_1|[1]]]<br />
| Cache = 1KB (90ns) [[#ref_1|[1]]]<br />
| Backup-cache = 64KB (180ns longword, 270ns quadword) [[#ref_4|[4]]]<br />
| Compatibility-mode = No<br />
| Console-processor = CPU<br />
| Console-device = None<br />
| Firmware-version = V5.3<br />
| Console-speed = 300 to 38400<br />
| Minimum-memory = 8MB<br />
| Maximum-memory = 64MB<br />
| Memory-checking = 32 + 7 bit ECC [[#ref_4|[4]]]<br />
| Memory-cycle = 450ns longword, 720ns quadword [[#ref_4|[4]]]<br />
| BUS-Qbus = 1 @ 3.3MB/s<br />
| VUPs = 2.7 [[#ref_2|[2]]]<br />
}}<br />
<br />
The KA650 CPU module is a quad-height [[QBUS]] [[VAX]] CPU produced by [[DEC]]. [[#ref_4|[4]]]<br />
<br />
The KA650 is implemented using the [[CVAX]] with floating point instruction support provided by the [[CFPA]], main memory control provided by [[CMCTL]], and various system support functions by the [[SSC]].<br />
<br />
==Memory Subsystem==<br />
<br />
The KA650 memory subsystem is detailed elsewhere, [[DEC KA650 Memory Subsystem]].<br />
<br />
== References ==<br />
<br />
<div id="ref_1">[1] "CVAX-based Systems", Digital Technical Journal, Vol 1 No 7, August 1988. </div><br />
<div id="ref_2">[2] VAXcluster Systems. Guidelines for VAXCluster System Configurations. EK-VAXCT-CG-006</div><br />
<div id="ref_3">[3] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="ref_4">[4] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div><br />
<br />
{{stub}}</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_Main_Memory_System&diff=21864
KA650 Main Memory System
2019-11-24T06:16:06Z
<p>Jzatarski: description of KA650 memory cycles</p>
<hr />
<div>This page contains notes on troubleshooting, repair, and theory of operation of the DEC KA650/MS650 memory subsystem.<br />
<br />
==Overview==<br />
<br />
The MS650-AA and MS650-BA memory module are intended to be used with the DEC KA650 VAX CPU, as the name might suggest. These quad width cards contain 8MB and 16MB of RAM for the VAX, respectively, complete with ECC.<br />
<br />
==Theory of Operation==<br />
<br />
===Memory Controller General Architecture and Organization===<br />
<br />
====Memory Control Signals Provided by the CMCTL====<br />
The CMCTL IC is the DRAM controller for the KA650 CPU. It has 10 address line outputs, 39 memory data I/O (MD), 4 CAS outputs, 4 RAS outputs, a WE pin, and an SE pin. Also available to the RAM card are the inverse of the 20th and 21st address lines (XA20 & XA21), which are used as bank selection when using 256kxX DRAMs. The data lines are provided to the RAM cards through a 50 conductor ribbon cable, while the rest of the control lines are provided through the CD interconnect on the backplane.<br />
<br />
The 10 address lines carry the row address on the rising edge of a RAS line, followed by the column address on the rising edge of a CAS line.<br />
<br />
The 39 data I/O carry the 32 data and 7 ECC bits for the RAM.<br />
<br />
The 4 CAS (Column Address Strobe) lines allow strobing the column address on up to 4 separate memory modules.<br />
<br />
The 4 RAS (Row Address Strobe) lines allow selection of up to 4 banks on a single memory module.<br />
<br />
The WE (Write Enable) pin indicates that the CMCTL is writing to memory, rather than reading.<br />
<br />
The SE (Strobe Enable?) pin seems to indicate that the CMCTL is refreshing memory. This is necessary for the 8MB card to correctly strobe the RAS lines of each rank during a refresh cycle, due to the extra RAS gating circuitry necessary on cards with 256kxX DRAMs.<br />
<br />
The XA20 and XA21 lines are the inverse of the latched address lines from the CDAL bus.<br />
<br />
Note that many of the above control lines are inverse logic from what is normally used to drive DRAMs; in particular, CAS, RAS, and WE lines are inverted from the normal JEDEC DRAM convention of active low /RAS, /CAS, and /WE.<br />
<br />
====Memory Ranks & Banks====<br />
<br />
Due to the 10 bit address bus using conventional multiplexed row and column DRAM addressing, an effective 20 bit address is formed. This allows the CMCTL to address up to 1MWord per rank.<br />
<br />
By strobing different pairings of RAS and CAS (RAS0+CAS0 is one rank, while RAS0+CAS1 is another rank, while RAS1+CAS0 is yet another rank), the CMCTL supports up to 16 ranks of RAM, each 1Mx39. Each rank is thus 4MB of memory once ECC overhead is accounted for. This puts a 64MB cap on the maximum amount of memory the CMCTL can address (16 ranks of 4MB).<br />
<br />
When 256kxX DRAMs are used in place of 1MxX DRAMs, each 1Mx39 rank is further divided into 4 banks of 256kx39. Each bank is selected by XA20 and XA21, which are provided to the RAM cards via the CD interconnect. These address bits appear to only be valid on the rising edge of RAS. Before CAS has strobed, the bits have generally already changed since these are derived from the CDAL bus of the VAX CPU. These bits are used to gate the /RAS lines to the DRAMs ensuring that only the selected bank is addressed. The /CAS line for the card is not affected.<br />
<br />
The MS650-AA card contains 312 256kx1 ZIP DRAMs, organized into 8 banks of 256kx39. As previously mentioned, one memory rank as addressed by the CMCTL memory controller consists of 4 banks, making up a total of 1MWord of memory per rank. Each DRAM on the card corresponds to one bit of the 39 bit word within a 1MB address region of the VAX.<br />
<br />
===Addressing===<br />
<br />
The CMCTL appears to convert 32 bit VAX addresses into DRAM addressing as follows:<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
| A21 || A20 || A19 || A18 || A17 || A16 || A15 || A14 || A13 || A12 || A11 || A10 || A09 || A08 || A07 || A06 || A05 || A04 || A03 || A02<br />
|-<br />
| width=2.5% | R09 <br />
| width=2.5% | <br />
| width=2.5% | R08<br />
| width=2.5% | R07<br />
| width=2.5% | R06<br />
| width=2.5% | R05<br />
| width=2.5% | R04<br />
| width=2.5% | R03<br />
| width=2.5% | R02<br />
| width=2.5% | R01<br />
| width=2.5% | R00<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
|-<br />
| width=2.5% | <br />
| width=2.5% | C09<br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | C08<br />
| width=2.5% | C07<br />
| width=2.5% | C06<br />
| width=2.5% | C05<br />
| width=2.5% | C04<br />
| width=2.5% | C03<br />
| width=2.5% | C02<br />
| width=2.5% | C01<br />
| width=2.5% | C00<br />
|}<br />
<br />
Axx are VAX address lines<br />
Rxx are DRAM row address bits<br />
Cxx are DRAM column address bits<br />
<br />
This addressing scheme is used to ensure that 256kxX DRAMs (which use only 9 bit row and column addresses) are still supported for use with the CMCTL.<br />
<br />
It is, of course, still up to the CMCTL to determine which ranks are selected by the upper bits of a given physical address. This is determined by the MEMCSR0-15 registers, which seem to specify whether or not a bank is present, as well as what base address it resides at. It may perform other functions, but it does not seem to be documented in available documentation.<br />
<br />
===CAS and RAS Signals===<br />
<br />
Each 16MB or 8MB memory card for the KA650 uses one CAS line in its entirety. This is why a maximum of 4 cards may be used in a KA650 system. Each RAM card uses the first CAS line, and passes the remaining lines on to the next card, shifted down one bit. So for example, the first card gets CAS0 CAS1 CAS2 CAS3, in that order. It uses CAS0 and passes CAS1 CAS2 and CAS3 on to the next card, in that order. The next card uses CAS1 and passes on CAS2 and CAS3. This repeats until 4 cards have used up all of the available CAS lines.<br />
<br />
The CAS line is not gated in any way on the MS650-AA. The CAS line is simply buffered, inverted to match the polarity of the DRAMs, and distributed to all DRAMs on the card (likely with some hierarchical buffering methodology).<br />
<br />
===Refresh===<br />
<br />
DRAMs are built using one tiny MOS capacitor for each bit. These capacitors leak slightly and need to be periodically refreshed. DRAM rows are refreshed by simply addressing a row. Any row access refreshes that row, no column needs to be strobed for a refresh.<br />
<br />
As such, during refresh cycles, the CMCTL places a row address to be refreshed on the address bus, asserts SE, and asserts all RAS lines for several clock cycles. The purpose of the SE signal is so that RAM cards with 256kxX DRAMs do not gate any of the /RAS lines going to the DRAMs, or else only whatever DRAM bank is (randomly) addressed by XA20 and XA21 would be refreshed.<br />
<br />
===ECC===<br />
<br />
The ECC supported by the CMCTL, according to the KA650 technical manual, has the ability to detect and correct single data bit errors, detect single ECC bit errors, and detect double-bit data errors.<br />
<br />
ECC is generally based on producing parity bits of various collections of data bits. Since parity is based around the simple XOR, it is a linear operation in a manner of speaking. Luckily this means we can determine the ECC equations based on a number of sample data patterns and the respective ECC bits, such as the ECC produced for 0 data, and data with only one bit in the word set. By comparing the ECC for each test pattern to that of 0, we can determine which ECC bits each bit in the data word affects.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| bit || colspan=8 | data || ECC<br />
|-<br />
| || MSB || colspan = 6 | || LSB ||<br />
|-<br />
| - || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0111100<br />
|-<br />
| 0 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 1100100<br />
|-<br />
| 1 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0100000<br />
|-<br />
| 2 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0100110<br />
|-<br />
| 3 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 1100010<br />
|-<br />
| 4 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0100011<br />
|-<br />
| 5 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 1100111<br />
|-<br />
| 6 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 1100001<br />
|-<br />
| 7 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0100101<br />
|-<br />
| 8 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 1010100<br />
|-<br />
| 9 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0010000<br />
|-<br />
| 10 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0010110<br />
|-<br />
| 11 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 1010010<br />
|-<br />
| 12 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0010011<br />
|-<br />
| 13 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 1010111<br />
|-<br />
| 14 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 1010001<br />
|-<br />
| 15 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0010101<br />
|-<br />
| 16 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 1001100<br />
|-<br />
| 17 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0001000<br />
|-<br />
| 18 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0001110<br />
|-<br />
| 19 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 1001010<br />
|-<br />
| 20 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001011<br />
|-<br />
| 21 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001111<br />
|-<br />
| 22 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001001<br />
|-<br />
| 23 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001101<br />
|-<br />
| 24 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000100<br />
|-<br />
| 25 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000000<br />
|-<br />
| 26 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000110<br />
|-<br />
| 27 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000010<br />
|-<br />
| 28 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000011<br />
|-<br />
| 29 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000111<br />
|-<br />
| 30 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000001<br />
|-<br />
| 31 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000101<br />
|}<br />
<br />
<br />
The results of this are depicted below. The basic result is that toggling one of the bits that belongs to the ECC bit group will result in that ECC bit toggling as well.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| ECC bit || colspan=3 | MSB || colspan=26 | || colspan=3 | LSB<br />
|-<br />
|MD32<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|-<br />
|MD33<br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
|-<br />
|MD34<br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
|-<br />
|MD35<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD36<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD37<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|-<br />
|MD38<br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
|}<br />
<br />
An interesting and potentially useful point to note is that flipping bit 28 happens to flip all of the ECC bits together. Another interesting point is that inverting the entire data word produces the same ECC.<br />
<br />
From this information, we can derive some data patterns that produce useful ECC combinations, such as ECC of all zeroes, all ones, only one bit set, and only one bit clear. Looking at the table above, we got lucky and examples of many of these combinations were found by chance. In particular, we happened upon data combinations that produced every possibility of 1 ECC bit set. These, combined with the fact that we can toggle bit 28 to get the inverse ECC bits, gives us a set of data patterns which produce ECC with only one bit clear. From here, we only need to derive a combination which produces all-zero ECC, and from that, derive all-one ECC.<br />
<br />
Starting with the ECC for bit 31 set, we can toggle single bits at a time until we find a combination that produces the ECC we want.<br />
<nowiki><br />
31 1000 0000 0000 0000 0000 0000 0000 0000 1000101<br />
1000 0000 0000 0000 0000 0000 0000 0001 0011101<br />
1000 0000 0000 0000 0000 0010 0000 0001 0110001<br />
1000 0000 1000 0000 0000 0010 0000 0001 0000000 <--<br />
1001 0000 1000 0000 0000 0010 0000 0001 1111111 <--<br />
</nowiki><br />
<br />
The summary of these useful ECC combinations is tabulated below (data in hex, ECC in binary)<br />
<br />
useful ECC combinations:<br />
<br />
{| border=1 style="text-align:center"<br />
| ECC (binary) || data (hex)<br />
|-<br />
| 0000000 || 80800201<br />
|-<br />
| 0000001 || 40000000<br />
|-<br />
| 0000010 || 08000000<br />
|-<br />
| 0000100 || 01000000<br />
|-<br />
| 0001000 || 00020000<br />
|-<br />
| 0010000 || 00000200<br />
|-<br />
| 0100000 || 00000002<br />
|-<br />
| 1000000 || 02000000<br />
|-<br />
| 1111111 || 90800201<br />
|-<br />
| 1111110 || 50000000<br />
|-<br />
| 1111101 || 18000000<br />
|-<br />
| 1111011 || 11000000<br />
|-<br />
| 1110111 || 10020000<br />
|-<br />
| 1101111 || 10000200<br />
|-<br />
| 1011111 || 10000002<br />
|-<br />
| 0111111 || 12000000<br />
|}<br />
<br />
===KA650 Memory Bus Cycles===<br />
<br />
[[File:MS650-AA-Longword-write-same-rank-bank-cycle.png|200px|thumb|left|Longword write cycle]]<br />
<br />
During a longword write cycle, the CMCTL first places the row address onto the memory address bus. Next, it asserts the RAS signal, causing the DRAMs to latch the row address. It then asserts the write enable signal and places the column address on the address bus, then asserts the CAS signal. Lastly, the data and ECC bits are placed on the bus, and some time later CAS deasserts, followed by RAS. On the MS650-AA RAM module, XA20 and XA21 are decoded to determine which bank is selected.<br />
<br />
[[File:MS650-AA-Longword-write-diff-rank-same-bank-cycle.png|200px|thumb|left|Longword write cycle to a different rank]]<br />
<br />
The CMCTL will assert only the RAS line for the rank which is selected based on the memory address the VAX CPU is accessing.<br />
<br />
[[File:MS650-AA-Longword-write-same-rank-diff-bank-cycle.png|200px|thumb|left|Longword write cycle to a different bank]]<br />
<br />
Likewise, the MS650-AA decoding circuitry will only allow the RAS line for the bank selected by XA20 and XA21 to be asserted, while ensuring the RAS lines for the other banks are gated off.<br />
<br />
[[File:MS650-AA-byte-write-cycle.png|200px|thumb|left|Byte write cycle]]<br />
<br />
During a byte write cycle, the CMCTL must first read the entire 39 bit word from the MS650, modify the byte which is being written, recalculate the ECC bits, and write the entire 39 bit word back to the MS650. Due to this, both a read and write cycle can be seen within a byte write cycle. Note that the RAS line stays asserted throughout both the read and write parts of the cycle.<br />
<br />
[[File:MS650-AA-qword-write-cycle.png|200px|thumb|left|Quadword write cycle]]<br />
<br />
During a quadword write cycle, two 39 bit words must be written to the MS650. Note that RAS actually cycles twice during this cycle.<br />
<br />
[[File:MS650-AA-read-cycle.png|200px|thumb|left|read cycle]]<br />
<br />
Any read cycle longword or smaller will appear to have the same cycle. Since the MS650 must be read or written as a full 39 bit cycle, there is no effective difference between a byte, word, or longword read. A quadword read, of course, involves reading two 39 bit words, and would thus result in a double cycle similar to the quadword write.<br />
<br />
[[File:MS650-AA-refresh-cycle.png|200px|thumb|left|refresh cycle]]<br />
<br />
Lastly, during a refresh cycle, the SE signal is asserted to force an MS650-AA to allow all banks to be refreshed at once. This would not be necessary for the 1MxX DRAMs on an MS650-BA. Similarly, the CMCTL asserts all RAS lines to load the row to be refreshed into every DRAM connected to the KA650. There is no assertion of CAS since there is no need to actually access a specific location, just to refresh a given row.<br />
<br />
==KA650 VAX Firmware Memory Tests==<br />
<br />
Many of the tests built in to the firmware of the VAX can be quite thorough, if used properly. The tests can be accessed by the TEST command in the monitor, abbreviated to 't'.<br />
<br />
The tests report diagnostic information upon failure, encoded simply as a number of values in registers and memory locations on the stack. With the proper documentation, these values could be decoded to determine the problem. Lacking that documentation, I was able to reverse engineer enough of one test that was failing to understand it's output.<br />
<br />
===TEST 48: MEM_Addr_shrts===<br />
<br />
This test is normally used to check for shorted address lines. It will fill the memory with a pattern first, then it will check each word in order to see if it is still the same pattern. After checking a word, it will check the CMCTL status register to ensure there were no detected errors. Then it will replace the word with another pattern (usually mostly an inverse of the first pattern).<br />
<br />
If any address line is shorted, when the test writes the second pattern, it will affect another location in memory. When that location is encountered, it will read as the wrong data thus showing the issue. However, the test is also capable of detecting stuck bits the way it is designed, and this test happened to find all DRAM errors in my case.<br />
<br />
The output when the test encounters an error looks like the following:<br />
<br />
<nowiki><br />
>>>t 48<br />
<br />
<br />
?48 2 08 FF 00 0002<br />
<br />
P1=00000000 P2=04000000 P3=00000004 P4=00031000 P5=AAAAAAAA<br />
P6=55555555 P7=00000043 P8=200C5875 P9=00000000 P10=2005311F<br />
r0=45555555 r1=000C5860 r2=45555555 r3=00000004 r4=0000006B<br />
r5=AAAAAAAA r6=20080140 r7=20080144 r8=00000000 ERF=80000000<br />
<br />
Normal operation not possible.<br />
<br />
>>><br />
</nowiki><br />
<br />
I figured out the meaning of some of these registers for this test. First of all, P10 indicates an address where presumably DEC personnel would check a source listing to find out the exact meaning of the rest of the values shown. The meanings of the registers I have found are only valid for this routine, located near 2005311F.<br />
<br />
{| border=1 style="text-align:center"<br />
| register || description<br />
|-<br />
| r0 || contents of memory at address being tested<br />
|-<br />
| r1 || address being tested<br />
|-<br />
| r2 || expected pattern from memory being tested<br />
|-<br />
| r5 || pattern to replace location with<br />
|-<br />
| r6 || address of CMCTL MEMCSR16 (a diagnostic register)<br />
|-<br />
| P8 || contents of MEMCSR16<br />
|}<br />
<br />
==MEMCSR16 Register==<br />
<br />
The MEMCSR16 register gives us information on what kind of memory failure<br />
occurred. The bit meanings are as follows, according to the KA650 technical manual:<br />
<br />
{| border=1 style="text-align:center"<br />
| bits || description<br />
|-<br />
| <31> || set if uncorrectable error occurred<br />
|-<br />
| <30> || set if multiple uncorrectable errors occurred<br />
|-<br />
| <29> || set if correctable error occurred<br />
|-<br />
| <28:9> || page address where error occurred (pages are 512 bytes)<br />
|-<br />
| <8> || set if error ocurred during DMA<br />
|-<br />
| <7> || set if CDAL bus parity error occurred<br />
|-<br />
| <6:0> || error syndrome: a unique combination is produced here for each possible single bit error<br />
|}<br />
<br />
writing 1s to bits 31, 30, 29, 8, or 7 of MEMCSR16 resets those bits. bits 28:9 and 6:0 are read only.<br />
<br />
The MEMCSR registers can be read with test 9c.<br />
<br />
===Error Syndrome Field===<br />
<br />
The error syndrome is particularly useful for troubleshooting memory errors as it can tell us exactly which bit had the error. A list of the syndromes and the corresponding bit error is given below.<br />
<br />
{| border=1 style="text-align:center"<br />
| syndrome || bit position or error description<br />
|-<br />
| 0000000 || no error<br />
|-<br />
| 0000001 || 32<br />
|-<br />
| 0000010 || 33<br />
|-<br />
| 0000100 || 34<br />
|-<br />
| 0000111 || result of incorrect check bits written on CDAL parity error<br />
|-<br />
| 0001000 || 35<br />
|-<br />
| 0010000 || 36<br />
|-<br />
| 0011001 || 7<br />
|-<br />
| 0011010 || 2<br />
|-<br />
| 0011100 || 1<br />
|-<br />
| 0011111 || 4<br />
|-<br />
| 0100000 || 37<br />
|-<br />
| 0101001 || 15<br />
|-<br />
| 0101010 || 10<br />
|-<br />
| 0101100 || 9<br />
|-<br />
| 0101111 || 12<br />
|-<br />
| 0110001 || 23<br />
|-<br />
| 0110010 || 18<br />
|-<br />
| 0110100 || 17<br />
|-<br />
| 0110111 || 20<br />
|-<br />
| 0111000 || 24<br />
|-<br />
| 0111011 || 29<br />
|-<br />
| 0111101 || 30<br />
|-<br />
| 0111110 || 27<br />
|-<br />
| 1000000 || 38<br />
|-<br />
| 1011000 || 0<br />
|-<br />
| 1011011 || 5<br />
|-<br />
| 1011101 || 6<br />
|-<br />
| 1011110 || 3<br />
|-<br />
| 1101000 || 8<br />
|-<br />
| 1101011 || 13<br />
|-<br />
| 1101101 || 14<br />
|-<br />
| 1101110 || 11<br />
|-<br />
| 1110000 || 16<br />
|-<br />
| 1110011 || 21<br />
|-<br />
| 1110101 || 22<br />
|-<br />
| 1110110 || 19<br />
|-<br />
| 1111001 || 31<br />
|-<br />
| 1111010 || 26<br />
|-<br />
| 1111100 || 25<br />
|-<br />
| 1111111 || 28<br />
|-<br />
| other || multibit error<br />
|}<br />
<br />
==Troubleshooting==<br />
<br />
We now have all of the information necessary to narrow down which bits in which address regions are bad. However, that doesn't do any good for repair unless we also know which physical DRAMs that bit and region correspond to.<br />
<br />
===MS650-AA===<br />
<br />
Shown below is a diagram of the MS650-AA RAM card, broken up into 11 columns and 37 rows. Each spot in this grid contains up to 1 DRAM, but some locations contain other circuitry instead.<br />
<br />
<nowiki><br />
<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
--------------------------------------------------------------------------------<br />
01 | ooooooooooooooooooooooooo |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 01<br />
| --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
08 | --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 08<br />
|-------------------------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
09 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 09<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
16 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 16<br />
17 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 17<br />
18 |DDDDDDD|TTTTTTT TTTTTTTTT TTTTTTTT |DDDDDDDDDDDDD|TTTTTTTT TTTTTTTTT TTTTTTTT | 18<br />
19 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 19<br />
20 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 20<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
32 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 32<br />
33 |DDDDDDD-----------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 33<br />
36 |DDDDDDD| PPPPPPP TTTTT TTTTT |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 35<br />
37 |-------- TTTTTTT TTTTTTT --------DDDDDDDDDDDDDD-------DDDDDDDDDDDDDD| 37<br />
| -------------- --------------| <br />
| ___- - ___- |<br />
| | | || | | |<br />
-------------------- ----------------------------------------------------------<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
<br />
-----------------------------------------------<br />
| D DRAMS |<br />
| T TTL IC |<br />
| B some kind of DEC custom fast data buffer? |<br />
| P PAL16L8 |<br />
| o data connector |<br />
| | border |<br />
| - border |<br />
-----------------------------------------------<br />
<br />
</nowiki><br />
<br />
The MS650-AA RAM card uses two RAS lines. During normal initialization of the VAX, the rank connected to RAS0 will be first in memory, followed by the rank connected to RAS1. Presumably, the MS650-BA card would have 4 ranks.<br />
<br />
RAS0 - first 4MB<br />
RAS1 - second 4MB<br />
<br />
Based on the bit with the error, as well as the memory region where the error occurred, the specific DRAM with the failure can be found and replaced.<br />
<br />
Below is a list of the DRAMs sorted by memory region and bit, showing the grid location of the DRAM IC.<br />
<br />
By using the built in tests, along with MEMCSR16, and perhaps some manual DEPOSIT and EXAMINE testing, the bad DRAM should be possible to locate and then, using this table, the DRAM can be replaced.<br />
<br />
{| border=1 style="text-align:center"<br />
| DRAM || Address || data bit<br />
|-<br />
| A12 || 0XXXXX || MD00<br />
|-<br />
| A11 || 1XXXXX || MD00<br />
|-<br />
| A10 || 2XXXXX || MD00<br />
|-<br />
| A09 || 3XXXXX || MD00<br />
|-<br />
| A16 || 4XXXXX || MD00<br />
|-<br />
| A15 || 5XXXXX || MD00<br />
|-<br />
| A14 || 6XXXXX || MD00<br />
|-<br />
| A13 || 7XXXXX || MD00<br />
|-<br />
| A24 || 0XXXXX || MD01<br />
|-<br />
| A23 || 1XXXXX || MD01<br />
|-<br />
| A22 || 2XXXXX || MD01<br />
|-<br />
| A21 || 3XXXXX || MD01<br />
|-<br />
| A20 || 4XXXXX || MD01<br />
|-<br />
| A19 || 5XXXXX || MD01<br />
|-<br />
| A18 || 6XXXXX || MD01<br />
|-<br />
| A17 || 7XXXXX || MD01<br />
|-<br />
| A32 || 0XXXXX || MD02<br />
|-<br />
| A31 || 1XXXXX || MD02<br />
|-<br />
| A30 || 2XXXXX || MD02<br />
|-<br />
| A29 || 3XXXXX || MD02<br />
|-<br />
| A28 || 4XXXXX || MD02<br />
|-<br />
| A27 || 5XXXXX || MD02<br />
|-<br />
| A26 || 6XXXXX || MD02<br />
|-<br />
| A25 || 7XXXXX || MD02<br />
|-<br />
| B12 || 0XXXXX || MD03<br />
|-<br />
| B11 || 1XXXXX || MD03<br />
|-<br />
| B10 || 2XXXXX || MD03<br />
|-<br />
| B09 || 3XXXXX || MD03<br />
|-<br />
| A36 || 4XXXXX || MD03<br />
|-<br />
| A35 || 5XXXXX || MD03<br />
|-<br />
| A34 || 6XXXXX || MD03<br />
|-<br />
| A33 || 7XXXXX || MD03<br />
|-<br />
| B24 || 0XXXXX || MD04<br />
|-<br />
| B23 || 1XXXXX || MD04<br />
|-<br />
| B22 || 2XXXXX || MD04<br />
|-<br />
| B21 || 3XXXXX || MD04<br />
|-<br />
| B16 || 4XXXXX || MD04<br />
|-<br />
| B15 || 5XXXXX || MD04<br />
|-<br />
| B14 || 6XXXXX || MD04<br />
|-<br />
| B13 || 7XXXXX || MD04<br />
|-<br />
| B32 || 0XXXXX || MD05<br />
|-<br />
| B31 || 1XXXXX || MD05<br />
|-<br />
| B30 || 2XXXXX || MD05<br />
|-<br />
| B29 || 3XXXXX || MD05<br />
|-<br />
| B28 || 4XXXXX || MD05<br />
|-<br />
| B27 || 5XXXXX || MD05<br />
|-<br />
| B26 || 6XXXXX || MD05<br />
|-<br />
| B25 || 7XXXXX || MD05<br />
|-<br />
| C12 || 0XXXXX || MD06<br />
|-<br />
| C11 || 1XXXXX || MD06<br />
|-<br />
| C10 || 2XXXXX || MD06<br />
|-<br />
| C09 || 3XXXXX || MD06<br />
|-<br />
| C16 || 4XXXXX || MD06<br />
|-<br />
| C15 || 5XXXXX || MD06<br />
|-<br />
| C14 || 6XXXXX || MD06<br />
|-<br />
| C13 || 7XXXXX || MD06<br />
|-<br />
| C24 || 0XXXXX || MD07<br />
|-<br />
| C23 || 1XXXXX || MD07<br />
|-<br />
| C22 || 2XXXXX || MD07<br />
|-<br />
| C21 || 3XXXXX || MD07<br />
|-<br />
| E20 || 4XXXXX || MD07<br />
|-<br />
| D20 || 5XXXXX || MD07<br />
|-<br />
| C20 || 6XXXXX || MD07<br />
|-<br />
| B20 || 7XXXXX || MD07<br />
|-<br />
| C32 || 0XXXXX || MD08<br />
|-<br />
| C31 || 1XXXXX || MD08<br />
|-<br />
| C30 || 2XXXXX || MD08<br />
|-<br />
| C29 || 3XXXXX || MD08<br />
|-<br />
| C28 || 4XXXXX || MD08<br />
|-<br />
| C27 || 5XXXXX || MD08<br />
|-<br />
| C26 || 6XXXXX || MD08<br />
|-<br />
| C25 || 7XXXXX || MD08<br />
|-<br />
| D32 || 0XXXXX || MD09<br />
|-<br />
| D31 || 1XXXXX || MD09<br />
|-<br />
| D30 || 2XXXXX || MD09<br />
|-<br />
| D29 || 3XXXXX || MD09<br />
|-<br />
| D28 || 4XXXXX || MD09<br />
|-<br />
| D27 || 5XXXXX || MD09<br />
|-<br />
| D26 || 6XXXXX || MD09<br />
|-<br />
| D25 || 7XXXXX || MD09<br />
|-<br />
| D24 || 0XXXXX || MD10<br />
|-<br />
| D23 || 1XXXXX || MD10<br />
|-<br />
| D22 || 2XXXXX || MD10<br />
|-<br />
| D21 || 3XXXXX || MD10<br />
|-<br />
| D16 || 4XXXXX || MD10<br />
|-<br />
| D15 || 5XXXXX || MD10<br />
|-<br />
| D14 || 6XXXXX || MD10<br />
|-<br />
| D13 || 7XXXXX || MD10<br />
|-<br />
| D12 || 0XXXXX || MD11<br />
|-<br />
| D11 || 1XXXXX || MD11<br />
|-<br />
| D10 || 2XXXXX || MD11<br />
|-<br />
| D09 || 3XXXXX || MD11<br />
|-<br />
| E16 || 4XXXXX || MD11<br />
|-<br />
| E15 || 5XXXXX || MD11<br />
|-<br />
| E14 || 6XXXXX || MD11<br />
|-<br />
| E13 || 7XXXXX || MD11<br />
|-<br />
| E12 || 0XXXXX || MD12<br />
|-<br />
| E11 || 1XXXXX || MD12<br />
|-<br />
| E10 || 2XXXXX || MD12<br />
|-<br />
| E09 || 3XXXXX || MD12<br />
|-<br />
| E28 || 4XXXXX || MD12<br />
|-<br />
| E27 || 5XXXXX || MD12<br />
|-<br />
| E26 || 6XXXXX || MD12<br />
|-<br />
| E25 || 7XXXXX || MD12<br />
|-<br />
| E24 || 0XXXXX || MD13<br />
|-<br />
| E23 || 1XXXXX || MD13<br />
|-<br />
| E22 || 2XXXXX || MD13<br />
|-<br />
| E21 || 3XXXXX || MD13<br />
|-<br />
| F16 || 4XXXXX || MD13<br />
|-<br />
| F15 || 5XXXXX || MD13<br />
|-<br />
| F14 || 6XXXXX || MD13<br />
|-<br />
| F13 || 7XXXXX || MD13<br />
|-<br />
| E32 || 0XXXXX || MD14<br />
|-<br />
| E31 || 1XXXXX || MD14<br />
|-<br />
| E30 || 2XXXXX || MD14<br />
|-<br />
| E29 || 3XXXXX || MD14<br />
|-<br />
| F20 || 4XXXXX || MD14<br />
|-<br />
| F19 || 5XXXXX || MD14<br />
|-<br />
| F18 || 6XXXXX || MD14<br />
|-<br />
| F17 || 7XXXXX || MD14<br />
|-<br />
| F32 || 0XXXXX || MD15<br />
|-<br />
| F31 || 1XXXXX || MD15<br />
|-<br />
| F30 || 2XXXXX || MD15<br />
|-<br />
| F29 || 3XXXXX || MD15<br />
|-<br />
| F28 || 4XXXXX || MD15<br />
|-<br />
| F27 || 5XXXXX || MD15<br />
|-<br />
| F26 || 6XXXXX || MD15<br />
|-<br />
| F25 || 7XXXXX || MD15<br />
|-<br />
| F24 || 0XXXXX || MD16<br />
|-<br />
| F23 || 1XXXXX || MD16<br />
|-<br />
| F22 || 2XXXXX || MD16<br />
|-<br />
| F21 || 3XXXXX || MD16<br />
|-<br />
| F36 || 4XXXXX || MD16<br />
|-<br />
| F35 || 5XXXXX || MD16<br />
|-<br />
| F34 || 6XXXXX || MD16<br />
|-<br />
| F33 || 7XXXXX || MD16<br />
|-<br />
| G32 || 0XXXXX || MD17<br />
|-<br />
| G31 || 1XXXXX || MD17<br />
|-<br />
| G30 || 2XXXXX || MD17<br />
|-<br />
| G29 || 3XXXXX || MD17<br />
|-<br />
| G36 || 4XXXXX || MD17<br />
|-<br />
| G35 || 5XXXXX || MD17<br />
|-<br />
| G34 || 6XXXXX || MD17<br />
|-<br />
| G33 || 7XXXXX || MD17<br />
|-<br />
| G24 || 0XXXXX || MD18<br />
|-<br />
| G23 || 1XXXXX || MD18<br />
|-<br />
| G22 || 2XXXXX || MD18<br />
|-<br />
| G21 || 3XXXXX || MD18<br />
|-<br />
| G28 || 4XXXXX || MD18<br />
|-<br />
| G27 || 5XXXXX || MD18<br />
|-<br />
| G26 || 6XXXXX || MD18<br />
|-<br />
| G25 || 7XXXXX || MD18<br />
|-<br />
| H32 || 0XXXXX || MD19<br />
|-<br />
| H31 || 1XXXXX || MD19<br />
|-<br />
| H30 || 2XXXXX || MD19<br />
|-<br />
| H29 || 3XXXXX || MD19<br />
|-<br />
| G20 || 4XXXXX || MD19<br />
|-<br />
| G19 || 5XXXXX || MD19<br />
|-<br />
| G18 || 6XXXXX || MD19<br />
|-<br />
| G17 || 7XXXXX || MD19<br />
|-<br />
| H24 || 0XXXXX || MD20<br />
|-<br />
| H23 || 1XXXXX || MD20<br />
|-<br />
| H22 || 2XXXXX || MD20<br />
|-<br />
| H21 || 3XXXXX || MD20<br />
|-<br />
| K37 || 4XXXXX || MD20<br />
|-<br />
| J37 || 5XXXXX || MD20<br />
|-<br />
| H37 || 6XXXXX || MD20<br />
|-<br />
| G37 || 7XXXXX || MD20<br />
|-<br />
| I32 || 0XXXXX || MD21<br />
|-<br />
| I31 || 1XXXXX || MD21<br />
|-<br />
| I30 || 2XXXXX || MD21<br />
|-<br />
| I29 || 3XXXXX || MD21<br />
|-<br />
| H36 || 4XXXXX || MD21<br />
|-<br />
| H35 || 5XXXXX || MD21<br />
|-<br />
| H34 || 6XXXXX || MD21<br />
|-<br />
| H33 || 7XXXXX || MD21<br />
|-<br />
| I24 || 0XXXXX || MD22<br />
|-<br />
| I23 || 1XXXXX || MD22<br />
|-<br />
| I22 || 2XXXXX || MD22<br />
|-<br />
| I21 || 3XXXXX || MD22<br />
|-<br />
| H28 || 4XXXXX || MD22<br />
|-<br />
| H27 || 5XXXXX || MD22<br />
|-<br />
| H26 || 6XXXXX || MD22<br />
|-<br />
| H25 || 7XXXXX || MD22<br />
|-<br />
| J32 || 0XXXXX || MD23<br />
|-<br />
| J31 || 1XXXXX || MD23<br />
|-<br />
| J30 || 2XXXXX || MD23<br />
|-<br />
| J29 || 3XXXXX || MD23<br />
|-<br />
| I36 || 4XXXXX || MD23<br />
|-<br />
| I35 || 5XXXXX || MD23<br />
|-<br />
| I34 || 6XXXXX || MD23<br />
|-<br />
| I33 || 7XXXXX || MD23<br />
|-<br />
| J24 || 0XXXXX || MD24<br />
|-<br />
| J23 || 1XXXXX || MD24<br />
|-<br />
| J22 || 2XXXXX || MD24<br />
|-<br />
| J21 || 3XXXXX || MD24<br />
|-<br />
| I28 || 4XXXXX || MD24<br />
|-<br />
| I27 || 5XXXXX || MD24<br />
|-<br />
| I26 || 6XXXXX || MD24<br />
|-<br />
| I25 || 7XXXXX || MD24<br />
|-<br />
| K32 || 0XXXXX || MD25<br />
|-<br />
| K31 || 1XXXXX || MD25<br />
|-<br />
| K30 || 2XXXXX || MD25<br />
|-<br />
| K29 || 3XXXXX || MD25<br />
|-<br />
| J36 || 4XXXXX || MD25<br />
|-<br />
| J35 || 5XXXXX || MD25<br />
|-<br />
| J34 || 6XXXXX || MD25<br />
|-<br />
| J33 || 7XXXXX || MD25<br />
|-<br />
| K24 || 0XXXXX || MD26<br />
|-<br />
| K23 || 1XXXXX || MD26<br />
|-<br />
| K22 || 2XXXXX || MD26<br />
|-<br />
| K21 || 3XXXXX || MD26<br />
|-<br />
| J28 || 4XXXXX || MD26<br />
|-<br />
| J27 || 5XXXXX || MD26<br />
|-<br />
| J26 || 6XXXXX || MD26<br />
|-<br />
| J25 || 7XXXXX || MD26<br />
|-<br />
| K20 || 0XXXXX || MD27<br />
|-<br />
| J20 || 1XXXXX || MD27<br />
|-<br />
| I20 || 2XXXXX || MD27<br />
|-<br />
| H20 || 3XXXXX || MD27<br />
|-<br />
| K36 || 4XXXXX || MD27<br />
|-<br />
| K35 || 5XXXXX || MD27<br />
|-<br />
| K34 || 6XXXXX || MD27<br />
|-<br />
| K33 || 7XXXXX || MD27<br />
|-<br />
| F12 || 0XXXXX || MD28<br />
|-<br />
| F11 || 1XXXXX || MD28<br />
|-<br />
| F10 || 2XXXXX || MD28<br />
|-<br />
| F09 || 3XXXXX || MD28<br />
|-<br />
| K28 || 4XXXXX || MD28<br />
|-<br />
| K26 || 6XXXXX || MD28<br />
|-<br />
| K27 || 5XXXXX || MD28<br />
|-<br />
| K25 || 7XXXXX || MD28<br />
|-<br />
| G12 || 0XXXXX || MD29<br />
|-<br />
| G11 || 1XXXXX || MD29<br />
|-<br />
| G10 || 2XXXXX || MD29<br />
|-<br />
| G09 || 3XXXXX || MD29<br />
|-<br />
| G16 || 4XXXXX || MD29<br />
|-<br />
| G15 || 5XXXXX || MD29<br />
|-<br />
| G14 || 6XXXXX || MD29<br />
|-<br />
| G13 || 7XXXXX || MD29<br />
|-<br />
| G04 || 0XXXXX || MD30<br />
|-<br />
| G03 || 1XXXXX || MD30<br />
|-<br />
| G02 || 2XXXXX || MD30<br />
|-<br />
| G01 || 3XXXXX || MD30<br />
|-<br />
| G08 || 4XXXXX || MD30<br />
|-<br />
| G07 || 5XXXXX || MD30<br />
|-<br />
| G06 || 6XXXXX || MD30<br />
|-<br />
| G05 || 7XXXXX || MD30<br />
|-<br />
| H04 || 0XXXXX || MD31<br />
|-<br />
| H03 || 1XXXXX || MD31<br />
|-<br />
| H02 || 2XXXXX || MD31<br />
|-<br />
| H01 || 3XXXXX || MD31<br />
|-<br />
| H08 || 4XXXXX || MD31<br />
|-<br />
| H07 || 5XXXXX || MD31<br />
|-<br />
| H06 || 6XXXXX || MD31<br />
|-<br />
| H05 || 7XXXXX || MD31<br />
|-<br />
| H12 || 0XXXXX || MD32<br />
|-<br />
| H11 || 1XXXXX || MD32<br />
|-<br />
| H10 || 2XXXXX || MD32<br />
|-<br />
| H09 || 3XXXXX || MD32<br />
|-<br />
| H16 || 4XXXXX || MD32<br />
|-<br />
| H15 || 5XXXXX || MD32<br />
|-<br />
| H14 || 6XXXXX || MD32<br />
|-<br />
| H13 || 7XXXXX || MD32<br />
|-<br />
| I04 || 0XXXXX || MD33<br />
|-<br />
| I03 || 1XXXXX || MD33<br />
|-<br />
| I02 || 2XXXXX || MD33<br />
|-<br />
| I01 || 3XXXXX || MD33<br />
|-<br />
| I08 || 4XXXXX || MD33<br />
|-<br />
| I07 || 5XXXXX || MD33<br />
|-<br />
| I06 || 6XXXXX || MD33<br />
|-<br />
| I05 || 7XXXXX || MD33<br />
|-<br />
| I12 || 0XXXXX || MD34<br />
|-<br />
| I11 || 1XXXXX || MD34<br />
|-<br />
| I10 || 2XXXXX || MD34<br />
|-<br />
| I09 || 3XXXXX || MD34<br />
|-<br />
| I16 || 4XXXXX || MD34<br />
|-<br />
| I15 || 5XXXXX || MD34<br />
|-<br />
| I14 || 6XXXXX || MD34<br />
|-<br />
| I13 || 7XXXXX || MD34<br />
|-<br />
| J04 || 0XXXXX || MD35<br />
|-<br />
| J03 || 1XXXXX || MD35<br />
|-<br />
| J02 || 2XXXXX || MD35<br />
|-<br />
| J01 || 3XXXXX || MD35<br />
|-<br />
| J08 || 4XXXXX || MD35<br />
|-<br />
| J07 || 5XXXXX || MD35<br />
|-<br />
| J06 || 6XXXXX || MD35<br />
|-<br />
| J05 || 7XXXXX || MD35<br />
|-<br />
| J12 || 0XXXXX || MD36<br />
|-<br />
| J11 || 1XXXXX || MD36<br />
|-<br />
| J10 || 2XXXXX || MD36<br />
|-<br />
| J09 || 3XXXXX || MD36<br />
|-<br />
| J16 || 4XXXXX || MD36<br />
|-<br />
| J15 || 5XXXXX || MD36<br />
|-<br />
| J14 || 6XXXXX || MD36<br />
|-<br />
| J13 || 7XXXXX || MD36<br />
|-<br />
| K04 || 0XXXXX || MD37<br />
|-<br />
| K03 || 1XXXXX || MD37<br />
|-<br />
| K02 || 2XXXXX || MD37<br />
|-<br />
| K01 || 3XXXXX || MD37<br />
|-<br />
| K08 || 4XXXXX || MD37<br />
|-<br />
| K07 || 5XXXXX || MD37<br />
|-<br />
| K06 || 6XXXXX || MD37<br />
|-<br />
| K05 || 7XXXXX || MD37<br />
|-<br />
| K12 || 0XXXXX || MD38<br />
|-<br />
| K11 || 1XXXXX || MD38<br />
|-<br />
| K10 || 2XXXXX || MD38<br />
|-<br />
| K09 || 3XXXXX || MD38<br />
|-<br />
| K16 || 4XXXXX || MD38<br />
|-<br />
| K15 || 5XXXXX || MD38<br />
|-<br />
| K14 || 6XXXXX || MD38<br />
|-<br />
| K13 || 7XXXXX || MD38<br />
|}<br />
<br />
===MS650-BA===<br />
<br />
Because I did not have an MS650-BA to test, I do not have as much information on this module as on the MS650-AA. Presumably, the MS650-BA has 4 ranks of 4MB in 1MBxX DRAMs, meaning there is no need to have 4 banks in each rank like the 256kx1 DRAMs on the MS650-AA.</div>
Jzatarski
https://gunkies.org/w/index.php?title=File:MS650-AA-refresh-cycle.png&diff=21863
File:MS650-AA-refresh-cycle.png
2019-11-24T05:50:24Z
<p>Jzatarski: This is a logic analyzer capture of a memory refresh cycle performed by a KA650 on an MS650-AA memory board.</p>
<hr />
<div>This is a logic analyzer capture of a memory refresh cycle performed by a KA650 on an MS650-AA memory board.</div>
Jzatarski
https://gunkies.org/w/index.php?title=File:MS650-AA-read-cycle.png&diff=21862
File:MS650-AA-read-cycle.png
2019-11-24T05:47:43Z
<p>Jzatarski: This is a logic analyzer capture of a memory read performed by a KA650 on an MS650-AA memory board.</p>
<hr />
<div>This is a logic analyzer capture of a memory read performed by a KA650 on an MS650-AA memory board.</div>
Jzatarski
https://gunkies.org/w/index.php?title=File:MS650-AA-qword-write-cycle.png&diff=21861
File:MS650-AA-qword-write-cycle.png
2019-11-24T05:46:56Z
<p>Jzatarski: This is a logic analyzer capture of a quadword write performed by a KA650 on an MS650-AA memory board.</p>
<hr />
<div>This is a logic analyzer capture of a quadword write performed by a KA650 on an MS650-AA memory board.</div>
Jzatarski
https://gunkies.org/w/index.php?title=File:MS650-AA-Longword-write-same-rank-diff-bank-cycle.png&diff=21860
File:MS650-AA-Longword-write-same-rank-diff-bank-cycle.png
2019-11-24T05:44:58Z
<p>Jzatarski: This is a logic analyzer capture of a longword write to the same rank but different bank as the DUT performed by a KA650 on an MS650-AA memory board.</p>
<hr />
<div>This is a logic analyzer capture of a longword write to the same rank but different bank as the DUT performed by a KA650 on an MS650-AA memory board.</div>
Jzatarski
https://gunkies.org/w/index.php?title=File:MS650-AA-Longword-write-same-rank-bank-cycle.png&diff=21859
File:MS650-AA-Longword-write-same-rank-bank-cycle.png
2019-11-24T05:43:43Z
<p>Jzatarski: This is a logic analyzer capture of a longword write to the same rank and bank as the DUT performed by a KA650 on an MS650-AA memory board.</p>
<hr />
<div>This is a logic analyzer capture of a longword write to the same rank and bank as the DUT performed by a KA650 on an MS650-AA memory board.</div>
Jzatarski
https://gunkies.org/w/index.php?title=File:MS650-AA-Longword-write-diff-rank-same-bank-cycle.png&diff=21858
File:MS650-AA-Longword-write-diff-rank-same-bank-cycle.png
2019-11-24T05:42:07Z
<p>Jzatarski: This is a logic analyzer capture of a longword write to a different rank, but same bank, as the DUT performed by a KA650 on an MS650-AA memory board.</p>
<hr />
<div>This is a logic analyzer capture of a longword write to a different rank, but same bank, as the DUT performed by a KA650 on an MS650-AA memory board.</div>
Jzatarski
https://gunkies.org/w/index.php?title=File:MS650-AA-byte-write-cycle.png&diff=21857
File:MS650-AA-byte-write-cycle.png
2019-11-24T05:27:05Z
<p>Jzatarski: This is a logic analyzer capture of a byte write performed by a KA650 on an MS650-AA memory board.</p>
<hr />
<div>This is a logic analyzer capture of a byte write performed by a KA650 on an MS650-AA memory board.</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_Main_Memory_System&diff=21856
KA650 Main Memory System
2019-11-24T04:54:14Z
<p>Jzatarski: </p>
<hr />
<div>This page contains notes on troubleshooting, repair, and theory of operation of the DEC KA650/MS650 memory subsystem.<br />
<br />
==Overview==<br />
<br />
The MS650-AA and MS650-BA memory module are intended to be used with the DEC KA650 VAX CPU, as the name might suggest. These quad width cards contain 8MB and 16MB of RAM for the VAX, respectively, complete with ECC.<br />
<br />
==Theory of Operation==<br />
<br />
===Memory Controller General Architecture and Organization===<br />
<br />
====Memory Control Signals Provided by the CMCTL====<br />
The CMCTL IC is the DRAM controller for the KA650 CPU. It has 10 address line outputs, 39 memory data I/O (MD), 4 CAS outputs, 4 RAS outputs, a WE pin, and an SE pin. Also available to the RAM card are the inverse of the 20th and 21st address lines (XA20 & XA21), which are used as bank selection when using 256kxX DRAMs. The data lines are provided to the RAM cards through a 50 conductor ribbon cable, while the rest of the control lines are provided through the CD interconnect on the backplane.<br />
<br />
The 10 address lines carry the row address on the rising edge of a RAS line, followed by the column address on the rising edge of a CAS line.<br />
<br />
The 39 data I/O carry the 32 data and 7 ECC bits for the RAM.<br />
<br />
The 4 CAS (Column Address Strobe) lines allow strobing the column address on up to 4 separate memory modules.<br />
<br />
The 4 RAS (Row Address Strobe) lines allow selection of up to 4 banks on a single memory module.<br />
<br />
The WE (Write Enable) pin indicates that the CMCTL is writing to memory, rather than reading.<br />
<br />
The SE (Strobe Enable?) pin seems to indicate that the CMCTL is refreshing memory. This is necessary for the 8MB card to correctly strobe the RAS lines of each rank during a refresh cycle, due to the extra RAS gating circuitry necessary on cards with 256kxX DRAMs.<br />
<br />
The XA20 and XA21 lines are the inverse of the latched address lines from the CDAL bus.<br />
<br />
Note that many of the above control lines are inverse logic from what is normally used to drive DRAMs; in particular, CAS, RAS, and WE lines are inverted from the normal JEDEC DRAM convention of active low /RAS, /CAS, and /WE.<br />
<br />
====Memory Ranks & Banks====<br />
<br />
Due to the 10 bit address bus using conventional multiplexed row and column DRAM addressing, an effective 20 bit address is formed. This allows the CMCTL to address up to 1MWord per rank.<br />
<br />
By strobing different pairings of RAS and CAS (RAS0+CAS0 is one rank, while RAS0+CAS1 is another rank, while RAS1+CAS0 is yet another rank), the CMCTL supports up to 16 ranks of RAM, each 1Mx39. Each rank is thus 4MB of memory once ECC overhead is accounted for. This puts a 64MB cap on the maximum amount of memory the CMCTL can address (16 ranks of 4MB).<br />
<br />
When 256kxX DRAMs are used in place of 1MxX DRAMs, each 1Mx39 rank is further divided into 4 banks of 256kx39. Each bank is selected by XA20 and XA21, which are provided to the RAM cards via the CD interconnect. These address bits appear to only be valid on the rising edge of RAS. Before CAS has strobed, the bits have generally already changed since these are derived from the CDAL bus of the VAX CPU. These bits are used to gate the /RAS lines to the DRAMs ensuring that only the selected bank is addressed. The /CAS line for the card is not affected.<br />
<br />
The MS650-AA card contains 312 256kx1 ZIP DRAMs, organized into 8 banks of 256kx39. As previously mentioned, one memory rank as addressed by the CMCTL memory controller consists of 4 banks, making up a total of 1MWord of memory per rank. Each DRAM on the card corresponds to one bit of the 39 bit word within a 1MB address region of the VAX.<br />
<br />
===Addressing===<br />
<br />
The CMCTL appears to convert 32 bit VAX addresses into DRAM addressing as follows:<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
| A21 || A20 || A19 || A18 || A17 || A16 || A15 || A14 || A13 || A12 || A11 || A10 || A09 || A08 || A07 || A06 || A05 || A04 || A03 || A02<br />
|-<br />
| width=2.5% | R09 <br />
| width=2.5% | <br />
| width=2.5% | R08<br />
| width=2.5% | R07<br />
| width=2.5% | R06<br />
| width=2.5% | R05<br />
| width=2.5% | R04<br />
| width=2.5% | R03<br />
| width=2.5% | R02<br />
| width=2.5% | R01<br />
| width=2.5% | R00<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
|-<br />
| width=2.5% | <br />
| width=2.5% | C09<br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | C08<br />
| width=2.5% | C07<br />
| width=2.5% | C06<br />
| width=2.5% | C05<br />
| width=2.5% | C04<br />
| width=2.5% | C03<br />
| width=2.5% | C02<br />
| width=2.5% | C01<br />
| width=2.5% | C00<br />
|}<br />
<br />
Axx are VAX address lines<br />
Rxx are DRAM row address bits<br />
Cxx are DRAM column address bits<br />
<br />
This addressing scheme is used to ensure that 256kxX DRAMs (which use only 9 bit row and column addresses) are still supported for use with the CMCTL.<br />
<br />
It is, of course, still up to the CMCTL to determine which ranks are selected by the upper bits of a given physical address. This is determined by the MEMCSR0-15 registers, which seem to specify whether or not a bank is present, as well as what base address it resides at. It may perform other functions, but it does not seem to be documented in available documentation.<br />
<br />
===CAS and RAS Signals===<br />
<br />
Each 16MB or 8MB memory card for the KA650 uses one CAS line in its entirety. This is why a maximum of 4 cards may be used in a KA650 system. Each RAM card uses the first CAS line, and passes the remaining lines on to the next card, shifted down one bit. So for example, the first card gets CAS0 CAS1 CAS2 CAS3, in that order. It uses CAS0 and passes CAS1 CAS2 and CAS3 on to the next card, in that order. The next card uses CAS1 and passes on CAS2 and CAS3. This repeats until 4 cards have used up all of the available CAS lines.<br />
<br />
The CAS line is not gated in any way on the MS650-AA. The CAS line is simply buffered, inverted to match the polarity of the DRAMs, and distributed to all DRAMs on the card (likely with some hierarchical buffering methodology).<br />
<br />
===Refresh===<br />
<br />
DRAMs are built using one tiny MOS capacitor for each bit. These capacitors leak slightly and need to be periodically refreshed. DRAM rows are refreshed by simply addressing a row. Any row access refreshes that row, no column needs to be strobed for a refresh.<br />
<br />
As such, during refresh cycles, the CMCTL places a row address to be refreshed on the address bus, asserts SE, and asserts all RAS lines for several clock cycles. The purpose of the SE signal is so that RAM cards with 256kxX DRAMs do not gate any of the /RAS lines going to the DRAMs, or else only whatever DRAM bank is (randomly) addressed by XA20 and XA21 would be refreshed.<br />
<br />
===ECC===<br />
<br />
The ECC supported by the CMCTL, according to the KA650 technical manual, has the ability to detect and correct single data bit errors, detect single ECC bit errors, and detect double-bit data errors.<br />
<br />
ECC is generally based on producing parity bits of various collections of data bits. Since parity is based around the simple XOR, it is a linear operation in a manner of speaking. Luckily this means we can determine the ECC equations based on a number of sample data patterns and the respective ECC bits, such as the ECC produced for 0 data, and data with only one bit in the word set. By comparing the ECC for each test pattern to that of 0, we can determine which ECC bits each bit in the data word affects.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| bit || colspan=8 | data || ECC<br />
|-<br />
| || MSB || colspan = 6 | || LSB ||<br />
|-<br />
| - || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0111100<br />
|-<br />
| 0 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 1100100<br />
|-<br />
| 1 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0100000<br />
|-<br />
| 2 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0100110<br />
|-<br />
| 3 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 1100010<br />
|-<br />
| 4 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0100011<br />
|-<br />
| 5 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 1100111<br />
|-<br />
| 6 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 1100001<br />
|-<br />
| 7 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0100101<br />
|-<br />
| 8 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 1010100<br />
|-<br />
| 9 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0010000<br />
|-<br />
| 10 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0010110<br />
|-<br />
| 11 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 1010010<br />
|-<br />
| 12 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0010011<br />
|-<br />
| 13 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 1010111<br />
|-<br />
| 14 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 1010001<br />
|-<br />
| 15 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0010101<br />
|-<br />
| 16 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 1001100<br />
|-<br />
| 17 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0001000<br />
|-<br />
| 18 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0001110<br />
|-<br />
| 19 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 1001010<br />
|-<br />
| 20 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001011<br />
|-<br />
| 21 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001111<br />
|-<br />
| 22 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001001<br />
|-<br />
| 23 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001101<br />
|-<br />
| 24 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000100<br />
|-<br />
| 25 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000000<br />
|-<br />
| 26 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000110<br />
|-<br />
| 27 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000010<br />
|-<br />
| 28 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000011<br />
|-<br />
| 29 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000111<br />
|-<br />
| 30 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000001<br />
|-<br />
| 31 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000101<br />
|}<br />
<br />
<br />
The results of this are depicted below. The basic result is that toggling one of the bits that belongs to the ECC bit group will result in that ECC bit toggling as well.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| ECC bit || colspan=3 | MSB || colspan=26 | || colspan=3 | LSB<br />
|-<br />
|MD32<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|-<br />
|MD33<br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
|-<br />
|MD34<br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
|-<br />
|MD35<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD36<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD37<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|-<br />
|MD38<br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
|}<br />
<br />
An interesting and potentially useful point to note is that flipping bit 28 happens to flip all of the ECC bits together. Another interesting point is that inverting the entire data word produces the same ECC.<br />
<br />
From this information, we can derive some data patterns that produce useful ECC combinations, such as ECC of all zeroes, all ones, only one bit set, and only one bit clear. Looking at the table above, we got lucky and examples of many of these combinations were found by chance. In particular, we happened upon data combinations that produced every possibility of 1 ECC bit set. These, combined with the fact that we can toggle bit 28 to get the inverse ECC bits, gives us a set of data patterns which produce ECC with only one bit clear. From here, we only need to derive a combination which produces all-zero ECC, and from that, derive all-one ECC.<br />
<br />
Starting with the ECC for bit 31 set, we can toggle single bits at a time until we find a combination that produces the ECC we want.<br />
<nowiki><br />
31 1000 0000 0000 0000 0000 0000 0000 0000 1000101<br />
1000 0000 0000 0000 0000 0000 0000 0001 0011101<br />
1000 0000 0000 0000 0000 0010 0000 0001 0110001<br />
1000 0000 1000 0000 0000 0010 0000 0001 0000000 <--<br />
1001 0000 1000 0000 0000 0010 0000 0001 1111111 <--<br />
</nowiki><br />
<br />
The summary of these useful ECC combinations is tabulated below (data in hex, ECC in binary)<br />
<br />
useful ECC combinations:<br />
<br />
{| border=1 style="text-align:center"<br />
| ECC (binary) || data (hex)<br />
|-<br />
| 0000000 || 80800201<br />
|-<br />
| 0000001 || 40000000<br />
|-<br />
| 0000010 || 08000000<br />
|-<br />
| 0000100 || 01000000<br />
|-<br />
| 0001000 || 00020000<br />
|-<br />
| 0010000 || 00000200<br />
|-<br />
| 0100000 || 00000002<br />
|-<br />
| 1000000 || 02000000<br />
|-<br />
| 1111111 || 90800201<br />
|-<br />
| 1111110 || 50000000<br />
|-<br />
| 1111101 || 18000000<br />
|-<br />
| 1111011 || 11000000<br />
|-<br />
| 1110111 || 10020000<br />
|-<br />
| 1101111 || 10000200<br />
|-<br />
| 1011111 || 10000002<br />
|-<br />
| 0111111 || 12000000<br />
|}<br />
<br />
==KA650 VAX Firmware Memory Tests==<br />
<br />
Many of the tests built in to the firmware of the VAX can be quite thorough, if used properly. The tests can be accessed by the TEST command in the monitor, abbreviated to 't'.<br />
<br />
The tests report diagnostic information upon failure, encoded simply as a number of values in registers and memory locations on the stack. With the proper documentation, these values could be decoded to determine the problem. Lacking that documentation, I was able to reverse engineer enough of one test that was failing to understand it's output.<br />
<br />
===TEST 48: MEM_Addr_shrts===<br />
<br />
This test is normally used to check for shorted address lines. It will fill the memory with a pattern first, then it will check each word in order to see if it is still the same pattern. After checking a word, it will check the CMCTL status register to ensure there were no detected errors. Then it will replace the word with another pattern (usually mostly an inverse of the first pattern).<br />
<br />
If any address line is shorted, when the test writes the second pattern, it will affect another location in memory. When that location is encountered, it will read as the wrong data thus showing the issue. However, the test is also capable of detecting stuck bits the way it is designed, and this test happened to find all DRAM errors in my case.<br />
<br />
The output when the test encounters an error looks like the following:<br />
<br />
<nowiki><br />
>>>t 48<br />
<br />
<br />
?48 2 08 FF 00 0002<br />
<br />
P1=00000000 P2=04000000 P3=00000004 P4=00031000 P5=AAAAAAAA<br />
P6=55555555 P7=00000043 P8=200C5875 P9=00000000 P10=2005311F<br />
r0=45555555 r1=000C5860 r2=45555555 r3=00000004 r4=0000006B<br />
r5=AAAAAAAA r6=20080140 r7=20080144 r8=00000000 ERF=80000000<br />
<br />
Normal operation not possible.<br />
<br />
>>><br />
</nowiki><br />
<br />
I figured out the meaning of some of these registers for this test. First of all, P10 indicates an address where presumably DEC personnel would check a source listing to find out the exact meaning of the rest of the values shown. The meanings of the registers I have found are only valid for this routine, located near 2005311F.<br />
<br />
{| border=1 style="text-align:center"<br />
| register || description<br />
|-<br />
| r0 || contents of memory at address being tested<br />
|-<br />
| r1 || address being tested<br />
|-<br />
| r2 || expected pattern from memory being tested<br />
|-<br />
| r5 || pattern to replace location with<br />
|-<br />
| r6 || address of CMCTL MEMCSR16 (a diagnostic register)<br />
|-<br />
| P8 || contents of MEMCSR16<br />
|}<br />
<br />
==MEMCSR16 Register==<br />
<br />
The MEMCSR16 register gives us information on what kind of memory failure<br />
occurred. The bit meanings are as follows, according to the KA650 technical manual:<br />
<br />
{| border=1 style="text-align:center"<br />
| bits || description<br />
|-<br />
| <31> || set if uncorrectable error occurred<br />
|-<br />
| <30> || set if multiple uncorrectable errors occurred<br />
|-<br />
| <29> || set if correctable error occurred<br />
|-<br />
| <28:9> || page address where error occurred (pages are 512 bytes)<br />
|-<br />
| <8> || set if error ocurred during DMA<br />
|-<br />
| <7> || set if CDAL bus parity error occurred<br />
|-<br />
| <6:0> || error syndrome: a unique combination is produced here for each possible single bit error<br />
|}<br />
<br />
writing 1s to bits 31, 30, 29, 8, or 7 of MEMCSR16 resets those bits. bits 28:9 and 6:0 are read only.<br />
<br />
The MEMCSR registers can be read with test 9c.<br />
<br />
===Error Syndrome Field===<br />
<br />
The error syndrome is particularly useful for troubleshooting memory errors as it can tell us exactly which bit had the error. A list of the syndromes and the corresponding bit error is given below.<br />
<br />
{| border=1 style="text-align:center"<br />
| syndrome || bit position or error description<br />
|-<br />
| 0000000 || no error<br />
|-<br />
| 0000001 || 32<br />
|-<br />
| 0000010 || 33<br />
|-<br />
| 0000100 || 34<br />
|-<br />
| 0000111 || result of incorrect check bits written on CDAL parity error<br />
|-<br />
| 0001000 || 35<br />
|-<br />
| 0010000 || 36<br />
|-<br />
| 0011001 || 7<br />
|-<br />
| 0011010 || 2<br />
|-<br />
| 0011100 || 1<br />
|-<br />
| 0011111 || 4<br />
|-<br />
| 0100000 || 37<br />
|-<br />
| 0101001 || 15<br />
|-<br />
| 0101010 || 10<br />
|-<br />
| 0101100 || 9<br />
|-<br />
| 0101111 || 12<br />
|-<br />
| 0110001 || 23<br />
|-<br />
| 0110010 || 18<br />
|-<br />
| 0110100 || 17<br />
|-<br />
| 0110111 || 20<br />
|-<br />
| 0111000 || 24<br />
|-<br />
| 0111011 || 29<br />
|-<br />
| 0111101 || 30<br />
|-<br />
| 0111110 || 27<br />
|-<br />
| 1000000 || 38<br />
|-<br />
| 1011000 || 0<br />
|-<br />
| 1011011 || 5<br />
|-<br />
| 1011101 || 6<br />
|-<br />
| 1011110 || 3<br />
|-<br />
| 1101000 || 8<br />
|-<br />
| 1101011 || 13<br />
|-<br />
| 1101101 || 14<br />
|-<br />
| 1101110 || 11<br />
|-<br />
| 1110000 || 16<br />
|-<br />
| 1110011 || 21<br />
|-<br />
| 1110101 || 22<br />
|-<br />
| 1110110 || 19<br />
|-<br />
| 1111001 || 31<br />
|-<br />
| 1111010 || 26<br />
|-<br />
| 1111100 || 25<br />
|-<br />
| 1111111 || 28<br />
|-<br />
| other || multibit error<br />
|}<br />
<br />
==Troubleshooting==<br />
<br />
We now have all of the information necessary to narrow down which bits in which address regions are bad. However, that doesn't do any good for repair unless we also know which physical DRAMs that bit and region correspond to.<br />
<br />
===MS650-AA===<br />
<br />
Shown below is a diagram of the MS650-AA RAM card, broken up into 11 columns and 37 rows. Each spot in this grid contains up to 1 DRAM, but some locations contain other circuitry instead.<br />
<br />
<nowiki><br />
<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
--------------------------------------------------------------------------------<br />
01 | ooooooooooooooooooooooooo |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 01<br />
| --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
08 | --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 08<br />
|-------------------------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
09 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 09<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
16 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 16<br />
17 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 17<br />
18 |DDDDDDD|TTTTTTT TTTTTTTTT TTTTTTTT |DDDDDDDDDDDDD|TTTTTTTT TTTTTTTTT TTTTTTTT | 18<br />
19 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 19<br />
20 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 20<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
32 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 32<br />
33 |DDDDDDD-----------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 33<br />
36 |DDDDDDD| PPPPPPP TTTTT TTTTT |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 35<br />
37 |-------- TTTTTTT TTTTTTT --------DDDDDDDDDDDDDD-------DDDDDDDDDDDDDD| 37<br />
| -------------- --------------| <br />
| ___- - ___- |<br />
| | | || | | |<br />
-------------------- ----------------------------------------------------------<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
<br />
-----------------------------------------------<br />
| D DRAMS |<br />
| T TTL IC |<br />
| B some kind of DEC custom fast data buffer? |<br />
| P PAL16L8 |<br />
| o data connector |<br />
| | border |<br />
| - border |<br />
-----------------------------------------------<br />
<br />
</nowiki><br />
<br />
The MS650-AA RAM card uses two RAS lines. During normal initialization of the VAX, the rank connected to RAS0 will be first in memory, followed by the rank connected to RAS1. Presumably, the MS650-BA card would have 4 ranks.<br />
<br />
RAS0 - first 4MB<br />
RAS1 - second 4MB<br />
<br />
Based on the bit with the error, as well as the memory region where the error occurred, the specific DRAM with the failure can be found and replaced.<br />
<br />
Below is a list of the DRAMs sorted by memory region and bit, showing the grid location of the DRAM IC.<br />
<br />
By using the built in tests, along with MEMCSR16, and perhaps some manual DEPOSIT and EXAMINE testing, the bad DRAM should be possible to locate and then, using this table, the DRAM can be replaced.<br />
<br />
{| border=1 style="text-align:center"<br />
| DRAM || Address || data bit<br />
|-<br />
| A12 || 0XXXXX || MD00<br />
|-<br />
| A11 || 1XXXXX || MD00<br />
|-<br />
| A10 || 2XXXXX || MD00<br />
|-<br />
| A09 || 3XXXXX || MD00<br />
|-<br />
| A16 || 4XXXXX || MD00<br />
|-<br />
| A15 || 5XXXXX || MD00<br />
|-<br />
| A14 || 6XXXXX || MD00<br />
|-<br />
| A13 || 7XXXXX || MD00<br />
|-<br />
| A24 || 0XXXXX || MD01<br />
|-<br />
| A23 || 1XXXXX || MD01<br />
|-<br />
| A22 || 2XXXXX || MD01<br />
|-<br />
| A21 || 3XXXXX || MD01<br />
|-<br />
| A20 || 4XXXXX || MD01<br />
|-<br />
| A19 || 5XXXXX || MD01<br />
|-<br />
| A18 || 6XXXXX || MD01<br />
|-<br />
| A17 || 7XXXXX || MD01<br />
|-<br />
| A32 || 0XXXXX || MD02<br />
|-<br />
| A31 || 1XXXXX || MD02<br />
|-<br />
| A30 || 2XXXXX || MD02<br />
|-<br />
| A29 || 3XXXXX || MD02<br />
|-<br />
| A28 || 4XXXXX || MD02<br />
|-<br />
| A27 || 5XXXXX || MD02<br />
|-<br />
| A26 || 6XXXXX || MD02<br />
|-<br />
| A25 || 7XXXXX || MD02<br />
|-<br />
| B12 || 0XXXXX || MD03<br />
|-<br />
| B11 || 1XXXXX || MD03<br />
|-<br />
| B10 || 2XXXXX || MD03<br />
|-<br />
| B09 || 3XXXXX || MD03<br />
|-<br />
| A36 || 4XXXXX || MD03<br />
|-<br />
| A35 || 5XXXXX || MD03<br />
|-<br />
| A34 || 6XXXXX || MD03<br />
|-<br />
| A33 || 7XXXXX || MD03<br />
|-<br />
| B24 || 0XXXXX || MD04<br />
|-<br />
| B23 || 1XXXXX || MD04<br />
|-<br />
| B22 || 2XXXXX || MD04<br />
|-<br />
| B21 || 3XXXXX || MD04<br />
|-<br />
| B16 || 4XXXXX || MD04<br />
|-<br />
| B15 || 5XXXXX || MD04<br />
|-<br />
| B14 || 6XXXXX || MD04<br />
|-<br />
| B13 || 7XXXXX || MD04<br />
|-<br />
| B32 || 0XXXXX || MD05<br />
|-<br />
| B31 || 1XXXXX || MD05<br />
|-<br />
| B30 || 2XXXXX || MD05<br />
|-<br />
| B29 || 3XXXXX || MD05<br />
|-<br />
| B28 || 4XXXXX || MD05<br />
|-<br />
| B27 || 5XXXXX || MD05<br />
|-<br />
| B26 || 6XXXXX || MD05<br />
|-<br />
| B25 || 7XXXXX || MD05<br />
|-<br />
| C12 || 0XXXXX || MD06<br />
|-<br />
| C11 || 1XXXXX || MD06<br />
|-<br />
| C10 || 2XXXXX || MD06<br />
|-<br />
| C09 || 3XXXXX || MD06<br />
|-<br />
| C16 || 4XXXXX || MD06<br />
|-<br />
| C15 || 5XXXXX || MD06<br />
|-<br />
| C14 || 6XXXXX || MD06<br />
|-<br />
| C13 || 7XXXXX || MD06<br />
|-<br />
| C24 || 0XXXXX || MD07<br />
|-<br />
| C23 || 1XXXXX || MD07<br />
|-<br />
| C22 || 2XXXXX || MD07<br />
|-<br />
| C21 || 3XXXXX || MD07<br />
|-<br />
| E20 || 4XXXXX || MD07<br />
|-<br />
| D20 || 5XXXXX || MD07<br />
|-<br />
| C20 || 6XXXXX || MD07<br />
|-<br />
| B20 || 7XXXXX || MD07<br />
|-<br />
| C32 || 0XXXXX || MD08<br />
|-<br />
| C31 || 1XXXXX || MD08<br />
|-<br />
| C30 || 2XXXXX || MD08<br />
|-<br />
| C29 || 3XXXXX || MD08<br />
|-<br />
| C28 || 4XXXXX || MD08<br />
|-<br />
| C27 || 5XXXXX || MD08<br />
|-<br />
| C26 || 6XXXXX || MD08<br />
|-<br />
| C25 || 7XXXXX || MD08<br />
|-<br />
| D32 || 0XXXXX || MD09<br />
|-<br />
| D31 || 1XXXXX || MD09<br />
|-<br />
| D30 || 2XXXXX || MD09<br />
|-<br />
| D29 || 3XXXXX || MD09<br />
|-<br />
| D28 || 4XXXXX || MD09<br />
|-<br />
| D27 || 5XXXXX || MD09<br />
|-<br />
| D26 || 6XXXXX || MD09<br />
|-<br />
| D25 || 7XXXXX || MD09<br />
|-<br />
| D24 || 0XXXXX || MD10<br />
|-<br />
| D23 || 1XXXXX || MD10<br />
|-<br />
| D22 || 2XXXXX || MD10<br />
|-<br />
| D21 || 3XXXXX || MD10<br />
|-<br />
| D16 || 4XXXXX || MD10<br />
|-<br />
| D15 || 5XXXXX || MD10<br />
|-<br />
| D14 || 6XXXXX || MD10<br />
|-<br />
| D13 || 7XXXXX || MD10<br />
|-<br />
| D12 || 0XXXXX || MD11<br />
|-<br />
| D11 || 1XXXXX || MD11<br />
|-<br />
| D10 || 2XXXXX || MD11<br />
|-<br />
| D09 || 3XXXXX || MD11<br />
|-<br />
| E16 || 4XXXXX || MD11<br />
|-<br />
| E15 || 5XXXXX || MD11<br />
|-<br />
| E14 || 6XXXXX || MD11<br />
|-<br />
| E13 || 7XXXXX || MD11<br />
|-<br />
| E12 || 0XXXXX || MD12<br />
|-<br />
| E11 || 1XXXXX || MD12<br />
|-<br />
| E10 || 2XXXXX || MD12<br />
|-<br />
| E09 || 3XXXXX || MD12<br />
|-<br />
| E28 || 4XXXXX || MD12<br />
|-<br />
| E27 || 5XXXXX || MD12<br />
|-<br />
| E26 || 6XXXXX || MD12<br />
|-<br />
| E25 || 7XXXXX || MD12<br />
|-<br />
| E24 || 0XXXXX || MD13<br />
|-<br />
| E23 || 1XXXXX || MD13<br />
|-<br />
| E22 || 2XXXXX || MD13<br />
|-<br />
| E21 || 3XXXXX || MD13<br />
|-<br />
| F16 || 4XXXXX || MD13<br />
|-<br />
| F15 || 5XXXXX || MD13<br />
|-<br />
| F14 || 6XXXXX || MD13<br />
|-<br />
| F13 || 7XXXXX || MD13<br />
|-<br />
| E32 || 0XXXXX || MD14<br />
|-<br />
| E31 || 1XXXXX || MD14<br />
|-<br />
| E30 || 2XXXXX || MD14<br />
|-<br />
| E29 || 3XXXXX || MD14<br />
|-<br />
| F20 || 4XXXXX || MD14<br />
|-<br />
| F19 || 5XXXXX || MD14<br />
|-<br />
| F18 || 6XXXXX || MD14<br />
|-<br />
| F17 || 7XXXXX || MD14<br />
|-<br />
| F32 || 0XXXXX || MD15<br />
|-<br />
| F31 || 1XXXXX || MD15<br />
|-<br />
| F30 || 2XXXXX || MD15<br />
|-<br />
| F29 || 3XXXXX || MD15<br />
|-<br />
| F28 || 4XXXXX || MD15<br />
|-<br />
| F27 || 5XXXXX || MD15<br />
|-<br />
| F26 || 6XXXXX || MD15<br />
|-<br />
| F25 || 7XXXXX || MD15<br />
|-<br />
| F24 || 0XXXXX || MD16<br />
|-<br />
| F23 || 1XXXXX || MD16<br />
|-<br />
| F22 || 2XXXXX || MD16<br />
|-<br />
| F21 || 3XXXXX || MD16<br />
|-<br />
| F36 || 4XXXXX || MD16<br />
|-<br />
| F35 || 5XXXXX || MD16<br />
|-<br />
| F34 || 6XXXXX || MD16<br />
|-<br />
| F33 || 7XXXXX || MD16<br />
|-<br />
| G32 || 0XXXXX || MD17<br />
|-<br />
| G31 || 1XXXXX || MD17<br />
|-<br />
| G30 || 2XXXXX || MD17<br />
|-<br />
| G29 || 3XXXXX || MD17<br />
|-<br />
| G36 || 4XXXXX || MD17<br />
|-<br />
| G35 || 5XXXXX || MD17<br />
|-<br />
| G34 || 6XXXXX || MD17<br />
|-<br />
| G33 || 7XXXXX || MD17<br />
|-<br />
| G24 || 0XXXXX || MD18<br />
|-<br />
| G23 || 1XXXXX || MD18<br />
|-<br />
| G22 || 2XXXXX || MD18<br />
|-<br />
| G21 || 3XXXXX || MD18<br />
|-<br />
| G28 || 4XXXXX || MD18<br />
|-<br />
| G27 || 5XXXXX || MD18<br />
|-<br />
| G26 || 6XXXXX || MD18<br />
|-<br />
| G25 || 7XXXXX || MD18<br />
|-<br />
| H32 || 0XXXXX || MD19<br />
|-<br />
| H31 || 1XXXXX || MD19<br />
|-<br />
| H30 || 2XXXXX || MD19<br />
|-<br />
| H29 || 3XXXXX || MD19<br />
|-<br />
| G20 || 4XXXXX || MD19<br />
|-<br />
| G19 || 5XXXXX || MD19<br />
|-<br />
| G18 || 6XXXXX || MD19<br />
|-<br />
| G17 || 7XXXXX || MD19<br />
|-<br />
| H24 || 0XXXXX || MD20<br />
|-<br />
| H23 || 1XXXXX || MD20<br />
|-<br />
| H22 || 2XXXXX || MD20<br />
|-<br />
| H21 || 3XXXXX || MD20<br />
|-<br />
| K37 || 4XXXXX || MD20<br />
|-<br />
| J37 || 5XXXXX || MD20<br />
|-<br />
| H37 || 6XXXXX || MD20<br />
|-<br />
| G37 || 7XXXXX || MD20<br />
|-<br />
| I32 || 0XXXXX || MD21<br />
|-<br />
| I31 || 1XXXXX || MD21<br />
|-<br />
| I30 || 2XXXXX || MD21<br />
|-<br />
| I29 || 3XXXXX || MD21<br />
|-<br />
| H36 || 4XXXXX || MD21<br />
|-<br />
| H35 || 5XXXXX || MD21<br />
|-<br />
| H34 || 6XXXXX || MD21<br />
|-<br />
| H33 || 7XXXXX || MD21<br />
|-<br />
| I24 || 0XXXXX || MD22<br />
|-<br />
| I23 || 1XXXXX || MD22<br />
|-<br />
| I22 || 2XXXXX || MD22<br />
|-<br />
| I21 || 3XXXXX || MD22<br />
|-<br />
| H28 || 4XXXXX || MD22<br />
|-<br />
| H27 || 5XXXXX || MD22<br />
|-<br />
| H26 || 6XXXXX || MD22<br />
|-<br />
| H25 || 7XXXXX || MD22<br />
|-<br />
| J32 || 0XXXXX || MD23<br />
|-<br />
| J31 || 1XXXXX || MD23<br />
|-<br />
| J30 || 2XXXXX || MD23<br />
|-<br />
| J29 || 3XXXXX || MD23<br />
|-<br />
| I36 || 4XXXXX || MD23<br />
|-<br />
| I35 || 5XXXXX || MD23<br />
|-<br />
| I34 || 6XXXXX || MD23<br />
|-<br />
| I33 || 7XXXXX || MD23<br />
|-<br />
| J24 || 0XXXXX || MD24<br />
|-<br />
| J23 || 1XXXXX || MD24<br />
|-<br />
| J22 || 2XXXXX || MD24<br />
|-<br />
| J21 || 3XXXXX || MD24<br />
|-<br />
| I28 || 4XXXXX || MD24<br />
|-<br />
| I27 || 5XXXXX || MD24<br />
|-<br />
| I26 || 6XXXXX || MD24<br />
|-<br />
| I25 || 7XXXXX || MD24<br />
|-<br />
| K32 || 0XXXXX || MD25<br />
|-<br />
| K31 || 1XXXXX || MD25<br />
|-<br />
| K30 || 2XXXXX || MD25<br />
|-<br />
| K29 || 3XXXXX || MD25<br />
|-<br />
| J36 || 4XXXXX || MD25<br />
|-<br />
| J35 || 5XXXXX || MD25<br />
|-<br />
| J34 || 6XXXXX || MD25<br />
|-<br />
| J33 || 7XXXXX || MD25<br />
|-<br />
| K24 || 0XXXXX || MD26<br />
|-<br />
| K23 || 1XXXXX || MD26<br />
|-<br />
| K22 || 2XXXXX || MD26<br />
|-<br />
| K21 || 3XXXXX || MD26<br />
|-<br />
| J28 || 4XXXXX || MD26<br />
|-<br />
| J27 || 5XXXXX || MD26<br />
|-<br />
| J26 || 6XXXXX || MD26<br />
|-<br />
| J25 || 7XXXXX || MD26<br />
|-<br />
| K20 || 0XXXXX || MD27<br />
|-<br />
| J20 || 1XXXXX || MD27<br />
|-<br />
| I20 || 2XXXXX || MD27<br />
|-<br />
| H20 || 3XXXXX || MD27<br />
|-<br />
| K36 || 4XXXXX || MD27<br />
|-<br />
| K35 || 5XXXXX || MD27<br />
|-<br />
| K34 || 6XXXXX || MD27<br />
|-<br />
| K33 || 7XXXXX || MD27<br />
|-<br />
| F12 || 0XXXXX || MD28<br />
|-<br />
| F11 || 1XXXXX || MD28<br />
|-<br />
| F10 || 2XXXXX || MD28<br />
|-<br />
| F09 || 3XXXXX || MD28<br />
|-<br />
| K28 || 4XXXXX || MD28<br />
|-<br />
| K26 || 6XXXXX || MD28<br />
|-<br />
| K27 || 5XXXXX || MD28<br />
|-<br />
| K25 || 7XXXXX || MD28<br />
|-<br />
| G12 || 0XXXXX || MD29<br />
|-<br />
| G11 || 1XXXXX || MD29<br />
|-<br />
| G10 || 2XXXXX || MD29<br />
|-<br />
| G09 || 3XXXXX || MD29<br />
|-<br />
| G16 || 4XXXXX || MD29<br />
|-<br />
| G15 || 5XXXXX || MD29<br />
|-<br />
| G14 || 6XXXXX || MD29<br />
|-<br />
| G13 || 7XXXXX || MD29<br />
|-<br />
| G04 || 0XXXXX || MD30<br />
|-<br />
| G03 || 1XXXXX || MD30<br />
|-<br />
| G02 || 2XXXXX || MD30<br />
|-<br />
| G01 || 3XXXXX || MD30<br />
|-<br />
| G08 || 4XXXXX || MD30<br />
|-<br />
| G07 || 5XXXXX || MD30<br />
|-<br />
| G06 || 6XXXXX || MD30<br />
|-<br />
| G05 || 7XXXXX || MD30<br />
|-<br />
| H04 || 0XXXXX || MD31<br />
|-<br />
| H03 || 1XXXXX || MD31<br />
|-<br />
| H02 || 2XXXXX || MD31<br />
|-<br />
| H01 || 3XXXXX || MD31<br />
|-<br />
| H08 || 4XXXXX || MD31<br />
|-<br />
| H07 || 5XXXXX || MD31<br />
|-<br />
| H06 || 6XXXXX || MD31<br />
|-<br />
| H05 || 7XXXXX || MD31<br />
|-<br />
| H12 || 0XXXXX || MD32<br />
|-<br />
| H11 || 1XXXXX || MD32<br />
|-<br />
| H10 || 2XXXXX || MD32<br />
|-<br />
| H09 || 3XXXXX || MD32<br />
|-<br />
| H16 || 4XXXXX || MD32<br />
|-<br />
| H15 || 5XXXXX || MD32<br />
|-<br />
| H14 || 6XXXXX || MD32<br />
|-<br />
| H13 || 7XXXXX || MD32<br />
|-<br />
| I04 || 0XXXXX || MD33<br />
|-<br />
| I03 || 1XXXXX || MD33<br />
|-<br />
| I02 || 2XXXXX || MD33<br />
|-<br />
| I01 || 3XXXXX || MD33<br />
|-<br />
| I08 || 4XXXXX || MD33<br />
|-<br />
| I07 || 5XXXXX || MD33<br />
|-<br />
| I06 || 6XXXXX || MD33<br />
|-<br />
| I05 || 7XXXXX || MD33<br />
|-<br />
| I12 || 0XXXXX || MD34<br />
|-<br />
| I11 || 1XXXXX || MD34<br />
|-<br />
| I10 || 2XXXXX || MD34<br />
|-<br />
| I09 || 3XXXXX || MD34<br />
|-<br />
| I16 || 4XXXXX || MD34<br />
|-<br />
| I15 || 5XXXXX || MD34<br />
|-<br />
| I14 || 6XXXXX || MD34<br />
|-<br />
| I13 || 7XXXXX || MD34<br />
|-<br />
| J04 || 0XXXXX || MD35<br />
|-<br />
| J03 || 1XXXXX || MD35<br />
|-<br />
| J02 || 2XXXXX || MD35<br />
|-<br />
| J01 || 3XXXXX || MD35<br />
|-<br />
| J08 || 4XXXXX || MD35<br />
|-<br />
| J07 || 5XXXXX || MD35<br />
|-<br />
| J06 || 6XXXXX || MD35<br />
|-<br />
| J05 || 7XXXXX || MD35<br />
|-<br />
| J12 || 0XXXXX || MD36<br />
|-<br />
| J11 || 1XXXXX || MD36<br />
|-<br />
| J10 || 2XXXXX || MD36<br />
|-<br />
| J09 || 3XXXXX || MD36<br />
|-<br />
| J16 || 4XXXXX || MD36<br />
|-<br />
| J15 || 5XXXXX || MD36<br />
|-<br />
| J14 || 6XXXXX || MD36<br />
|-<br />
| J13 || 7XXXXX || MD36<br />
|-<br />
| K04 || 0XXXXX || MD37<br />
|-<br />
| K03 || 1XXXXX || MD37<br />
|-<br />
| K02 || 2XXXXX || MD37<br />
|-<br />
| K01 || 3XXXXX || MD37<br />
|-<br />
| K08 || 4XXXXX || MD37<br />
|-<br />
| K07 || 5XXXXX || MD37<br />
|-<br />
| K06 || 6XXXXX || MD37<br />
|-<br />
| K05 || 7XXXXX || MD37<br />
|-<br />
| K12 || 0XXXXX || MD38<br />
|-<br />
| K11 || 1XXXXX || MD38<br />
|-<br />
| K10 || 2XXXXX || MD38<br />
|-<br />
| K09 || 3XXXXX || MD38<br />
|-<br />
| K16 || 4XXXXX || MD38<br />
|-<br />
| K15 || 5XXXXX || MD38<br />
|-<br />
| K14 || 6XXXXX || MD38<br />
|-<br />
| K13 || 7XXXXX || MD38<br />
|}<br />
<br />
===MS650-BA===<br />
<br />
Because I did not have an MS650-BA to test, I do not have as much information on this module as on the MS650-AA. Presumably, the MS650-BA has 4 ranks of 4MB in 1MBxX DRAMs, meaning there is no need to have 4 banks in each rank like the 256kx1 DRAMs on the MS650-AA.</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_Main_Memory_System&diff=21855
KA650 Main Memory System
2019-11-24T04:53:19Z
<p>Jzatarski: last table formatted</p>
<hr />
<div>This page contains notes on troubleshooting, repair, and theory of operation of the DEC KA650/MS650 memory subsystem.<br />
<br />
==Overview==<br />
<br />
The MS650-AA and MS650-BA memory module are intended to be used with the DEC KA650 VAX CPU, as the name might suggest. These quad width cards contain 8MB and 16MB of RAM for the VAX, respectively, complete with ECC.<br />
<br />
==Theory of Operation==<br />
<br />
===Memory Controller General Architecture and Organization===<br />
<br />
====Memory Control Signals Provided by the CMCTL====<br />
The CMCTL IC is the DRAM controller for the KA650 CPU. It has 10 address line outputs, 39 memory data I/O (MD), 4 CAS outputs, 4 RAS outputs, a WE pin, and an SE pin. Also available to the RAM card are the inverse of the 20th and 21st address lines (XA20 & XA21), which are used as bank selection when using 256kxX DRAMs. The data lines are provided to the RAM cards through a 50 conductor ribbon cable, while the rest of the control lines are provided through the CD interconnect on the backplane.<br />
<br />
The 10 address lines carry the row address on the rising edge of a RAS line, followed by the column address on the rising edge of a CAS line.<br />
<br />
The 39 data I/O carry the 32 data and 7 ECC bits for the RAM.<br />
<br />
The 4 CAS (Column Address Strobe) lines allow strobing the column address on up to 4 separate memory modules.<br />
<br />
The 4 RAS (Row Address Strobe) lines allow selection of up to 4 banks on a single memory module.<br />
<br />
The WE (Write Enable) pin indicates that the CMCTL is writing to memory, rather than reading.<br />
<br />
The SE (Strobe Enable?) pin seems to indicate that the CMCTL is refreshing memory. This is necessary for the 8MB card to correctly strobe the RAS lines of each rank during a refresh cycle, due to the extra RAS gating circuitry necessary on cards with 256kxX DRAMs.<br />
<br />
The XA20 and XA21 lines are the inverse of the latched address lines from the CDAL bus.<br />
<br />
Note that many of the above control lines are inverse logic from what is normally used to drive DRAMs; in particular, CAS, RAS, and WE lines are inverted from the normal JEDEC DRAM convention of active low /RAS, /CAS, and /WE.<br />
<br />
====Memory Ranks & Banks====<br />
<br />
Due to the 10 bit address bus using conventional multiplexed row and column DRAM addressing, an effective 20 bit address is formed. This allows the CMCTL to address up to 1MWord per rank.<br />
<br />
By strobing different pairings of RAS and CAS (RAS0+CAS0 is one rank, while RAS0+CAS1 is another rank, while RAS1+CAS0 is yet another rank), the CMCTL supports up to 16 ranks of RAM, each 1Mx39. Each rank is thus 4MB of memory once ECC overhead is accounted for. This puts a 64MB cap on the maximum amount of memory the CMCTL can address (16 ranks of 4MB).<br />
<br />
When 256kxX DRAMs are used in place of 1MxX DRAMs, each 1Mx39 rank is further divided into 4 banks of 256kx39. Each bank is selected by XA20 and XA21, which are provided to the RAM cards via the CD interconnect. These address bits appear to only be valid on the rising edge of RAS. Before CAS has strobed, the bits have generally already changed since these are derived from the CDAL bus of the VAX CPU. These bits are used to gate the /RAS lines to the DRAMs ensuring that only the selected bank is addressed. The /CAS line for the card is not affected.<br />
<br />
The MS650-AA card contains 312 256kx1 ZIP DRAMs, organized into 8 banks of 256kx39. As previously mentioned, one memory rank as addressed by the CMCTL memory controller consists of 4 banks, making up a total of 1MWord of memory per rank. Each DRAM on the card corresponds to one bit of the 39 bit word within a 1MB address region of the VAX.<br />
<br />
===Addressing===<br />
<br />
The CMCTL appears to convert 32 bit VAX addresses into DRAM addressing as follows:<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
| A21 || A20 || A19 || A18 || A17 || A16 || A15 || A14 || A13 || A12 || A11 || A10 || A09 || A08 || A07 || A06 || A05 || A04 || A03 || A02<br />
|-<br />
| width=2.5% | R09 <br />
| width=2.5% | <br />
| width=2.5% | R08<br />
| width=2.5% | R07<br />
| width=2.5% | R06<br />
| width=2.5% | R05<br />
| width=2.5% | R04<br />
| width=2.5% | R03<br />
| width=2.5% | R02<br />
| width=2.5% | R01<br />
| width=2.5% | R00<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
|-<br />
| width=2.5% | <br />
| width=2.5% | C09<br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | C08<br />
| width=2.5% | C07<br />
| width=2.5% | C06<br />
| width=2.5% | C05<br />
| width=2.5% | C04<br />
| width=2.5% | C03<br />
| width=2.5% | C02<br />
| width=2.5% | C01<br />
| width=2.5% | C00<br />
|}<br />
<br />
Axx are VAX address lines<br />
Rxx are DRAM row address bits<br />
Cxx are DRAM column address bits<br />
<br />
This addressing scheme is used to ensure that 256kxX DRAMs (which use only 9 bit row and column addresses) are still supported for use with the CMCTL.<br />
<br />
It is, of course, still up to the CMCTL to determine which ranks are selected by the upper bits of a given physical address. This is determined by the MEMCSR0-15 registers, which seem to specify whether or not a bank is present, as well as what base address it resides at. It may perform other functions, but it does not seem to be documented in available documentation.<br />
<br />
===CAS and RAS Signals===<br />
<br />
Each 16MB or 8MB memory card for the KA650 uses one CAS line in its entirety. This is why a maximum of 4 cards may be used in a KA650 system. Each RAM card uses the first CAS line, and passes the remaining lines on to the next card, shifted down one bit. So for example, the first card gets CAS0 CAS1 CAS2 CAS3, in that order. It uses CAS0 and passes CAS1 CAS2 and CAS3 on to the next card, in that order. The next card uses CAS1 and passes on CAS2 and CAS3. This repeats until 4 cards have used up all of the available CAS lines.<br />
<br />
The CAS line is not gated in any way on the MS650-AA. The CAS line is simply buffered, inverted to match the polarity of the DRAMs, and distributed to all DRAMs on the card (likely with some hierarchical buffering methodology).<br />
<br />
===Refresh===<br />
<br />
DRAMs are built using one tiny MOS capacitor for each bit. These capacitors leak slightly and need to be periodically refreshed. DRAM rows are refreshed by simply addressing a row. Any row access refreshes that row, no column needs to be strobed for a refresh.<br />
<br />
As such, during refresh cycles, the CMCTL places a row address to be refreshed on the address bus, asserts SE, and asserts all RAS lines for several clock cycles. The purpose of the SE signal is so that RAM cards with 256kxX DRAMs do not gate any of the /RAS lines going to the DRAMs, or else only whatever DRAM bank is (randomly) addressed by XA20 and XA21 would be refreshed.<br />
<br />
===ECC===<br />
<br />
The ECC supported by the CMCTL, according to the KA650 technical manual, has the ability to detect and correct single data bit errors, detect single ECC bit errors, and detect double-bit data errors.<br />
<br />
ECC is generally based on producing parity bits of various collections of data bits. Since parity is based around the simple XOR, it is a linear operation in a manner of speaking. Luckily this means we can determine the ECC equations based on a number of sample data patterns and the respective ECC bits, such as the ECC produced for 0 data, and data with only one bit in the word set. By comparing the ECC for each test pattern to that of 0, we can determine which ECC bits each bit in the data word affects.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| bit || colspan=8 | data || ECC<br />
|-<br />
| || MSB || colspan = 6 | || LSB ||<br />
|-<br />
| - || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0111100<br />
|-<br />
| 0 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 1100100<br />
|-<br />
| 1 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0100000<br />
|-<br />
| 2 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0100110<br />
|-<br />
| 3 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 1100010<br />
|-<br />
| 4 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0100011<br />
|-<br />
| 5 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 1100111<br />
|-<br />
| 6 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 1100001<br />
|-<br />
| 7 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0100101<br />
|-<br />
| 8 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 1010100<br />
|-<br />
| 9 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0010000<br />
|-<br />
| 10 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0010110<br />
|-<br />
| 11 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 1010010<br />
|-<br />
| 12 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0010011<br />
|-<br />
| 13 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 1010111<br />
|-<br />
| 14 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 1010001<br />
|-<br />
| 15 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0010101<br />
|-<br />
| 16 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 1001100<br />
|-<br />
| 17 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0001000<br />
|-<br />
| 18 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0001110<br />
|-<br />
| 19 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 1001010<br />
|-<br />
| 20 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001011<br />
|-<br />
| 21 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001111<br />
|-<br />
| 22 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001001<br />
|-<br />
| 23 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001101<br />
|-<br />
| 24 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000100<br />
|-<br />
| 25 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000000<br />
|-<br />
| 26 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000110<br />
|-<br />
| 27 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000010<br />
|-<br />
| 28 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000011<br />
|-<br />
| 29 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000111<br />
|-<br />
| 30 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000001<br />
|-<br />
| 31 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000101<br />
|}<br />
<br />
<br />
The results of this are depicted below. The basic result is that toggling one of the bits that belongs to the ECC bit group will result in that ECC bit toggling as well.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| ECC bit || colspan=3 | MSB || colspan=26 | || colspan=3 | LSB<br />
|-<br />
|MD32<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|-<br />
|MD33<br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
|-<br />
|MD34<br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
|-<br />
|MD35<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD36<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD37<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|-<br />
|MD38<br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
|}<br />
<br />
An interesting and potentially useful point to note is that flipping bit 28 happens to flip all of the ECC bits together. Another interesting point is that inverting the entire data word produces the same ECC.<br />
<br />
From this information, we can derive some data patterns that produce useful ECC combinations, such as ECC of all zeroes, all ones, only one bit set, and only one bit clear. Looking at the table above, we got lucky and examples of many of these combinations were found by chance. In particular, we happened upon data combinations that produced every possibility of 1 ECC bit set. These, combined with the fact that we can toggle bit 28 to get the inverse ECC bits, gives us a set of data patterns which produce ECC with only one bit clear. From here, we only need to derive a combination which produces all-zero ECC, and from that, derive all-one ECC.<br />
<br />
Starting with the ECC for bit 31 set, we can toggle single bits at a time until we find a combination that produces the ECC we want.<br />
<nowiki><br />
31 1000 0000 0000 0000 0000 0000 0000 0000 1000101<br />
1000 0000 0000 0000 0000 0000 0000 0001 0011101<br />
1000 0000 0000 0000 0000 0010 0000 0001 0110001<br />
1000 0000 1000 0000 0000 0010 0000 0001 0000000 <--<br />
1001 0000 1000 0000 0000 0010 0000 0001 1111111 <--<br />
</nowiki><br />
<br />
The summary of these useful ECC combinations is tabulated below (data in hex, ECC in binary)<br />
<br />
useful ECC combinations:<br />
<br />
{| border=1 style="text-align:center"<br />
| ECC (binary) || data (hex)<br />
|-<br />
| 0000000 || 80800201<br />
|-<br />
| 0000001 || 40000000<br />
|-<br />
| 0000010 || 08000000<br />
|-<br />
| 0000100 || 01000000<br />
|-<br />
| 0001000 || 00020000<br />
|-<br />
| 0010000 || 00000200<br />
|-<br />
| 0100000 || 00000002<br />
|-<br />
| 1000000 || 02000000<br />
|-<br />
| 1111111 || 90800201<br />
|-<br />
| 1111110 || 50000000<br />
|-<br />
| 1111101 || 18000000<br />
|-<br />
| 1111011 || 11000000<br />
|-<br />
| 1110111 || 10020000<br />
|-<br />
| 1101111 || 10000200<br />
|-<br />
| 1011111 || 10000002<br />
|-<br />
| 0111111 || 12000000<br />
|}<br />
<br />
==KA650 VAX Firmware Memory Tests==<br />
<br />
Many of the tests built in to the firmware of the VAX can be quite thorough, if used properly. The tests can be accessed by the TEST command in the monitor, abbreviated to 't'.<br />
<br />
The tests report diagnostic information upon failure, encoded simply as a number of values in registers and memory locations on the stack. With the proper documentation, these values could be decoded to determine the problem. Lacking that documentation, I was able to reverse engineer enough of one test that was failing to understand it's output.<br />
<br />
===TEST 48: MEM_Addr_shrts===<br />
<br />
This test is normally used to check for shorted address lines. It will fill the memory with a pattern first, then it will check each word in order to see if it is still the same pattern. After checking a word, it will check the CMCTL status register to ensure there were no detected errors. Then it will replace the word with another pattern (usually mostly an inverse of the first pattern).<br />
<br />
If any address line is shorted, when the test writes the second pattern, it will affect another location in memory. When that location is encountered, it will read as the wrong data thus showing the issue. However, the test is also capable of detecting stuck bits the way it is designed, and this test happened to find all DRAM errors in my case.<br />
<br />
The output when the test encounters an error looks like the following:<br />
<br />
<nowiki><br />
>>>t 48<br />
<br />
<br />
?48 2 08 FF 00 0002<br />
<br />
P1=00000000 P2=04000000 P3=00000004 P4=00031000 P5=AAAAAAAA<br />
P6=55555555 P7=00000043 P8=200C5875 P9=00000000 P10=2005311F<br />
r0=45555555 r1=000C5860 r2=45555555 r3=00000004 r4=0000006B<br />
r5=AAAAAAAA r6=20080140 r7=20080144 r8=00000000 ERF=80000000<br />
<br />
Normal operation not possible.<br />
<br />
>>><br />
</nowiki><br />
<br />
I figured out the meaning of some of these registers for this test. First of all, P10 indicates an address where presumably DEC personnel would check a source listing to find out the exact meaning of the rest of the values shown. The meanings of the registers I have found are only valid for this routine, located near 2005311F.<br />
<br />
{| border=1 style="text-align:center"<br />
| register || description<br />
|-<br />
| r0 || contents of memory at address being tested<br />
|-<br />
| r1 || address being tested<br />
|-<br />
| r2 || expected pattern from memory being tested<br />
|-<br />
| r5 || pattern to replace location with<br />
|-<br />
| r6 || address of CMCTL MEMCSR16 (a diagnostic register)<br />
|-<br />
| P8 || contents of MEMCSR16<br />
|}<br />
<br />
==MEMCSR16 Register==<br />
<br />
The MEMCSR16 register gives us information on what kind of memory failure<br />
occurred. The bit meanings are as follows, according to the KA650 technical manual:<br />
<br />
{| border=1 style="text-align:center"<br />
| bits || description<br />
|-<br />
| <31> || set if uncorrectable error occurred<br />
|-<br />
| <30> || set if multiple uncorrectable errors occurred<br />
|-<br />
| <29> || set if correctable error occurred<br />
|-<br />
| <28:9> || page address where error occurred (pages are 512 bytes)<br />
|-<br />
| <8> || set if error ocurred during DMA<br />
|-<br />
| <7> || set if CDAL bus parity error occurred<br />
|-<br />
| <6:0> || error syndrome: a unique combination is produced here for each possible single bit error<br />
|}<br />
<br />
writing 1s to bits 31, 30, 29, 8, or 7 of MEMCSR16 resets those bits. bits 28:9 and 6:0 are read only.<br />
<br />
The MEMCSR registers can be read with test 9c.<br />
<br />
===Error Syndrome Field===<br />
<br />
The error syndrome is particularly useful for troubleshooting memory errors as it can tell us exactly which bit had the error. A list of the syndromes and the corresponding bit error is given below.<br />
<br />
{| border=1 style="text-align:center"<br />
| syndrome || bit position or error description<br />
|-<br />
| 0000000 || no error<br />
|-<br />
| 0000001 || 32<br />
|-<br />
| 0000010 || 33<br />
|-<br />
| 0000100 || 34<br />
|-<br />
| 0000111 || result of incorrect check bits written on CDAL parity error<br />
|-<br />
| 0001000 || 35<br />
|-<br />
| 0010000 || 36<br />
|-<br />
| 0011001 || 7<br />
|-<br />
| 0011010 || 2<br />
|-<br />
| 0011100 || 1<br />
|-<br />
| 0011111 || 4<br />
|-<br />
| 0100000 || 37<br />
|-<br />
| 0101001 || 15<br />
|-<br />
| 0101010 || 10<br />
|-<br />
| 0101100 || 9<br />
|-<br />
| 0101111 || 12<br />
|-<br />
| 0110001 || 23<br />
|-<br />
| 0110010 || 18<br />
|-<br />
| 0110100 || 17<br />
|-<br />
| 0110111 || 20<br />
|-<br />
| 0111000 || 24<br />
|-<br />
| 0111011 || 29<br />
|-<br />
| 0111101 || 30<br />
|-<br />
| 0111110 || 27<br />
|-<br />
| 1000000 || 38<br />
|-<br />
| 1011000 || 0<br />
|-<br />
| 1011011 || 5<br />
|-<br />
| 1011101 || 6<br />
|-<br />
| 1011110 || 3<br />
|-<br />
| 1101000 || 8<br />
|-<br />
| 1101011 || 13<br />
|-<br />
| 1101101 || 14<br />
|-<br />
| 1101110 || 11<br />
|-<br />
| 1110000 || 16<br />
|-<br />
| 1110011 || 21<br />
|-<br />
| 1110101 || 22<br />
|-<br />
| 1110110 || 19<br />
|-<br />
| 1111001 || 31<br />
|-<br />
| 1111010 || 26<br />
|-<br />
| 1111100 || 25<br />
|-<br />
| 1111111 || 28<br />
|-<br />
| other || multibit error<br />
|}<br />
<br />
==TROUBLESHOOTING==<br />
<br />
We now have all of the information necessary to narrow down which bits in which address regions are bad. However, that doesn't do any good for repair unless we also know which physical DRAMs that bit and region correspond to.<br />
<br />
===MS650-AA===<br />
<br />
Shown below is a diagram of the MS650-AA RAM card, broken up into 11 columns and 37 rows. Each spot in this grid contains up to 1 DRAM, but some locations contain other circuitry instead.<br />
<br />
<nowiki><br />
<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
--------------------------------------------------------------------------------<br />
01 | ooooooooooooooooooooooooo |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 01<br />
| --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
08 | --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 08<br />
|-------------------------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
09 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 09<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
16 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 16<br />
17 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 17<br />
18 |DDDDDDD|TTTTTTT TTTTTTTTT TTTTTTTT |DDDDDDDDDDDDD|TTTTTTTT TTTTTTTTT TTTTTTTT | 18<br />
19 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 19<br />
20 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 20<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
32 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 32<br />
33 |DDDDDDD-----------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 33<br />
36 |DDDDDDD| PPPPPPP TTTTT TTTTT |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 35<br />
37 |-------- TTTTTTT TTTTTTT --------DDDDDDDDDDDDDD-------DDDDDDDDDDDDDD| 37<br />
| -------------- --------------| <br />
| ___- - ___- |<br />
| | | || | | |<br />
-------------------- ----------------------------------------------------------<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
<br />
-----------------------------------------------<br />
| D DRAMS |<br />
| T TTL IC |<br />
| B some kind of DEC custom fast data buffer? |<br />
| P PAL16L8 |<br />
| o data connector |<br />
| | border |<br />
| - border |<br />
-----------------------------------------------<br />
<br />
</nowiki><br />
<br />
The MS650-AA RAM card uses two RAS lines. During normal initialization of the VAX, the rank connected to RAS0 will be first in memory, followed by the rank connected to RAS1. Presumably, the MS650-BA card would have 4 ranks.<br />
<br />
RAS0 - first 4MB<br />
RAS1 - second 4MB<br />
<br />
Based on the bit with the error, as well as the memory region where the error occurred, the specific DRAM with the failure can be found and replaced.<br />
<br />
Below is a list of the DRAMs sorted by memory region and bit, showing the grid location of the DRAM IC.<br />
<br />
By using the built in tests, along with MEMCSR16, and perhaps some manual DEPOSIT and EXAMINE testing, the bad DRAM should be possible to locate and then, using this table, the DRAM can be replaced.<br />
<br />
{| border=1 style="text-align:center"<br />
| DRAM || Address || data bit<br />
|-<br />
| A12 || 0XXXXX || MD00<br />
|-<br />
| A11 || 1XXXXX || MD00<br />
|-<br />
| A10 || 2XXXXX || MD00<br />
|-<br />
| A09 || 3XXXXX || MD00<br />
|-<br />
| A16 || 4XXXXX || MD00<br />
|-<br />
| A15 || 5XXXXX || MD00<br />
|-<br />
| A14 || 6XXXXX || MD00<br />
|-<br />
| A13 || 7XXXXX || MD00<br />
|-<br />
| A24 || 0XXXXX || MD01<br />
|-<br />
| A23 || 1XXXXX || MD01<br />
|-<br />
| A22 || 2XXXXX || MD01<br />
|-<br />
| A21 || 3XXXXX || MD01<br />
|-<br />
| A20 || 4XXXXX || MD01<br />
|-<br />
| A19 || 5XXXXX || MD01<br />
|-<br />
| A18 || 6XXXXX || MD01<br />
|-<br />
| A17 || 7XXXXX || MD01<br />
|-<br />
| A32 || 0XXXXX || MD02<br />
|-<br />
| A31 || 1XXXXX || MD02<br />
|-<br />
| A30 || 2XXXXX || MD02<br />
|-<br />
| A29 || 3XXXXX || MD02<br />
|-<br />
| A28 || 4XXXXX || MD02<br />
|-<br />
| A27 || 5XXXXX || MD02<br />
|-<br />
| A26 || 6XXXXX || MD02<br />
|-<br />
| A25 || 7XXXXX || MD02<br />
|-<br />
| B12 || 0XXXXX || MD03<br />
|-<br />
| B11 || 1XXXXX || MD03<br />
|-<br />
| B10 || 2XXXXX || MD03<br />
|-<br />
| B09 || 3XXXXX || MD03<br />
|-<br />
| A36 || 4XXXXX || MD03<br />
|-<br />
| A35 || 5XXXXX || MD03<br />
|-<br />
| A34 || 6XXXXX || MD03<br />
|-<br />
| A33 || 7XXXXX || MD03<br />
|-<br />
| B24 || 0XXXXX || MD04<br />
|-<br />
| B23 || 1XXXXX || MD04<br />
|-<br />
| B22 || 2XXXXX || MD04<br />
|-<br />
| B21 || 3XXXXX || MD04<br />
|-<br />
| B16 || 4XXXXX || MD04<br />
|-<br />
| B15 || 5XXXXX || MD04<br />
|-<br />
| B14 || 6XXXXX || MD04<br />
|-<br />
| B13 || 7XXXXX || MD04<br />
|-<br />
| B32 || 0XXXXX || MD05<br />
|-<br />
| B31 || 1XXXXX || MD05<br />
|-<br />
| B30 || 2XXXXX || MD05<br />
|-<br />
| B29 || 3XXXXX || MD05<br />
|-<br />
| B28 || 4XXXXX || MD05<br />
|-<br />
| B27 || 5XXXXX || MD05<br />
|-<br />
| B26 || 6XXXXX || MD05<br />
|-<br />
| B25 || 7XXXXX || MD05<br />
|-<br />
| C12 || 0XXXXX || MD06<br />
|-<br />
| C11 || 1XXXXX || MD06<br />
|-<br />
| C10 || 2XXXXX || MD06<br />
|-<br />
| C09 || 3XXXXX || MD06<br />
|-<br />
| C16 || 4XXXXX || MD06<br />
|-<br />
| C15 || 5XXXXX || MD06<br />
|-<br />
| C14 || 6XXXXX || MD06<br />
|-<br />
| C13 || 7XXXXX || MD06<br />
|-<br />
| C24 || 0XXXXX || MD07<br />
|-<br />
| C23 || 1XXXXX || MD07<br />
|-<br />
| C22 || 2XXXXX || MD07<br />
|-<br />
| C21 || 3XXXXX || MD07<br />
|-<br />
| E20 || 4XXXXX || MD07<br />
|-<br />
| D20 || 5XXXXX || MD07<br />
|-<br />
| C20 || 6XXXXX || MD07<br />
|-<br />
| B20 || 7XXXXX || MD07<br />
|-<br />
| C32 || 0XXXXX || MD08<br />
|-<br />
| C31 || 1XXXXX || MD08<br />
|-<br />
| C30 || 2XXXXX || MD08<br />
|-<br />
| C29 || 3XXXXX || MD08<br />
|-<br />
| C28 || 4XXXXX || MD08<br />
|-<br />
| C27 || 5XXXXX || MD08<br />
|-<br />
| C26 || 6XXXXX || MD08<br />
|-<br />
| C25 || 7XXXXX || MD08<br />
|-<br />
| D32 || 0XXXXX || MD09<br />
|-<br />
| D31 || 1XXXXX || MD09<br />
|-<br />
| D30 || 2XXXXX || MD09<br />
|-<br />
| D29 || 3XXXXX || MD09<br />
|-<br />
| D28 || 4XXXXX || MD09<br />
|-<br />
| D27 || 5XXXXX || MD09<br />
|-<br />
| D26 || 6XXXXX || MD09<br />
|-<br />
| D25 || 7XXXXX || MD09<br />
|-<br />
| D24 || 0XXXXX || MD10<br />
|-<br />
| D23 || 1XXXXX || MD10<br />
|-<br />
| D22 || 2XXXXX || MD10<br />
|-<br />
| D21 || 3XXXXX || MD10<br />
|-<br />
| D16 || 4XXXXX || MD10<br />
|-<br />
| D15 || 5XXXXX || MD10<br />
|-<br />
| D14 || 6XXXXX || MD10<br />
|-<br />
| D13 || 7XXXXX || MD10<br />
|-<br />
| D12 || 0XXXXX || MD11<br />
|-<br />
| D11 || 1XXXXX || MD11<br />
|-<br />
| D10 || 2XXXXX || MD11<br />
|-<br />
| D09 || 3XXXXX || MD11<br />
|-<br />
| E16 || 4XXXXX || MD11<br />
|-<br />
| E15 || 5XXXXX || MD11<br />
|-<br />
| E14 || 6XXXXX || MD11<br />
|-<br />
| E13 || 7XXXXX || MD11<br />
|-<br />
| E12 || 0XXXXX || MD12<br />
|-<br />
| E11 || 1XXXXX || MD12<br />
|-<br />
| E10 || 2XXXXX || MD12<br />
|-<br />
| E09 || 3XXXXX || MD12<br />
|-<br />
| E28 || 4XXXXX || MD12<br />
|-<br />
| E27 || 5XXXXX || MD12<br />
|-<br />
| E26 || 6XXXXX || MD12<br />
|-<br />
| E25 || 7XXXXX || MD12<br />
|-<br />
| E24 || 0XXXXX || MD13<br />
|-<br />
| E23 || 1XXXXX || MD13<br />
|-<br />
| E22 || 2XXXXX || MD13<br />
|-<br />
| E21 || 3XXXXX || MD13<br />
|-<br />
| F16 || 4XXXXX || MD13<br />
|-<br />
| F15 || 5XXXXX || MD13<br />
|-<br />
| F14 || 6XXXXX || MD13<br />
|-<br />
| F13 || 7XXXXX || MD13<br />
|-<br />
| E32 || 0XXXXX || MD14<br />
|-<br />
| E31 || 1XXXXX || MD14<br />
|-<br />
| E30 || 2XXXXX || MD14<br />
|-<br />
| E29 || 3XXXXX || MD14<br />
|-<br />
| F20 || 4XXXXX || MD14<br />
|-<br />
| F19 || 5XXXXX || MD14<br />
|-<br />
| F18 || 6XXXXX || MD14<br />
|-<br />
| F17 || 7XXXXX || MD14<br />
|-<br />
| F32 || 0XXXXX || MD15<br />
|-<br />
| F31 || 1XXXXX || MD15<br />
|-<br />
| F30 || 2XXXXX || MD15<br />
|-<br />
| F29 || 3XXXXX || MD15<br />
|-<br />
| F28 || 4XXXXX || MD15<br />
|-<br />
| F27 || 5XXXXX || MD15<br />
|-<br />
| F26 || 6XXXXX || MD15<br />
|-<br />
| F25 || 7XXXXX || MD15<br />
|-<br />
| F24 || 0XXXXX || MD16<br />
|-<br />
| F23 || 1XXXXX || MD16<br />
|-<br />
| F22 || 2XXXXX || MD16<br />
|-<br />
| F21 || 3XXXXX || MD16<br />
|-<br />
| F36 || 4XXXXX || MD16<br />
|-<br />
| F35 || 5XXXXX || MD16<br />
|-<br />
| F34 || 6XXXXX || MD16<br />
|-<br />
| F33 || 7XXXXX || MD16<br />
|-<br />
| G32 || 0XXXXX || MD17<br />
|-<br />
| G31 || 1XXXXX || MD17<br />
|-<br />
| G30 || 2XXXXX || MD17<br />
|-<br />
| G29 || 3XXXXX || MD17<br />
|-<br />
| G36 || 4XXXXX || MD17<br />
|-<br />
| G35 || 5XXXXX || MD17<br />
|-<br />
| G34 || 6XXXXX || MD17<br />
|-<br />
| G33 || 7XXXXX || MD17<br />
|-<br />
| G24 || 0XXXXX || MD18<br />
|-<br />
| G23 || 1XXXXX || MD18<br />
|-<br />
| G22 || 2XXXXX || MD18<br />
|-<br />
| G21 || 3XXXXX || MD18<br />
|-<br />
| G28 || 4XXXXX || MD18<br />
|-<br />
| G27 || 5XXXXX || MD18<br />
|-<br />
| G26 || 6XXXXX || MD18<br />
|-<br />
| G25 || 7XXXXX || MD18<br />
|-<br />
| H32 || 0XXXXX || MD19<br />
|-<br />
| H31 || 1XXXXX || MD19<br />
|-<br />
| H30 || 2XXXXX || MD19<br />
|-<br />
| H29 || 3XXXXX || MD19<br />
|-<br />
| G20 || 4XXXXX || MD19<br />
|-<br />
| G19 || 5XXXXX || MD19<br />
|-<br />
| G18 || 6XXXXX || MD19<br />
|-<br />
| G17 || 7XXXXX || MD19<br />
|-<br />
| H24 || 0XXXXX || MD20<br />
|-<br />
| H23 || 1XXXXX || MD20<br />
|-<br />
| H22 || 2XXXXX || MD20<br />
|-<br />
| H21 || 3XXXXX || MD20<br />
|-<br />
| K37 || 4XXXXX || MD20<br />
|-<br />
| J37 || 5XXXXX || MD20<br />
|-<br />
| H37 || 6XXXXX || MD20<br />
|-<br />
| G37 || 7XXXXX || MD20<br />
|-<br />
| I32 || 0XXXXX || MD21<br />
|-<br />
| I31 || 1XXXXX || MD21<br />
|-<br />
| I30 || 2XXXXX || MD21<br />
|-<br />
| I29 || 3XXXXX || MD21<br />
|-<br />
| H36 || 4XXXXX || MD21<br />
|-<br />
| H35 || 5XXXXX || MD21<br />
|-<br />
| H34 || 6XXXXX || MD21<br />
|-<br />
| H33 || 7XXXXX || MD21<br />
|-<br />
| I24 || 0XXXXX || MD22<br />
|-<br />
| I23 || 1XXXXX || MD22<br />
|-<br />
| I22 || 2XXXXX || MD22<br />
|-<br />
| I21 || 3XXXXX || MD22<br />
|-<br />
| H28 || 4XXXXX || MD22<br />
|-<br />
| H27 || 5XXXXX || MD22<br />
|-<br />
| H26 || 6XXXXX || MD22<br />
|-<br />
| H25 || 7XXXXX || MD22<br />
|-<br />
| J32 || 0XXXXX || MD23<br />
|-<br />
| J31 || 1XXXXX || MD23<br />
|-<br />
| J30 || 2XXXXX || MD23<br />
|-<br />
| J29 || 3XXXXX || MD23<br />
|-<br />
| I36 || 4XXXXX || MD23<br />
|-<br />
| I35 || 5XXXXX || MD23<br />
|-<br />
| I34 || 6XXXXX || MD23<br />
|-<br />
| I33 || 7XXXXX || MD23<br />
|-<br />
| J24 || 0XXXXX || MD24<br />
|-<br />
| J23 || 1XXXXX || MD24<br />
|-<br />
| J22 || 2XXXXX || MD24<br />
|-<br />
| J21 || 3XXXXX || MD24<br />
|-<br />
| I28 || 4XXXXX || MD24<br />
|-<br />
| I27 || 5XXXXX || MD24<br />
|-<br />
| I26 || 6XXXXX || MD24<br />
|-<br />
| I25 || 7XXXXX || MD24<br />
|-<br />
| K32 || 0XXXXX || MD25<br />
|-<br />
| K31 || 1XXXXX || MD25<br />
|-<br />
| K30 || 2XXXXX || MD25<br />
|-<br />
| K29 || 3XXXXX || MD25<br />
|-<br />
| J36 || 4XXXXX || MD25<br />
|-<br />
| J35 || 5XXXXX || MD25<br />
|-<br />
| J34 || 6XXXXX || MD25<br />
|-<br />
| J33 || 7XXXXX || MD25<br />
|-<br />
| K24 || 0XXXXX || MD26<br />
|-<br />
| K23 || 1XXXXX || MD26<br />
|-<br />
| K22 || 2XXXXX || MD26<br />
|-<br />
| K21 || 3XXXXX || MD26<br />
|-<br />
| J28 || 4XXXXX || MD26<br />
|-<br />
| J27 || 5XXXXX || MD26<br />
|-<br />
| J26 || 6XXXXX || MD26<br />
|-<br />
| J25 || 7XXXXX || MD26<br />
|-<br />
| K20 || 0XXXXX || MD27<br />
|-<br />
| J20 || 1XXXXX || MD27<br />
|-<br />
| I20 || 2XXXXX || MD27<br />
|-<br />
| H20 || 3XXXXX || MD27<br />
|-<br />
| K36 || 4XXXXX || MD27<br />
|-<br />
| K35 || 5XXXXX || MD27<br />
|-<br />
| K34 || 6XXXXX || MD27<br />
|-<br />
| K33 || 7XXXXX || MD27<br />
|-<br />
| F12 || 0XXXXX || MD28<br />
|-<br />
| F11 || 1XXXXX || MD28<br />
|-<br />
| F10 || 2XXXXX || MD28<br />
|-<br />
| F09 || 3XXXXX || MD28<br />
|-<br />
| K28 || 4XXXXX || MD28<br />
|-<br />
| K26 || 6XXXXX || MD28<br />
|-<br />
| K27 || 5XXXXX || MD28<br />
|-<br />
| K25 || 7XXXXX || MD28<br />
|-<br />
| G12 || 0XXXXX || MD29<br />
|-<br />
| G11 || 1XXXXX || MD29<br />
|-<br />
| G10 || 2XXXXX || MD29<br />
|-<br />
| G09 || 3XXXXX || MD29<br />
|-<br />
| G16 || 4XXXXX || MD29<br />
|-<br />
| G15 || 5XXXXX || MD29<br />
|-<br />
| G14 || 6XXXXX || MD29<br />
|-<br />
| G13 || 7XXXXX || MD29<br />
|-<br />
| G04 || 0XXXXX || MD30<br />
|-<br />
| G03 || 1XXXXX || MD30<br />
|-<br />
| G02 || 2XXXXX || MD30<br />
|-<br />
| G01 || 3XXXXX || MD30<br />
|-<br />
| G08 || 4XXXXX || MD30<br />
|-<br />
| G07 || 5XXXXX || MD30<br />
|-<br />
| G06 || 6XXXXX || MD30<br />
|-<br />
| G05 || 7XXXXX || MD30<br />
|-<br />
| H04 || 0XXXXX || MD31<br />
|-<br />
| H03 || 1XXXXX || MD31<br />
|-<br />
| H02 || 2XXXXX || MD31<br />
|-<br />
| H01 || 3XXXXX || MD31<br />
|-<br />
| H08 || 4XXXXX || MD31<br />
|-<br />
| H07 || 5XXXXX || MD31<br />
|-<br />
| H06 || 6XXXXX || MD31<br />
|-<br />
| H05 || 7XXXXX || MD31<br />
|-<br />
| H12 || 0XXXXX || MD32<br />
|-<br />
| H11 || 1XXXXX || MD32<br />
|-<br />
| H10 || 2XXXXX || MD32<br />
|-<br />
| H09 || 3XXXXX || MD32<br />
|-<br />
| H16 || 4XXXXX || MD32<br />
|-<br />
| H15 || 5XXXXX || MD32<br />
|-<br />
| H14 || 6XXXXX || MD32<br />
|-<br />
| H13 || 7XXXXX || MD32<br />
|-<br />
| I04 || 0XXXXX || MD33<br />
|-<br />
| I03 || 1XXXXX || MD33<br />
|-<br />
| I02 || 2XXXXX || MD33<br />
|-<br />
| I01 || 3XXXXX || MD33<br />
|-<br />
| I08 || 4XXXXX || MD33<br />
|-<br />
| I07 || 5XXXXX || MD33<br />
|-<br />
| I06 || 6XXXXX || MD33<br />
|-<br />
| I05 || 7XXXXX || MD33<br />
|-<br />
| I12 || 0XXXXX || MD34<br />
|-<br />
| I11 || 1XXXXX || MD34<br />
|-<br />
| I10 || 2XXXXX || MD34<br />
|-<br />
| I09 || 3XXXXX || MD34<br />
|-<br />
| I16 || 4XXXXX || MD34<br />
|-<br />
| I15 || 5XXXXX || MD34<br />
|-<br />
| I14 || 6XXXXX || MD34<br />
|-<br />
| I13 || 7XXXXX || MD34<br />
|-<br />
| J04 || 0XXXXX || MD35<br />
|-<br />
| J03 || 1XXXXX || MD35<br />
|-<br />
| J02 || 2XXXXX || MD35<br />
|-<br />
| J01 || 3XXXXX || MD35<br />
|-<br />
| J08 || 4XXXXX || MD35<br />
|-<br />
| J07 || 5XXXXX || MD35<br />
|-<br />
| J06 || 6XXXXX || MD35<br />
|-<br />
| J05 || 7XXXXX || MD35<br />
|-<br />
| J12 || 0XXXXX || MD36<br />
|-<br />
| J11 || 1XXXXX || MD36<br />
|-<br />
| J10 || 2XXXXX || MD36<br />
|-<br />
| J09 || 3XXXXX || MD36<br />
|-<br />
| J16 || 4XXXXX || MD36<br />
|-<br />
| J15 || 5XXXXX || MD36<br />
|-<br />
| J14 || 6XXXXX || MD36<br />
|-<br />
| J13 || 7XXXXX || MD36<br />
|-<br />
| K04 || 0XXXXX || MD37<br />
|-<br />
| K03 || 1XXXXX || MD37<br />
|-<br />
| K02 || 2XXXXX || MD37<br />
|-<br />
| K01 || 3XXXXX || MD37<br />
|-<br />
| K08 || 4XXXXX || MD37<br />
|-<br />
| K07 || 5XXXXX || MD37<br />
|-<br />
| K06 || 6XXXXX || MD37<br />
|-<br />
| K05 || 7XXXXX || MD37<br />
|-<br />
| K12 || 0XXXXX || MD38<br />
|-<br />
| K11 || 1XXXXX || MD38<br />
|-<br />
| K10 || 2XXXXX || MD38<br />
|-<br />
| K09 || 3XXXXX || MD38<br />
|-<br />
| K16 || 4XXXXX || MD38<br />
|-<br />
| K15 || 5XXXXX || MD38<br />
|-<br />
| K14 || 6XXXXX || MD38<br />
|-<br />
| K13 || 7XXXXX || MD38<br />
|}<br />
<br />
===MS650-BA===<br />
<br />
Because I did not have an MS650-BA to test, I do not have as much information on this module as on the MS650-AA. Presumably, the MS650-BA has 4 ranks of 4MB in 1MBxX DRAMs, meaning there is no need to have 4 banks in each rank like the 256kx1 DRAMs on the MS650-AA.</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_Main_Memory_System&diff=21854
KA650 Main Memory System
2019-11-24T04:15:48Z
<p>Jzatarski: mostly cleaned up/reformatted. Table at bottom needs some more work</p>
<hr />
<div>This page contains notes on troubleshooting, repair, and theory of operation of the DEC KA650/MS650 memory subsystem.<br />
<br />
==Overview==<br />
<br />
The MS650-AA and MS650-BA memory module are intended to be used with the DEC KA650 VAX CPU, as the name might suggest. These quad width cards contain 8MB and 16MB of RAM for the VAX, respectively, complete with ECC.<br />
<br />
==Theory of Operation==<br />
<br />
===Memory Controller General Architecture and Organization===<br />
<br />
====Memory Control Signals Provided by the CMCTL====<br />
The CMCTL IC is the DRAM controller for the KA650 CPU. It has 10 address line outputs, 39 memory data I/O (MD), 4 CAS outputs, 4 RAS outputs, a WE pin, and an SE pin. Also available to the RAM card are the inverse of the 20th and 21st address lines (XA20 & XA21), which are used as bank selection when using 256kxX DRAMs. The data lines are provided to the RAM cards through a 50 conductor ribbon cable, while the rest of the control lines are provided through the CD interconnect on the backplane.<br />
<br />
The 10 address lines carry the row address on the rising edge of a RAS line, followed by the column address on the rising edge of a CAS line.<br />
<br />
The 39 data I/O carry the 32 data and 7 ECC bits for the RAM.<br />
<br />
The 4 CAS (Column Address Strobe) lines allow strobing the column address on up to 4 separate memory modules.<br />
<br />
The 4 RAS (Row Address Strobe) lines allow selection of up to 4 banks on a single memory module.<br />
<br />
The WE (Write Enable) pin indicates that the CMCTL is writing to memory, rather than reading.<br />
<br />
The SE (Strobe Enable?) pin seems to indicate that the CMCTL is refreshing memory. This is necessary for the 8MB card to correctly strobe the RAS lines of each rank during a refresh cycle, due to the extra RAS gating circuitry necessary on cards with 256kxX DRAMs.<br />
<br />
The XA20 and XA21 lines are the inverse of the latched address lines from the CDAL bus.<br />
<br />
Note that many of the above control lines are inverse logic from what is normally used to drive DRAMs; in particular, CAS, RAS, and WE lines are inverted from the normal JEDEC DRAM convention of active low /RAS, /CAS, and /WE.<br />
<br />
====Memory Ranks & Banks====<br />
<br />
Due to the 10 bit address bus using conventional multiplexed row and column DRAM addressing, an effective 20 bit address is formed. This allows the CMCTL to address up to 1MWord per rank.<br />
<br />
By strobing different pairings of RAS and CAS (RAS0+CAS0 is one rank, while RAS0+CAS1 is another rank, while RAS1+CAS0 is yet another rank), the CMCTL supports up to 16 ranks of RAM, each 1Mx39. Each rank is thus 4MB of memory once ECC overhead is accounted for. This puts a 64MB cap on the maximum amount of memory the CMCTL can address (16 ranks of 4MB).<br />
<br />
When 256kxX DRAMs are used in place of 1MxX DRAMs, each 1Mx39 rank is further divided into 4 banks of 256kx39. Each bank is selected by XA20 and XA21, which are provided to the RAM cards via the CD interconnect. These address bits appear to only be valid on the rising edge of RAS. Before CAS has strobed, the bits have generally already changed since these are derived from the CDAL bus of the VAX CPU. These bits are used to gate the /RAS lines to the DRAMs ensuring that only the selected bank is addressed. The /CAS line for the card is not affected.<br />
<br />
The MS650-AA card contains 312 256kx1 ZIP DRAMs, organized into 8 banks of 256kx39. As previously mentioned, one memory rank as addressed by the CMCTL memory controller consists of 4 banks, making up a total of 1MWord of memory per rank. Each DRAM on the card corresponds to one bit of the 39 bit word within a 1MB address region of the VAX.<br />
<br />
===Addressing===<br />
<br />
The CMCTL appears to convert 32 bit VAX addresses into DRAM addressing as follows:<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
| A21 || A20 || A19 || A18 || A17 || A16 || A15 || A14 || A13 || A12 || A11 || A10 || A09 || A08 || A07 || A06 || A05 || A04 || A03 || A02<br />
|-<br />
| width=2.5% | R09 <br />
| width=2.5% | <br />
| width=2.5% | R08<br />
| width=2.5% | R07<br />
| width=2.5% | R06<br />
| width=2.5% | R05<br />
| width=2.5% | R04<br />
| width=2.5% | R03<br />
| width=2.5% | R02<br />
| width=2.5% | R01<br />
| width=2.5% | R00<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
| width=2.5% |<br />
|-<br />
| width=2.5% | <br />
| width=2.5% | C09<br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | <br />
| width=2.5% | C08<br />
| width=2.5% | C07<br />
| width=2.5% | C06<br />
| width=2.5% | C05<br />
| width=2.5% | C04<br />
| width=2.5% | C03<br />
| width=2.5% | C02<br />
| width=2.5% | C01<br />
| width=2.5% | C00<br />
|}<br />
<br />
Axx are VAX address lines<br />
Rxx are DRAM row address bits<br />
Cxx are DRAM column address bits<br />
<br />
This addressing scheme is used to ensure that 256kxX DRAMs (which use only 9 bit row and column addresses) are still supported for use with the CMCTL.<br />
<br />
It is, of course, still up to the CMCTL to determine which ranks are selected by the upper bits of a given physical address. This is determined by the MEMCSR0-15 registers, which seem to specify whether or not a bank is present, as well as what base address it resides at. It may perform other functions, but it does not seem to be documented in available documentation.<br />
<br />
===CAS and RAS Signals===<br />
<br />
Each 16MB or 8MB memory card for the KA650 uses one CAS line in its entirety. This is why a maximum of 4 cards may be used in a KA650 system. Each RAM card uses the first CAS line, and passes the remaining lines on to the next card, shifted down one bit. So for example, the first card gets CAS0 CAS1 CAS2 CAS3, in that order. It uses CAS0 and passes CAS1 CAS2 and CAS3 on to the next card, in that order. The next card uses CAS1 and passes on CAS2 and CAS3. This repeats until 4 cards have used up all of the available CAS lines.<br />
<br />
The CAS line is not gated in any way on the MS650-AA. The CAS line is simply buffered, inverted to match the polarity of the DRAMs, and distributed to all DRAMs on the card (likely with some hierarchical buffering methodology).<br />
<br />
===Refresh===<br />
<br />
DRAMs are built using one tiny MOS capacitor for each bit. These capacitors leak slightly and need to be periodically refreshed. DRAM rows are refreshed by simply addressing a row. Any row access refreshes that row, no column needs to be strobed for a refresh.<br />
<br />
As such, during refresh cycles, the CMCTL places a row address to be refreshed on the address bus, asserts SE, and asserts all RAS lines for several clock cycles. The purpose of the SE signal is so that RAM cards with 256kxX DRAMs do not gate any of the /RAS lines going to the DRAMs, or else only whatever DRAM bank is (randomly) addressed by XA20 and XA21 would be refreshed.<br />
<br />
===ECC===<br />
<br />
The ECC supported by the CMCTL, according to the KA650 technical manual, has the ability to detect and correct single data bit errors, detect single ECC bit errors, and detect double-bit data errors.<br />
<br />
ECC is generally based on producing parity bits of various collections of data bits. Since parity is based around the simple XOR, it is a linear operation in a manner of speaking. Luckily this means we can determine the ECC equations based on a number of sample data patterns and the respective ECC bits, such as the ECC produced for 0 data, and data with only one bit in the word set. By comparing the ECC for each test pattern to that of 0, we can determine which ECC bits each bit in the data word affects.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| bit || colspan=8 | data || ECC<br />
|-<br />
| || MSB || colspan = 6 | || LSB ||<br />
|-<br />
| - || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0111100<br />
|-<br />
| 0 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 1100100<br />
|-<br />
| 1 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0100000<br />
|-<br />
| 2 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0100110<br />
|-<br />
| 3 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 1100010<br />
|-<br />
| 4 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0100011<br />
|-<br />
| 5 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 1100111<br />
|-<br />
| 6 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 1100001<br />
|-<br />
| 7 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0100101<br />
|-<br />
| 8 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 1010100<br />
|-<br />
| 9 || 0000 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0010000<br />
|-<br />
| 10 || 0000 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0010110<br />
|-<br />
| 11 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 1010010<br />
|-<br />
| 12 || 0000 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0010011<br />
|-<br />
| 13 || 0000 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 1010111<br />
|-<br />
| 14 || 0000 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 1010001<br />
|-<br />
| 15 || 0000 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0010101<br />
|-<br />
| 16 || 0000 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 1001100<br />
|-<br />
| 17 || 0000 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0001000<br />
|-<br />
| 18 || 0000 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0001110<br />
|-<br />
| 19 || 0000 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 1001010<br />
|-<br />
| 20 || 0000 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001011<br />
|-<br />
| 21 || 0000 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001111<br />
|-<br />
| 22 || 0000 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 1001001<br />
|-<br />
| 23 || 0000 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0001101<br />
|-<br />
| 24 || 0000 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000100<br />
|-<br />
| 25 || 0000 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000000<br />
|-<br />
| 26 || 0000 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000110<br />
|-<br />
| 27 || 0000 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000010<br />
|-<br />
| 28 || 0001 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000011<br />
|-<br />
| 29 || 0010 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000111<br />
|-<br />
| 30 || 0100 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000001<br />
|-<br />
| 31 || 1000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 0000 || 1000101<br />
|}<br />
<br />
<br />
The results of this are depicted below. The basic result is that toggling one of the bits that belongs to the ECC bit group will result in that ECC bit toggling as well.<br />
<br />
{| border=1 width=90% style="text-align:center"<br />
|| ECC bit || colspan=3 | MSB || colspan=26 | || colspan=3 | LSB<br />
|-<br />
|MD32<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|| || || || <br />
|-<br />
|MD33<br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
| || ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| || <br />
|-<br />
|MD34<br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X|| ||style="background-color: #FFFF00;"|X|| <br />
|-<br />
|MD35<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD36<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|-<br />
|MD37<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
|style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X<br />
| || || || <br />
| || || || <br />
|-<br />
|MD38<br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
| ||style="background-color: #FFFF00;"|X||style="background-color: #FFFF00;"|X|| <br />
|style="background-color: #FFFF00;"|X|| || ||style="background-color: #FFFF00;"|X<br />
|}<br />
<br />
An interesting and potentially useful point to note is that flipping bit 28 happens to flip all of the ECC bits together. Another interesting point is that inverting the entire data word produces the same ECC.<br />
<br />
From this information, we can derive some data patterns that produce useful ECC combinations, such as ECC of all zeroes, all ones, only one bit set, and only one bit clear. Looking at the table above, we got lucky and examples of many of these combinations were found by chance. In particular, we happened upon data combinations that produced every possibility of 1 ECC bit set. These, combined with the fact that we can toggle bit 28 to get the inverse ECC bits, gives us a set of data patterns which produce ECC with only one bit clear. From here, we only need to derive a combination which produces all-zero ECC, and from that, derive all-one ECC.<br />
<br />
Starting with the ECC for bit 31 set, we can toggle single bits at a time until we find a combination that produces the ECC we want.<br />
<nowiki><br />
31 1000 0000 0000 0000 0000 0000 0000 0000 1000101<br />
1000 0000 0000 0000 0000 0000 0000 0001 0011101<br />
1000 0000 0000 0000 0000 0010 0000 0001 0110001<br />
1000 0000 1000 0000 0000 0010 0000 0001 0000000 <--<br />
1001 0000 1000 0000 0000 0010 0000 0001 1111111 <--<br />
</nowiki><br />
<br />
The summary of these useful ECC combinations is tabulated below (data in hex, ECC in binary)<br />
<br />
useful ECC combinations:<br />
<br />
{| border=1 style="text-align:center"<br />
| ECC (binary) || data (hex)<br />
|-<br />
| 0000000 || 80800201<br />
|-<br />
| 0000001 || 40000000<br />
|-<br />
| 0000010 || 08000000<br />
|-<br />
| 0000100 || 01000000<br />
|-<br />
| 0001000 || 00020000<br />
|-<br />
| 0010000 || 00000200<br />
|-<br />
| 0100000 || 00000002<br />
|-<br />
| 1000000 || 02000000<br />
|-<br />
| 1111111 || 90800201<br />
|-<br />
| 1111110 || 50000000<br />
|-<br />
| 1111101 || 18000000<br />
|-<br />
| 1111011 || 11000000<br />
|-<br />
| 1110111 || 10020000<br />
|-<br />
| 1101111 || 10000200<br />
|-<br />
| 1011111 || 10000002<br />
|-<br />
| 0111111 || 12000000<br />
|}<br />
<br />
==KA650 VAX Firmware Memory Tests==<br />
<br />
Many of the tests built in to the firmware of the VAX can be quite thorough, if used properly. The tests can be accessed by the TEST command in the monitor, abbreviated to 't'.<br />
<br />
The tests report diagnostic information upon failure, encoded simply as a number of values in registers and memory locations on the stack. With the proper documentation, these values could be decoded to determine the problem. Lacking that documentation, I was able to reverse engineer enough of one test that was failing to understand it's output.<br />
<br />
===TEST 48: MEM_Addr_shrts===<br />
<br />
This test is normally used to check for shorted address lines. It will fill the memory with a pattern first, then it will check each word in order to see if it is still the same pattern. After checking a word, it will check the CMCTL status register to ensure there were no detected errors. Then it will replace the word with another pattern (usually mostly an inverse of the first pattern).<br />
<br />
If any address line is shorted, when the test writes the second pattern, it will affect another location in memory. When that location is encountered, it will read as the wrong data thus showing the issue. However, the test is also capable of detecting stuck bits the way it is designed, and this test happened to find all DRAM errors in my case.<br />
<br />
The output when the test encounters an error looks like the following:<br />
<br />
<nowiki><br />
>>>t 48<br />
<br />
<br />
?48 2 08 FF 00 0002<br />
<br />
P1=00000000 P2=04000000 P3=00000004 P4=00031000 P5=AAAAAAAA<br />
P6=55555555 P7=00000043 P8=200C5875 P9=00000000 P10=2005311F<br />
r0=45555555 r1=000C5860 r2=45555555 r3=00000004 r4=0000006B<br />
r5=AAAAAAAA r6=20080140 r7=20080144 r8=00000000 ERF=80000000<br />
<br />
Normal operation not possible.<br />
<br />
>>><br />
</nowiki><br />
<br />
I figured out the meaning of some of these registers for this test. First of all, P10 indicates an address where presumably DEC personnel would check a source listing to find out the exact meaning of the rest of the values shown. The meanings of the registers I have found are only valid for this routine, located near 2005311F.<br />
<br />
{| border=1 style="text-align:center"<br />
| register || description<br />
|-<br />
| r0 || contents of memory at address being tested<br />
|-<br />
| r1 || address being tested<br />
|-<br />
| r2 || expected pattern from memory being tested<br />
|-<br />
| r5 || pattern to replace location with<br />
|-<br />
| r6 || address of CMCTL MEMCSR16 (a diagnostic register)<br />
|-<br />
| P8 || contents of MEMCSR16<br />
|}<br />
<br />
==MEMCSR16 Register==<br />
<br />
The MEMCSR16 register gives us information on what kind of memory failure<br />
occurred. The bit meanings are as follows, according to the KA650 technical manual:<br />
<br />
{| border=1 style="text-align:center"<br />
| bits || description<br />
|-<br />
| <31> || set if uncorrectable error occurred<br />
|-<br />
| <30> || set if multiple uncorrectable errors occurred<br />
|-<br />
| <29> || set if correctable error occurred<br />
|-<br />
| <28:9> || page address where error occurred (pages are 512 bytes)<br />
|-<br />
| <8> || set if error ocurred during DMA<br />
|-<br />
| <7> || set if CDAL bus parity error occurred<br />
|-<br />
| <6:0> || error syndrome: a unique combination is produced here for each possible single bit error<br />
|}<br />
<br />
writing 1s to bits 31, 30, 29, 8, or 7 of MEMCSR16 resets those bits. bits 28:9 and 6:0 are read only.<br />
<br />
The MEMCSR registers can be read with test 9c.<br />
<br />
===Error Syndrome Field===<br />
<br />
The error syndrome is particularly useful for troubleshooting memory errors as it can tell us exactly which bit had the error. A list of the syndromes and the corresponding bit error is given below.<br />
<br />
{| border=1 style="text-align:center"<br />
| syndrome || bit position or error description<br />
|-<br />
| 0000000 || no error<br />
|-<br />
| 0000001 || 32<br />
|-<br />
| 0000010 || 33<br />
|-<br />
| 0000100 || 34<br />
|-<br />
| 0000111 || result of incorrect check bits written on CDAL parity error<br />
|-<br />
| 0001000 || 35<br />
|-<br />
| 0010000 || 36<br />
|-<br />
| 0011001 || 7<br />
|-<br />
| 0011010 || 2<br />
|-<br />
| 0011100 || 1<br />
|-<br />
| 0011111 || 4<br />
|-<br />
| 0100000 || 37<br />
|-<br />
| 0101001 || 15<br />
|-<br />
| 0101010 || 10<br />
|-<br />
| 0101100 || 9<br />
|-<br />
| 0101111 || 12<br />
|-<br />
| 0110001 || 23<br />
|-<br />
| 0110010 || 18<br />
|-<br />
| 0110100 || 17<br />
|-<br />
| 0110111 || 20<br />
|-<br />
| 0111000 || 24<br />
|-<br />
| 0111011 || 29<br />
|-<br />
| 0111101 || 30<br />
|-<br />
| 0111110 || 27<br />
|-<br />
| 1000000 || 38<br />
|-<br />
| 1011000 || 0<br />
|-<br />
| 1011011 || 5<br />
|-<br />
| 1011101 || 6<br />
|-<br />
| 1011110 || 3<br />
|-<br />
| 1101000 || 8<br />
|-<br />
| 1101011 || 13<br />
|-<br />
| 1101101 || 14<br />
|-<br />
| 1101110 || 11<br />
|-<br />
| 1110000 || 16<br />
|-<br />
| 1110011 || 21<br />
|-<br />
| 1110101 || 22<br />
|-<br />
| 1110110 || 19<br />
|-<br />
| 1111001 || 31<br />
|-<br />
| 1111010 || 26<br />
|-<br />
| 1111100 || 25<br />
|-<br />
| 1111111 || 28<br />
|-<br />
| other || multibit error<br />
|}<br />
<br />
==TROUBLESHOOTING==<br />
<br />
We now have all of the information necessary to narrow down which bits in which address regions are bad. However, that doesn't do any good for repair unless we also know which physical DRAMs that bit and region correspond to.<br />
<br />
===MS650-AA===<br />
<br />
Shown below is a diagram of the MS650-AA RAM card, broken up into 11 columns and 37 rows. Each spot in this grid contains up to 1 DRAM, but some locations contain other circuitry instead.<br />
<br />
<nowiki><br />
<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
--------------------------------------------------------------------------------<br />
01 | ooooooooooooooooooooooooo |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 01<br />
| --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
08 | --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 08<br />
|-------------------------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
09 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 09<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
16 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 16<br />
17 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 17<br />
18 |DDDDDDD|TTTTTTT TTTTTTTTT TTTTTTTT |DDDDDDDDDDDDD|TTTTTTTT TTTTTTTTT TTTTTTTT | 18<br />
19 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 19<br />
20 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 20<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
32 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 32<br />
33 |DDDDDDD-----------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 33<br />
36 |DDDDDDD| PPPPPPP TTTTT TTTTT |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 35<br />
37 |-------- TTTTTTT TTTTTTT --------DDDDDDDDDDDDDD-------DDDDDDDDDDDDDD| 37<br />
| -------------- --------------| <br />
| ___- - ___- |<br />
| | | || | | |<br />
-------------------- ----------------------------------------------------------<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
<br />
-----------------------------------------------<br />
| D DRAMS |<br />
| T TTL IC |<br />
| B some kind of DEC custom fast data buffer? |<br />
| P PAL16L8 |<br />
| o data connector |<br />
| | border |<br />
| - border |<br />
-----------------------------------------------<br />
<br />
</nowiki><br />
<br />
The MS650-AA RAM card uses two RAS lines. During normal initialization of the VAX, the rank connected to RAS0 will be first in memory, followed by the rank connected to RAS1. Presumably, the MS650-BA card would have 4 ranks.<br />
<br />
RAS0 - first 4MB<br />
RAS1 - second 4MB<br />
<br />
Based on the bit with the error, as well as the memory region where the error occurred, the specific DRAM with the failure can be found and replaced.<br />
<br />
Below is a list of the DRAMs sorted by memory region and bit, showing the grid location of the DRAM IC.<br />
<br />
By using the built in tests, along with MEMCSR16, and perhaps some manual DEPOSIT and EXAMINE testing, the bad DRAM should be possible to locate and then, using this table, the DRAM can be replaced.<br />
<br />
{| border=1 style="text-align:center"<br />
| DRAM || Address || data bit<br />
| A12 || 0XXXXX || MD00<br />
|A11 - 1XXXXX MD00<br />
|A10 - 2XXXXX MD00<br />
|A09 - 3XXXXX MD00<br />
|A16 - 4XXXXX MD00<br />
|A15 - 5XXXXX MD00<br />
|A14 - 6XXXXX MD00<br />
|A13 - 7XXXXX MD00<br />
|A24 - 0XXXXX MD01<br />
|A23 - 1XXXXX MD01<br />
|A22 - 2XXXXX MD01<br />
|A21 - 3XXXXX MD01<br />
|A20 - 4XXXXX MD01<br />
|A19 - 5XXXXX MD01<br />
|A18 - 6XXXXX MD01<br />
|A17 - 7XXXXX MD01<br />
|A32 - 0XXXXX MD02<br />
|A31 - 1XXXXX MD02<br />
|A30 - 2XXXXX MD02<br />
|A29 - 3XXXXX MD02<br />
|A28 - 4XXXXX MD02<br />
|A27 - 5XXXXX MD02<br />
|A26 - 6XXXXX MD02<br />
|A25 - 7XXXXX MD02<br />
|B12 - 0XXXXX MD03<br />
|B11 - 1XXXXX MD03<br />
|B10 - 2XXXXX MD03<br />
|B09 - 3XXXXX MD03<br />
|A36 - 4XXXXX MD03<br />
|A35 - 5XXXXX MD03<br />
|A34 - 6XXXXX MD03<br />
|A33 - 7XXXXX MD03<br />
|B24 - 0XXXXX MD04<br />
|B23 - 1XXXXX MD04<br />
|B22 - 2XXXXX MD04<br />
|B21 - 3XXXXX MD04<br />
|B16 - 4XXXXX MD04<br />
|B15 - 5XXXXX MD04<br />
|B14 - 6XXXXX MD04<br />
|B13 - 7XXXXX MD04<br />
|B32 - 0XXXXX MD05<br />
|B31 - 1XXXXX MD05<br />
|B30 - 2XXXXX MD05<br />
|B29 - 3XXXXX MD05<br />
|B28 - 4XXXXX MD05<br />
|B27 - 5XXXXX MD05<br />
|B26 - 6XXXXX MD05<br />
|B25 - 7XXXXX MD05<br />
|C12 - 0XXXXX MD06<br />
|C11 - 1XXXXX MD06<br />
|C10 - 2XXXXX MD06<br />
|C09 - 3XXXXX MD06<br />
|C16 - 4XXXXX MD06<br />
|C15 - 5XXXXX MD06<br />
|C14 - 6XXXXX MD06<br />
|C13 - 7XXXXX MD06<br />
|C24 - 0XXXXX MD07<br />
|C23 - 1XXXXX MD07<br />
|C22 - 2XXXXX MD07<br />
|C21 - 3XXXXX MD07<br />
|E20 - 4XXXXX MD07<br />
|D20 - 5XXXXX MD07<br />
|C20 - 6XXXXX MD07<br />
|B20 - 7XXXXX MD07<br />
|C32 - 0XXXXX MD08<br />
|C31 - 1XXXXX MD08<br />
|C30 - 2XXXXX MD08<br />
|C29 - 3XXXXX MD08<br />
|C28 - 4XXXXX MD08<br />
|C27 - 5XXXXX MD08<br />
|C26 - 6XXXXX MD08<br />
|C25 - 7XXXXX MD08<br />
|D32 - 0XXXXX MD09<br />
|D31 - 1XXXXX MD09<br />
|D30 - 2XXXXX MD09<br />
|D29 - 3XXXXX MD09<br />
|D28 - 4XXXXX MD09<br />
|D27 - 5XXXXX MD09<br />
|D26 - 6XXXXX MD09<br />
|D25 - 7XXXXX MD09<br />
|D24 - 0XXXXX MD10<br />
|D23 - 1XXXXX MD10<br />
|D22 - 2XXXXX MD10<br />
|D21 - 3XXXXX MD10<br />
|D16 - 4XXXXX MD10<br />
|D15 - 5XXXXX MD10<br />
|D14 - 6XXXXX MD10<br />
|D13 - 7XXXXX MD10<br />
|D12 - 0XXXXX MD11<br />
|D11 - 1XXXXX MD11<br />
|D10 - 2XXXXX MD11<br />
|D09 - 3XXXXX MD11<br />
|E16 - 4XXXXX MD11<br />
|E15 - 5XXXXX MD11<br />
|E14 - 6XXXXX MD11<br />
|E13 - 7XXXXX MD11<br />
|E12 - 0XXXXX MD12<br />
|E11 - 1XXXXX MD12<br />
|E10 - 2XXXXX MD12<br />
|E09 - 3XXXXX MD12<br />
|E28 - 4XXXXX MD12<br />
|E27 - 5XXXXX MD12<br />
|E26 - 6XXXXX MD12<br />
|E25 - 7XXXXX MD12<br />
|E24 - 0XXXXX MD13<br />
|E23 - 1XXXXX MD13<br />
|E22 - 2XXXXX MD13<br />
|E21 - 3XXXXX MD13<br />
|F16 - 4XXXXX MD13<br />
|F15 - 5XXXXX MD13<br />
|F14 - 6XXXXX MD13<br />
|F13 - 7XXXXX MD13<br />
|E32 - 0XXXXX MD14<br />
|E31 - 1XXXXX MD14<br />
|E30 - 2XXXXX MD14<br />
|E29 - 3XXXXX MD14<br />
|F20 - 4XXXXX MD14<br />
|F19 - 5XXXXX MD14<br />
|F18 - 6XXXXX MD14<br />
|F17 - 7XXXXX MD14<br />
|F32 - 0XXXXX MD15<br />
|F31 - 1XXXXX MD15<br />
|F30 - 2XXXXX MD15<br />
|F29 - 3XXXXX MD15<br />
|F28 - 4XXXXX MD15<br />
|F27 - 5XXXXX MD15<br />
|F26 - 6XXXXX MD15<br />
|F25 - 7XXXXX MD15<br />
|F24 - 0XXXXX MD16<br />
|F23 - 1XXXXX MD16<br />
|F22 - 2XXXXX MD16<br />
|F21 - 3XXXXX MD16<br />
|F36 - 4XXXXX MD16<br />
|F35 - 5XXXXX MD16<br />
|F34 - 6XXXXX MD16<br />
|F33 - 7XXXXX MD16<br />
|G32 - 0XXXXX MD17<br />
|G31 - 1XXXXX MD17<br />
|G30 - 2XXXXX MD17<br />
|G29 - 3XXXXX MD17<br />
|G36 - 4XXXXX MD17<br />
|G35 - 5XXXXX MD17<br />
|G34 - 6XXXXX MD17<br />
|G33 - 7XXXXX MD17<br />
|G24 - 0XXXXX MD18<br />
|G23 - 1XXXXX MD18<br />
|G22 - 2XXXXX MD18<br />
|G21 - 3XXXXX MD18<br />
|G28 - 4XXXXX MD18<br />
|G27 - 5XXXXX MD18<br />
|G26 - 6XXXXX MD18<br />
|G25 - 7XXXXX MD18<br />
|H32 - 0XXXXX MD19<br />
|H31 - 1XXXXX MD19<br />
|H30 - 2XXXXX MD19<br />
|H29 - 3XXXXX MD19<br />
|G20 - 4XXXXX MD19<br />
|G19 - 5XXXXX MD19<br />
|G18 - 6XXXXX MD19<br />
|G17 - 7XXXXX MD19<br />
|H24 - 0XXXXX MD20<br />
|H23 - 1XXXXX MD20<br />
|H22 - 2XXXXX MD20<br />
|H21 - 3XXXXX MD20<br />
|K37 - 4XXXXX MD20<br />
|J37 - 5XXXXX MD20<br />
|H37 - 6XXXXX MD20<br />
|G37 - 7XXXXX MD20<br />
|I32 - 0XXXXX MD21<br />
|I31 - 1XXXXX MD21<br />
|I30 - 2XXXXX MD21<br />
|I29 - 3XXXXX MD21<br />
|H36 - 4XXXXX MD21<br />
|H35 - 5XXXXX MD21<br />
|H34 - 6XXXXX MD21<br />
|H33 - 7XXXXX MD21<br />
|I24 - 0XXXXX MD22<br />
|I23 - 1XXXXX MD22<br />
|I22 - 2XXXXX MD22<br />
|I21 - 3XXXXX MD22<br />
|H28 - 4XXXXX MD22<br />
|H27 - 5XXXXX MD22<br />
|H26 - 6XXXXX MD22<br />
|H25 - 7XXXXX MD22<br />
|J32 - 0XXXXX MD23<br />
|J31 - 1XXXXX MD23<br />
|J30 - 2XXXXX MD23<br />
|J29 - 3XXXXX MD23<br />
|I36 - 4XXXXX MD23<br />
|I35 - 5XXXXX MD23<br />
|I34 - 6XXXXX MD23<br />
|I33 - 7XXXXX MD23<br />
|J24 - 0XXXXX MD24<br />
|J23 - 1XXXXX MD24<br />
|J22 - 2XXXXX MD24<br />
|J21 - 3XXXXX MD24<br />
|I28 - 4XXXXX MD24<br />
|I27 - 5XXXXX MD24<br />
|I26 - 6XXXXX MD24<br />
|I25 - 7XXXXX MD24<br />
|K32 - 0XXXXX MD25<br />
|K31 - 1XXXXX MD25<br />
|K30 - 2XXXXX MD25<br />
|K29 - 3XXXXX MD25<br />
|J36 - 4XXXXX MD25<br />
|J35 - 5XXXXX MD25<br />
|J34 - 6XXXXX MD25<br />
|J33 - 7XXXXX MD25<br />
|K24 - 0XXXXX MD26<br />
|K23 - 1XXXXX MD26<br />
|K22 - 2XXXXX MD26<br />
|K21 - 3XXXXX MD26<br />
|J28 - 4XXXXX MD26<br />
|J27 - 5XXXXX MD26<br />
|J26 - 6XXXXX MD26<br />
|J25 - 7XXXXX MD26<br />
|K20 - 0XXXXX MD27<br />
|J20 - 1XXXXX MD27<br />
|I20 - 2XXXXX MD27<br />
|H20 - 3XXXXX MD27<br />
|K36 - 4XXXXX MD27<br />
|K35 - 5XXXXX MD27<br />
|K34 - 6XXXXX MD27<br />
|K33 - 7XXXXX MD27<br />
|F12 - 0XXXXX MD28<br />
|F11 - 1XXXXX MD28<br />
|F10 - 2XXXXX MD28<br />
|F09 - 3XXXXX MD28<br />
|K28 - 4XXXXX MD28<br />
|K26 - 6XXXXX MD28<br />
|K27 - 5XXXXX MD28<br />
|K25 - 7XXXXX MD28<br />
|G12 - 0XXXXX MD29<br />
|G11 - 1XXXXX MD29<br />
|G10 - 2XXXXX MD29<br />
|G09 - 3XXXXX MD29<br />
|G16 - 4XXXXX MD29<br />
|G15 - 5XXXXX MD29<br />
|G14 - 6XXXXX MD29<br />
|G13 - 7XXXXX MD29<br />
|G04 - 0XXXXX MD30<br />
|G03 - 1XXXXX MD30<br />
|G02 - 2XXXXX MD30<br />
|G01 - 3XXXXX MD30<br />
|G08 - 4XXXXX MD30<br />
|G07 - 5XXXXX MD30<br />
|G06 - 6XXXXX MD30<br />
|G05 - 7XXXXX MD30<br />
|H04 - 0XXXXX MD31<br />
|H03 - 1XXXXX MD31<br />
|H02 - 2XXXXX MD31<br />
|H01 - 3XXXXX MD31<br />
|H08 - 4XXXXX MD31<br />
|H07 - 5XXXXX MD31<br />
|H06 - 6XXXXX MD31<br />
|H05 - 7XXXXX MD31<br />
|H12 - 0XXXXX MD32<br />
|H11 - 1XXXXX MD32<br />
|H10 - 2XXXXX MD32<br />
|H09 - 3XXXXX MD32<br />
|H16 - 4XXXXX MD32<br />
|H15 - 5XXXXX MD32<br />
|H14 - 6XXXXX MD32<br />
|H13 - 7XXXXX MD32<br />
|I04 - 0XXXXX MD33<br />
|I03 - 1XXXXX MD33<br />
|I02 - 2XXXXX MD33<br />
|I01 - 3XXXXX MD33<br />
|I08 - 4XXXXX MD33<br />
|I07 - 5XXXXX MD33<br />
|I06 - 6XXXXX MD33<br />
|I05 - 7XXXXX MD33<br />
|I12 - 0XXXXX MD34<br />
|I11 - 1XXXXX MD34<br />
|I10 - 2XXXXX MD34<br />
|I09 - 3XXXXX MD34<br />
|I16 - 4XXXXX MD34<br />
|I15 - 5XXXXX MD34<br />
|I14 - 6XXXXX MD34<br />
|I13 - 7XXXXX MD34<br />
|J04 - 0XXXXX MD35<br />
|J03 - 1XXXXX MD35<br />
|J02 - 2XXXXX MD35<br />
|J01 - 3XXXXX MD35<br />
|J08 - 4XXXXX MD35<br />
|J07 - 5XXXXX MD35<br />
|J06 - 6XXXXX MD35<br />
|J05 - 7XXXXX MD35<br />
|J12 - 0XXXXX MD36<br />
|J11 - 1XXXXX MD36<br />
|J10 - 2XXXXX MD36<br />
|J09 - 3XXXXX MD36<br />
|J16 - 4XXXXX MD36<br />
|J15 - 5XXXXX MD36<br />
|J14 - 6XXXXX MD36<br />
|J13 - 7XXXXX MD36<br />
|K04 - 0XXXXX MD37<br />
|K03 - 1XXXXX MD37<br />
|K02 - 2XXXXX MD37<br />
|K01 - 3XXXXX MD37<br />
|K08 - 4XXXXX MD37<br />
|K07 - 5XXXXX MD37<br />
|K06 - 6XXXXX MD37<br />
|K05 - 7XXXXX MD37<br />
|K12 - 0XXXXX MD38<br />
|K11 - 1XXXXX MD38<br />
|K10 - 2XXXXX MD38<br />
|K09 - 3XXXXX MD38<br />
|K16 - 4XXXXX MD38<br />
|K15 - 5XXXXX MD38<br />
|K14 - 6XXXXX MD38<br />
|K13 - 7XXXXX MD38<br />
|}</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_Main_Memory_System&diff=21853
KA650 Main Memory System
2019-11-24T00:50:15Z
<p>Jzatarski: Initial info dump</p>
<hr />
<div>DEC MS650-AA: NOTES ON TROUBLESHOOTING, REPAIR, AND THEORY OF OPERATION<br />
<br />
OVERVIEW<br />
<br />
The MS650-AA memory card is intended to be used with the DEC KA650 VAX CPU, as<br />
the name might suggest. The quad width card contains 8MB of memory for the VAX,<br />
complete with ECC.<br />
<br />
THEORY OF OPERATION<br />
MEMORY CONTROLLER GENERAL ARCHITECTURE AND ORGANIZATION<br />
The CMCTL IC is the DRAM controller for the KA650 CPU. It has 10 address line<br />
outputs, 39 data I/O, 4 CAS lines, 4 RAS lines, a WE pin, and an SE pin. Also<br />
available to the RAM card are the inverse of the 20th and 21st address lines,<br />
which are used as rank selection when using 256kxX DRAMs. The data lines are<br />
provided to the RAM cards through a 50 conductor ribbon cable, while the rest of<br />
the control lines are provided through the CD interconnect on the backplane.<br />
<br />
The 10 address lines carry the row address on the rising edge of a RAS line,<br />
followed by the column address on the rising edge of a CAS line.<br />
<br />
The 39 data I/O carry the 32 data and 7 ECC bits for the RAM<br />
<br />
The 4 CAS (Column Address Strobe) lines allow strobing the column address on up<br />
to 4 separate memory cards.<br />
<br />
The 4 RAS (Row Address Strobe) lines allow selection of up to 4 banks on a<br />
single memory card.<br />
<br />
The WE (Write Enable) pin indicates that the CMCTL is writing to memory, rather<br />
than reading.<br />
<br />
The SE (Strobe Enable?) pin seems to indicate that the CMCTL is refreshing<br />
memory.<br />
<br />
The XA20 and XA21 lines are the inverse of the latched address lines from the<br />
CDAL bus.<br />
<br />
Note that many of the above control lines are inverse logic from what is<br />
normally used to drive DRAMs; in particular, CAS, RAS, and WE lines are inverted<br />
from the normal JEDEC DRAM convention of active low /RAS, /CAS, and /WE.<br />
<br />
<br />
Due to the 10 bit address bus using conventional multiplexed row and column DRAM<br />
addressing, an effective 20 bit address is formed. This allows the CMCTL to<br />
address up to 1MWord per bank.<br />
<br />
By strobing different pairings of RAS and CAS (RAS0+CAS0 is one bank, while<br />
RAS0+CAS1 is another bank, while RAS1+CAS0 is yet another bank), the CMCTL<br />
supports up to 16 banks of RAM, each 1Mx39. Each bank is thus 4MB of memory once<br />
ECC overhead is accounted for. This puts a 64MB cap on the maximum amount of<br />
memory the CMCTL can address (16 banks of 4MB).<br />
<br />
When 256kxX DRAMs are used in place of 1MxX DRAMs, each 1Mx39 bank is divided<br />
into 4 ranks of 256kx39. Each rank is selected by XA20 and XA21, which are<br />
provided to the RAM cards via the CD interconnect. These address bits appear to<br />
only be valid on the risng edge of RAS. Before CAS has strobed, the bits have<br />
generally already changed since these are derived from the CDAL bus of the VAX<br />
CPU. These bits are used to gate the /RAS lines to the DRAMs ensuring that only<br />
the selected rank is addressed. The /CAS line for the card is not affected.<br />
<br />
The MS650-AA card contains 312 256kx1 ZIP DRAMs, organized into 8 ranks of<br />
256kx39. As previously mentioned, one memory bank as addressed by the CMCTL<br />
memory controller consists of 4 ranks, making up a total of 1MWord of memory per<br />
bank. Each DRAM on the card corresponds to one bit of the 39 bit word within a<br />
1MB address region of the VAX.<br />
<br />
ADDRESSING<br />
<br />
The CMCTL appears to convert 32 bit VAX addresses into DRAM addressing as<br />
follows:<br />
<br />
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02<br />
R09 R08 R07 R06 R05 R04 R03 R02 R01 R00<br />
C09 C08 C07 C06 C05 C04 C03 C02 C01 C00<br />
<br />
Axx are VAX address lines<br />
Rxx are DRAM row address bits<br />
Cxx ard DRAM column address bits<br />
<br />
This addressing scheme is used to ensure that 256kxX DRAMs (which use only 9 bit<br />
row and column addresses) are still supported for use with the CMCTL.<br />
<br />
It is, of course, still up to the CMCTL to determine which banks are selected by<br />
the upper bits of a given physical address. This is determined by the MEMCSR0-15<br />
registers, which seem to specify whether or not a bank is present, as well as<br />
what base address it resides at. It may perform other functions, but it does not<br />
seem to be documented in available documentation.<br />
<br />
CAS AND RAS LINES<br />
<br />
Each 16MB or 8MB memory card for the KA650 uses one CAS line in its entirety.<br />
This is why a maximum of 4 cards may be used in a KA650 system. Each RAM card<br />
uses the first CAS line, and passes the remaining lines on to the next card,<br />
shifted down one bit. So for example, the first card gets CAS0 CAS1 CAS2 CAS3,<br />
in that order. It uses CAS0 and passes CAS1 CAS2 and CAS3 on to the next card,<br />
in that order. The next card uses CAS1 and passes on CAS2 and CAS3. This repeats<br />
until 4 cards have used up all of the available CAS lines.<br />
<br />
The CAS line is not gated in any way on the MS650-AA. The CAS line is simply<br />
buffered, inverted to match the polarity of the DRAMs, and distributed to all<br />
DRAMs on the card (likely with some hierarchical buffering methodology)<br />
<br />
REFRESH<br />
<br />
DRAMs are built using one tiny MOS capacitor for each bit. These capacitors leak<br />
slightly and need to be periodically refreshed. DRAM rows are refreshed by<br />
simply addressing a row. Any row access refreshes that row, no column needs to<br />
be strobed for a refresh.<br />
<br />
As such, during refresh cycles, the CMCTL places a row address to be refreshed<br />
on the address bus, asserts SE, and asserts all RAS lines for several clock<br />
cycles. The purpose of the SE signal is so that RAM cards with 256kxX DRAMs do<br />
not gate any of the /RAS lines going to the DRAMs, or else only whatever DRAM<br />
rank is (randomly) addressed by XA20 and XA21 would be refreshed.<br />
<br />
ECC<br />
<br />
The ECC supported by the CMCTL, according to the KA650 technical manual, has the<br />
ability to detect and correct single data bit errors, detect single ECC bit<br />
errors, and detect double-bit data errors.<br />
<br />
ECC is generally based on producing parity bits of various collections of data<br />
bits. Since parity is based around the simple XOR, it is a linear operation in a<br />
manner of speaking. Luckily this means we can determine the ECC equations based<br />
on a number of sample data patterns and the respective ECC bits, such as the ECC<br />
produce for 0 data, and data with only one bit in the word set. By comparing the<br />
ECC for each test pattern to that of 0, we can determine which ECC bits each bit<br />
in the data word affects.<br />
<br />
data LSB ecc LSB<br />
0000 0000 0000 0000 0000 0000 0000 0000 0111100<br />
00 0000 0000 0000 0000 0000 0000 0000 0001 1100100<br />
01 0000 0000 0000 0000 0000 0000 0000 0010 0100000 <--<br />
02 0000 0000 0000 0000 0000 0000 0000 0100 0100110<br />
03 0000 0000 0000 0000 0000 0000 0000 1000 1100010<br />
04 0000 0000 0000 0000 0000 0000 0001 0000 0100011<br />
05 0000 0000 0000 0000 0000 0000 0010 0000 1100111<br />
06 0000 0000 0000 0000 0000 0000 0100 0000 1100001<br />
07 0000 0000 0000 0000 0000 0000 1000 0000 0100101<br />
08 0000 0000 0000 0000 0000 0001 0000 0000 1010100<br />
09 0000 0000 0000 0000 0000 0010 0000 0000 0010000 <--<br />
10 0000 0000 0000 0000 0000 0100 0000 0000 0010110<br />
11 0000 0000 0000 0000 0000 1000 0000 0000 1010010<br />
12 0000 0000 0000 0000 0001 0000 0000 0000 0010011<br />
13 0000 0000 0000 0000 0010 0000 0000 0000 1010111<br />
14 0000 0000 0000 0000 0100 0000 0000 0000 1010001<br />
15 0000 0000 0000 0000 1000 0000 0000 0000 0010101<br />
16 0000 0000 0000 0001 0000 0000 0000 0000 1001100<br />
17 0000 0000 0000 0010 0000 0000 0000 0000 0001000 <--<br />
18 0000 0000 0000 0100 0000 0000 0000 0000 0001110<br />
19 0000 0000 0000 1000 0000 0000 0000 0000 1001010<br />
20 0000 0000 0001 0000 0000 0000 0000 0000 0001011<br />
21 0000 0000 0010 0000 0000 0000 0000 0000 1001111<br />
22 0000 0000 0100 0000 0000 0000 0000 0000 1001001<br />
23 0000 0000 1000 0000 0000 0000 0000 0000 0001101<br />
24 0000 0001 0000 0000 0000 0000 0000 0000 0000100 <--<br />
25 0000 0010 0000 0000 0000 0000 0000 0000 1000000 <--<br />
26 0000 0100 0000 0000 0000 0000 0000 0000 1000110<br />
27 0000 1000 0000 0000 0000 0000 0000 0000 0000010 <--<br />
28 0001 0000 0000 0000 0000 0000 0000 0000 1000011<br />
29 0010 0000 0000 0000 0000 0000 0000 0000 0000111<br />
30 0100 0000 0000 0000 0000 0000 0000 0000 0000001 <--<br />
31 1000 0000 0000 0000 0000 0000 0000 0000 1000101<br />
<br />
The results of this are depicted below. The basic result is that toggling one of<br />
the bits that belongs to the ECC bit group will result in that ECC bit toggling<br />
as well.<br />
<br />
<br />
MD32 - 04,05,06,07, 12,13,14.15, 20,21,22,23, 28,29,30,31<br />
MD33 - 02,03,04,05, 10,11,12,13, 18,19,20,21, 26,27,28,29, <br />
MD34 - 01, 03,04, 06, 09, 11,12, 14, 17, 19,20, 22, 25, 27,28, 30, <br />
MD35 - 00,01,02,03,04,05,06,07,08,09,10,11,12,13,14,15, 24,25,26,27,28,29,30,31<br />
MD36 - 00,01,02,03,04,05,06,07, 16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31<br />
MD37 - 08,09,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31<br />
MD39 - 00, 03, 05,06, 08, 11, 13,14, 16, 19, 21,22, 25,26, 28, 31<br />
^<br />
|<br />
|<br />
note flipping bit 28<br />
flips all ECC bits<br />
<br />
An interesting and potentially useful point to note is that flipping bit 28<br />
happens to flip all of the ECC bits together. Another interesting point is that<br />
inverting the entire data word produces the same ECC.<br />
<br />
From this information, we can derive some data patterns that produce useful ECC<br />
combinations, such as ECC of all zeroes, all ones, only one bit set, and only<br />
one bit clear. Looking at the table above, we got lucky and examples of many of<br />
these combinations were found by chance. In particular, we happened upon data<br />
combinations that produced every possibility of 1 ECC bit set. These, combined<br />
with the fact that we can toggle bit 28 to get the inverse ECC bits, gives us a<br />
set of data patterns which produce ECC with only one bit clear. From here, we<br />
only need to derive a combination which produces all-zero ECC, and from that,<br />
derive all-one ECC.<br />
<br />
Starting with the ECC for bit 31 set, we can toggle single bits at a time until<br />
we find a combination that produces the ECC we want.<br />
<br />
31 1000 0000 0000 0000 0000 0000 0000 0000 1000101<br />
1000 0000 0000 0000 0000 0000 0000 0001 0011101<br />
1000 0000 0000 0000 0000 0010 0000 0001 0110001<br />
1000 0000 1000 0000 0000 0010 0000 0001 0000000 <--<br />
1001 0000 1000 0000 0000 0010 0000 0001 1111111 <--<br />
<br />
The summary of these useful ECC combinations is tabulated below (data in hex,<br />
ECC in binary)<br />
<br />
useful ECC combinations:<br />
ECC data<br />
0000000 80800201<br />
0000001 40000000<br />
0000010 08000000<br />
0000100 01000000<br />
0001000 00020000<br />
0010000 00000200<br />
0100000 00000002<br />
1000000 02000000<br />
1111111 90800201<br />
1111110 50000000<br />
1111101 18000000<br />
1111011 11000000<br />
1110111 10020000<br />
1101111 10000200<br />
1011111 10000002<br />
0111111 12000000<br />
<br />
KA650 VAX FIRMWARE MEMORY TESTS<br />
<br />
Many of the tests built in to the firmware of the VAX can be quite thorough, if<br />
used properly. The tests can be accessed by the TEST command in the monitor,<br />
abbreviated to 't'.<br />
<br />
The tests report diagnostic information upon failure, encoded simply as a number<br />
of values in registers and memory locations on the stack. With the proper<br />
documentation, these values could be decoded to determine the problem. Lacking<br />
that documentation, I was able to reverse engineer enough of one test that was<br />
failing to understand it's ouput.<br />
<br />
TEST 48: MEM_Addr_shrts<br />
This test is normally used to check for shorted address lines. It will fill the<br />
memory with a pattern first, then it will check each word in order to see if it<br />
is still the same pattern. After checking a word, it will check the CMCTL status<br />
register to ensure there were no detected errors. Then it will replace the word<br />
with another pattern (usually mostly an inverse of the first pattern).<br />
<br />
If any address line is shorted, when the test writes the second pattern, it will<br />
affect another location in memory. When that location is encountered, it will<br />
read as the wrong data thus showing the issue. However, the test is also capable<br />
of detecting stuck bits the way it is designed, and this test happened to find<br />
all DRAM errors in my case.<br />
<br />
The output when the test encounters an error looks like the following:<br />
<br />
>>>t 48<br />
<br />
<br />
?48 2 08 FF 00 0002<br />
<br />
P1=00000000 P2=04000000 P3=00000004 P4=00031000 P5=AAAAAAAA<br />
P6=55555555 P7=00000043 P8=200C5875 P9=00000000 P10=2005311F<br />
r0=45555555 r1=000C5860 r2=45555555 r3=00000004 r4=0000006B<br />
r5=AAAAAAAA r6=20080140 r7=20080144 r8=00000000 ERF=80000000<br />
<br />
Normal operation not possible.<br />
<br />
>>><br />
<br />
I figured out the meaning of some of these registers for this test. First of<br />
all, P10 indicates an address where presumably DEC personnel would check a<br />
source listing to find out the exact meaning of the rest of the values shown.<br />
The meanings of the registers I have found are only valid for this routine,<br />
located near 2005311F.<br />
<br />
r0 - contents of memory at address being tested<br />
r1 - address being tested<br />
r2 - expected pattern from memory being tested<br />
r5 - pattern to replace location with<br />
r6 - address of CMCTL MEMCSR16 (a diagnostic register)<br />
P8 - contents of MEMCSR16<br />
<br />
MEMCSR16 REGISTER<br />
<br />
The MEMCSR16 register gives us information on what kind of memory failure<br />
occurred. The bit meanings are as follows, according the the KA650 technical<br />
manual:<br />
<br />
<31> set if uncorrectable error occurred<br />
<30> set if multiple uncorrectable errors occurred<br />
<29> set if correctable error occurred<br />
<28:9> page address where error occurred (pages are 512 bytes)<br />
<8> set if error ocurred during DMA<br />
<7> set if CDAL bus parity error occurred<br />
<6:0> error syndrome: a unique combination is produced here for each possible<br />
single bit error<br />
<br />
writing 1s to bits 31, 30, 29, 8, or 7 of MEMCSR16 resets those bits. bits 28:9<br />
and 6:0 are read only.<br />
<br />
The MEMCSR registers can be read with test 9c.<br />
<br />
The error syndrome is particularly useful for troubleshooting memory errors as<br />
it can tell us exactly which bit had the error. A list of the syndromes and the<br />
corresponding bit error is given below, copied and resorted from the KA650 tech<br />
manual for convenience.<br />
<br />
syndrome bit position<br />
0000000 no error<br />
0000001 32<br />
0000010 33<br />
0000100 34<br />
0000111 result of incorrect check bits written on CDAL parity error<br />
0001000 35<br />
0010000 36<br />
0011001 7<br />
0011010 2<br />
0011100 1<br />
0011111 4<br />
0100000 37<br />
0101001 15<br />
0101010 10<br />
0101100 9<br />
0101111 12<br />
0110001 23<br />
0110010 18<br />
0110100 17<br />
0110111 20<br />
0111000 24<br />
0111011 29<br />
0111101 30<br />
0111110 27<br />
1000000 38<br />
1011000 0<br />
1011011 5<br />
1011101 6<br />
1011110 3<br />
1101000 8<br />
1101011 13<br />
1101101 14<br />
1101110 11<br />
1110000 16<br />
1110011 21<br />
1110101 22<br />
1110110 19<br />
1111001 31<br />
1111010 26<br />
1111100 25<br />
1111111 28<br />
<br />
ELSE multibit error<br />
<br />
TROUBLESHOOTING<br />
<br />
We now have all of the information necessary to narrow down which bits in which<br />
address regions are bad. However, that doesn't do any good for repair unless we<br />
also know which physical DRAMs that bit and region correspond to.<br />
<br />
Shown below is a diagram of the MS650-AA RAM card, broken up into 11 columns and<br />
37 rows. Each spot in this grid contains up to 1 DRAM, but some locations<br />
contain other circuitry instead.<br />
<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
--------------------------------------------------------------------------------<br />
01 | ooooooooooooooooooooooooo |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 01<br />
| --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
| |BBBBBBB| |BBBBBBB| |BBBBBBB| |BBBBBBB| |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
08 | --------- --------- --------- --------- |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 08<br />
|-------------------------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
09 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 09<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
16 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 16<br />
17 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 17<br />
18 |DDDDDDD|TTTTTTT TTTTTTTTT TTTTTTTT |DDDDDDDDDDDDD|TTTTTTTT TTTTTTTTT TTTTTTTT | 18<br />
19 |DDDDDDD-----------------------------DDDDDDDDDDDDD-----------------------------| 19<br />
20 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 20<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
|DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD|<br />
32 |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 32<br />
33 |DDDDDDD-----------------------------DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 33<br />
36 |DDDDDDD| PPPPPPP TTTTT TTTTT |DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD| 35<br />
37 |-------- TTTTTTT TTTTTTT --------DDDDDDDDDDDDDD-------DDDDDDDDDDDDDD| 37<br />
| -------------- --------------| <br />
| ___- - ___- |<br />
| | | || | | |<br />
-------------------- ----------------------------------------------------------<br />
| A | B | C | D | E | F | G | H | I | J | K |<br />
<br />
-----------------------------------------------<br />
| D DRAMS |<br />
| T TTL IC |<br />
| B some kind of DEC custom fast data buffer? |<br />
| P PAL16L8 |<br />
| o data connector |<br />
| | border |<br />
| - border |<br />
-----------------------------------------------<br />
<br />
The RAM card uses two RAS lines. During normal initialization of the VAX, the<br />
bank connected to RAS0 will be first in memory, followed by the bank connected<br />
to RAS1.<br />
<br />
RAS0 - first 4MB<br />
RAS1 - second 4MB<br />
<br />
Based on the bit with the error, as well as the memory region where the error<br />
occurred, the specific DRAM with the failure can be found and replaced.<br />
<br />
Below is a list of the DRAMs sorted by memory region and bit, showing the grid<br />
location of the DRAM IC.<br />
<br />
By using the built in tests, along with MEMCSR16, and perhaps some manual<br />
DEPOSIT and EXAMINE testing, the bad DRAM should be possible to locate and then,<br />
using this table, the DRAM can be replaced.<br />
<br />
<br />
A12 - 0XXXXX MD00<br />
A11 - 1XXXXX MD00<br />
A10 - 2XXXXX MD00<br />
A09 - 3XXXXX MD00<br />
A16 - 4XXXXX MD00<br />
A15 - 5XXXXX MD00<br />
A14 - 6XXXXX MD00<br />
A13 - 7XXXXX MD00<br />
A24 - 0XXXXX MD01<br />
A23 - 1XXXXX MD01<br />
A22 - 2XXXXX MD01<br />
A21 - 3XXXXX MD01<br />
A20 - 4XXXXX MD01<br />
A19 - 5XXXXX MD01<br />
A18 - 6XXXXX MD01<br />
A17 - 7XXXXX MD01<br />
A32 - 0XXXXX MD02<br />
A31 - 1XXXXX MD02<br />
A30 - 2XXXXX MD02<br />
A29 - 3XXXXX MD02<br />
A28 - 4XXXXX MD02<br />
A27 - 5XXXXX MD02<br />
A26 - 6XXXXX MD02<br />
A25 - 7XXXXX MD02<br />
B12 - 0XXXXX MD03<br />
B11 - 1XXXXX MD03<br />
B10 - 2XXXXX MD03<br />
B09 - 3XXXXX MD03<br />
A36 - 4XXXXX MD03<br />
A35 - 5XXXXX MD03<br />
A34 - 6XXXXX MD03<br />
A33 - 7XXXXX MD03<br />
B24 - 0XXXXX MD04<br />
B23 - 1XXXXX MD04<br />
B22 - 2XXXXX MD04<br />
B21 - 3XXXXX MD04<br />
B16 - 4XXXXX MD04<br />
B15 - 5XXXXX MD04<br />
B14 - 6XXXXX MD04<br />
B13 - 7XXXXX MD04<br />
B32 - 0XXXXX MD05<br />
B31 - 1XXXXX MD05<br />
B30 - 2XXXXX MD05<br />
B29 - 3XXXXX MD05<br />
B28 - 4XXXXX MD05<br />
B27 - 5XXXXX MD05<br />
B26 - 6XXXXX MD05<br />
B25 - 7XXXXX MD05<br />
C12 - 0XXXXX MD06<br />
C11 - 1XXXXX MD06<br />
C10 - 2XXXXX MD06<br />
C09 - 3XXXXX MD06<br />
C16 - 4XXXXX MD06<br />
C15 - 5XXXXX MD06<br />
C14 - 6XXXXX MD06<br />
C13 - 7XXXXX MD06<br />
C24 - 0XXXXX MD07<br />
C23 - 1XXXXX MD07<br />
C22 - 2XXXXX MD07<br />
C21 - 3XXXXX MD07<br />
E20 - 4XXXXX MD07<br />
D20 - 5XXXXX MD07<br />
C20 - 6XXXXX MD07<br />
B20 - 7XXXXX MD07<br />
C32 - 0XXXXX MD08<br />
C31 - 1XXXXX MD08<br />
C30 - 2XXXXX MD08<br />
C29 - 3XXXXX MD08<br />
C28 - 4XXXXX MD08<br />
C27 - 5XXXXX MD08<br />
C26 - 6XXXXX MD08<br />
C25 - 7XXXXX MD08<br />
D32 - 0XXXXX MD09<br />
D31 - 1XXXXX MD09<br />
D30 - 2XXXXX MD09<br />
D29 - 3XXXXX MD09<br />
D28 - 4XXXXX MD09<br />
D27 - 5XXXXX MD09<br />
D26 - 6XXXXX MD09<br />
D25 - 7XXXXX MD09<br />
D24 - 0XXXXX MD10<br />
D23 - 1XXXXX MD10<br />
D22 - 2XXXXX MD10<br />
D21 - 3XXXXX MD10<br />
D16 - 4XXXXX MD10<br />
D15 - 5XXXXX MD10<br />
D14 - 6XXXXX MD10<br />
D13 - 7XXXXX MD10<br />
D12 - 0XXXXX MD11<br />
D11 - 1XXXXX MD11<br />
D10 - 2XXXXX MD11<br />
D09 - 3XXXXX MD11<br />
E16 - 4XXXXX MD11<br />
E15 - 5XXXXX MD11<br />
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E12 - 0XXXXX MD12<br />
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E10 - 2XXXXX MD12<br />
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E28 - 4XXXXX MD12<br />
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E22 - 2XXXXX MD13<br />
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F16 - 4XXXXX MD13<br />
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F14 - 6XXXXX MD13<br />
F13 - 7XXXXX MD13<br />
E32 - 0XXXXX MD14<br />
E31 - 1XXXXX MD14<br />
E30 - 2XXXXX MD14<br />
E29 - 3XXXXX MD14<br />
F20 - 4XXXXX MD14<br />
F19 - 5XXXXX MD14<br />
F18 - 6XXXXX MD14<br />
F17 - 7XXXXX MD14<br />
F32 - 0XXXXX MD15<br />
F31 - 1XXXXX MD15<br />
F30 - 2XXXXX MD15<br />
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F28 - 4XXXXX MD15<br />
F27 - 5XXXXX MD15<br />
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F25 - 7XXXXX MD15<br />
F24 - 0XXXXX MD16<br />
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F22 - 2XXXXX MD16<br />
F21 - 3XXXXX MD16<br />
F36 - 4XXXXX MD16<br />
F35 - 5XXXXX MD16<br />
F34 - 6XXXXX MD16<br />
F33 - 7XXXXX MD16<br />
G32 - 0XXXXX MD17<br />
G31 - 1XXXXX MD17<br />
G30 - 2XXXXX MD17<br />
G29 - 3XXXXX MD17<br />
G36 - 4XXXXX MD17<br />
G35 - 5XXXXX MD17<br />
G34 - 6XXXXX MD17<br />
G33 - 7XXXXX MD17<br />
G24 - 0XXXXX MD18<br />
G23 - 1XXXXX MD18<br />
G22 - 2XXXXX MD18<br />
G21 - 3XXXXX MD18<br />
G28 - 4XXXXX MD18<br />
G27 - 5XXXXX MD18<br />
G26 - 6XXXXX MD18<br />
G25 - 7XXXXX MD18<br />
H32 - 0XXXXX MD19<br />
H31 - 1XXXXX MD19<br />
H30 - 2XXXXX MD19<br />
H29 - 3XXXXX MD19<br />
G20 - 4XXXXX MD19<br />
G19 - 5XXXXX MD19<br />
G18 - 6XXXXX MD19<br />
G17 - 7XXXXX MD19<br />
H24 - 0XXXXX MD20<br />
H23 - 1XXXXX MD20<br />
H22 - 2XXXXX MD20<br />
H21 - 3XXXXX MD20<br />
K37 - 4XXXXX MD20<br />
J37 - 5XXXXX MD20<br />
H37 - 6XXXXX MD20<br />
G37 - 7XXXXX MD20<br />
I32 - 0XXXXX MD21<br />
I31 - 1XXXXX MD21<br />
I30 - 2XXXXX MD21<br />
I29 - 3XXXXX MD21<br />
H36 - 4XXXXX MD21<br />
H35 - 5XXXXX MD21<br />
H34 - 6XXXXX MD21<br />
H33 - 7XXXXX MD21<br />
I24 - 0XXXXX MD22<br />
I23 - 1XXXXX MD22<br />
I22 - 2XXXXX MD22<br />
I21 - 3XXXXX MD22<br />
H28 - 4XXXXX MD22<br />
H27 - 5XXXXX MD22<br />
H26 - 6XXXXX MD22<br />
H25 - 7XXXXX MD22<br />
J32 - 0XXXXX MD23<br />
J31 - 1XXXXX MD23<br />
J30 - 2XXXXX MD23<br />
J29 - 3XXXXX MD23<br />
I36 - 4XXXXX MD23<br />
I35 - 5XXXXX MD23<br />
I34 - 6XXXXX MD23<br />
I33 - 7XXXXX MD23<br />
J24 - 0XXXXX MD24<br />
J23 - 1XXXXX MD24<br />
J22 - 2XXXXX MD24<br />
J21 - 3XXXXX MD24<br />
I28 - 4XXXXX MD24<br />
I27 - 5XXXXX MD24<br />
I26 - 6XXXXX MD24<br />
I25 - 7XXXXX MD24<br />
K32 - 0XXXXX MD25<br />
K31 - 1XXXXX MD25<br />
K30 - 2XXXXX MD25<br />
K29 - 3XXXXX MD25<br />
J36 - 4XXXXX MD25<br />
J35 - 5XXXXX MD25<br />
J34 - 6XXXXX MD25<br />
J33 - 7XXXXX MD25<br />
K24 - 0XXXXX MD26<br />
K23 - 1XXXXX MD26<br />
K22 - 2XXXXX MD26<br />
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J28 - 4XXXXX MD26<br />
J27 - 5XXXXX MD26<br />
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J25 - 7XXXXX MD26<br />
K20 - 0XXXXX MD27<br />
J20 - 1XXXXX MD27<br />
I20 - 2XXXXX MD27<br />
H20 - 3XXXXX MD27<br />
K36 - 4XXXXX MD27<br />
K35 - 5XXXXX MD27<br />
K34 - 6XXXXX MD27<br />
K33 - 7XXXXX MD27<br />
F12 - 0XXXXX MD28<br />
F11 - 1XXXXX MD28<br />
F10 - 2XXXXX MD28<br />
F09 - 3XXXXX MD28<br />
K28 - 4XXXXX MD28<br />
K26 - 6XXXXX MD28<br />
K27 - 5XXXXX MD28<br />
K25 - 7XXXXX MD28<br />
G12 - 0XXXXX MD29<br />
G11 - 1XXXXX MD29<br />
G10 - 2XXXXX MD29<br />
G09 - 3XXXXX MD29<br />
G16 - 4XXXXX MD29<br />
G15 - 5XXXXX MD29<br />
G14 - 6XXXXX MD29<br />
G13 - 7XXXXX MD29<br />
G04 - 0XXXXX MD30<br />
G03 - 1XXXXX MD30<br />
G02 - 2XXXXX MD30<br />
G01 - 3XXXXX MD30<br />
G08 - 4XXXXX MD30<br />
G07 - 5XXXXX MD30<br />
G06 - 6XXXXX MD30<br />
G05 - 7XXXXX MD30<br />
H04 - 0XXXXX MD31<br />
H03 - 1XXXXX MD31<br />
H02 - 2XXXXX MD31<br />
H01 - 3XXXXX MD31<br />
H08 - 4XXXXX MD31<br />
H07 - 5XXXXX MD31<br />
H06 - 6XXXXX MD31<br />
H05 - 7XXXXX MD31<br />
H12 - 0XXXXX MD32<br />
H11 - 1XXXXX MD32<br />
H10 - 2XXXXX MD32<br />
H09 - 3XXXXX MD32<br />
H16 - 4XXXXX MD32<br />
H15 - 5XXXXX MD32<br />
H14 - 6XXXXX MD32<br />
H13 - 7XXXXX MD32<br />
I04 - 0XXXXX MD33<br />
I03 - 1XXXXX MD33<br />
I02 - 2XXXXX MD33<br />
I01 - 3XXXXX MD33<br />
I08 - 4XXXXX MD33<br />
I07 - 5XXXXX MD33<br />
I06 - 6XXXXX MD33<br />
I05 - 7XXXXX MD33<br />
I12 - 0XXXXX MD34<br />
I11 - 1XXXXX MD34<br />
I10 - 2XXXXX MD34<br />
I09 - 3XXXXX MD34<br />
I16 - 4XXXXX MD34<br />
I15 - 5XXXXX MD34<br />
I14 - 6XXXXX MD34<br />
I13 - 7XXXXX MD34<br />
J04 - 0XXXXX MD35<br />
J03 - 1XXXXX MD35<br />
J02 - 2XXXXX MD35<br />
J01 - 3XXXXX MD35<br />
J08 - 4XXXXX MD35<br />
J07 - 5XXXXX MD35<br />
J06 - 6XXXXX MD35<br />
J05 - 7XXXXX MD35<br />
J12 - 0XXXXX MD36<br />
J11 - 1XXXXX MD36<br />
J10 - 2XXXXX MD36<br />
J09 - 3XXXXX MD36<br />
J16 - 4XXXXX MD36<br />
J15 - 5XXXXX MD36<br />
J14 - 6XXXXX MD36<br />
J13 - 7XXXXX MD36<br />
K04 - 0XXXXX MD37<br />
K03 - 1XXXXX MD37<br />
K02 - 2XXXXX MD37<br />
K01 - 3XXXXX MD37<br />
K08 - 4XXXXX MD37<br />
K07 - 5XXXXX MD37<br />
K06 - 6XXXXX MD37<br />
K05 - 7XXXXX MD37<br />
K12 - 0XXXXX MD38<br />
K11 - 1XXXXX MD38<br />
K10 - 2XXXXX MD38<br />
K09 - 3XXXXX MD38<br />
K16 - 4XXXXX MD38<br />
K15 - 5XXXXX MD38<br />
K14 - 6XXXXX MD38<br />
K13 - 7XXXXX MD38</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_CPU&diff=21852
KA650 CPU
2019-11-24T00:48:14Z
<p>Jzatarski: </p>
<hr />
<div>{{InfoboxVAXCPU-Data<br />
| name = KA650<br />
| OS-support-VMS = V4.7A or later<br />
| OS-support-ULTRIX = ULTRIX V2.2<br />
| CPU-name-VMS = KA650<br />
| CPU-module = KA650<br />
| Module = M7620 [[#ref_3|[3]]]<br />
| Num-proc = 1<br />
| VMS-CPU = 10<br />
| VMS-XCPU = 1<br />
| SID = 0A000005<br />
| XSID = 01530101<br />
| CPU-chip = 78034 (CVAX) [[#ref_1|[1]]]<br />
| FPU-chip = 78132<br />
| CPU-technology = CMOS<br />
| CPU-cycle = 90ns [[#ref_4|[4]]]<br />
| Instruction-buffer = 12 bytes [[#ref_1|[1]]]<br />
| Translation-buffer = 28 entries [[#ref_1|[1]]]<br />
| Cache = 1KB (90ns) [[#ref_1|[1]]]<br />
| Backup-cache = 64KB (180ns longword, 270ns quadword) [[#ref_4|[4]]]<br />
| Compatibility-mode = No<br />
| Console-processor = CPU<br />
| Console-device = None<br />
| Firmware-version = V5.3<br />
| Console-speed = 300 to 38400<br />
| Minimum-memory = 8MB<br />
| Maximum-memory = 64MB<br />
| Memory-checking = 32 + 7 bit ECC [[#ref_4|[4]]]<br />
| Memory-cycle = 450ns longword, 720ns quadword [[#ref_4|[4]]]<br />
| BUS-Qbus = 1 @ 3.3MB/s<br />
| VUPs = 2.7 [[#ref_2|[2]]]<br />
}}<br />
<br />
The KA650 CPU module is a quad-height [[QBUS]] [[VAX]] CPU produced by [[DEC]]. [[#ref_4|[4]]]<br />
<br />
The KA650 is implemented using the [[CVAX]] with floating point instruction support provided by the [[CFPA]], main memory control provided by [[CMCTL]], and various system support functions by the [[SSC]]. <br />
<br />
== References ==<br />
<br />
<div id="ref_1">[1] "CVAX-based Systems", Digital Technical Journal, Vol 1 No 7, August 1988. </div><br />
<div id="ref_2">[2] VAXcluster Systems. Guidelines for VAXCluster System Configurations. EK-VAXCT-CG-006</div><br />
<div id="ref_3">[3] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="ref_4">[4] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div><br />
<br />
{{stub}}</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_CPU&diff=21850
KA650 CPU
2019-11-24T00:22:53Z
<p>Jzatarski: Jzatarski moved page KA650 to DEC KA650</p>
<hr />
<div>{{InfoboxVAXCPU-Data<br />
| name = KA650<br />
| OS-support-VMS = V4.7A or later<br />
| OS-support-ULTRIX = ULTRIX V2.2<br />
| CPU-name-VMS = KA650<br />
| CPU-module = KA650<br />
| Module = M7620 [[#ref_3|[3]]]<br />
| Num-proc = 1<br />
| VMS-CPU = 10<br />
| VMS-XCPU = 1<br />
| SID = 0A000005<br />
| XSID = 01530101<br />
| CPU-chip = 78034 (CVAX) [[#ref_1|[1]]]<br />
| FPU-chip = 78132<br />
| CPU-technology = CMOS<br />
| CPU-cycle = 90ns [[#ref_4|[4]]]<br />
| Instruction-buffer = 12 bytes [[#ref_1|[1]]]<br />
| Translation-buffer = 28 entries [[#ref_1|[1]]]<br />
| Cache = 1KB (90ns) [[#ref_1|[1]]]<br />
| Backup-cache = 64KB (180ns longword, 270ns quadword) [[#ref_4|[4]]]<br />
| Compatibility-mode = No<br />
| Console-processor = CPU<br />
| Console-device = None<br />
| Firmware-version = V5.3<br />
| Console-speed = 300 to 38400<br />
| Minimum-memory = 8MB<br />
| Maximum-memory = 64MB<br />
| Memory-checking = 32 + 7 bit ECC [[#ref_4|[4]]]<br />
| Memory-cycle = 450ns longword, 720ns quadword [[#ref_4|[4]]]<br />
| BUS-Qbus = 1 @ 3.3MB/s<br />
| VUPs = 2.7 [[#ref_2|[2]]]<br />
}}<br />
<br />
The KA650 CPU module is a quad-height [[QBUS]] [[VAX]] CPU produced by [[DEC]]. [[#ref_4|[4]]]<br />
<br />
The KA650 is implemented using the [[CVAX]] with floating point instruction support provided by the [[CFPA]] and main memory control provided by [[CMCTL]]. <br />
<br />
== References ==<br />
<br />
<div id="ref_1">[1] "CVAX-based Systems", Digital Technical Journal, Vol 1 No 7, August 1988. </div><br />
<div id="ref_2">[2] VAXcluster Systems. Guidelines for VAXCluster System Configurations. EK-VAXCT-CG-006</div><br />
<div id="ref_3">[3] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="ref_4">[4] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div><br />
<br />
{{stub}}</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650&diff=21851
KA650
2019-11-24T00:22:53Z
<p>Jzatarski: Jzatarski moved page KA650 to DEC KA650</p>
<hr />
<div>#REDIRECT [[DEC KA650]]</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_CPU&diff=21847
KA650 CPU
2019-11-23T20:16:17Z
<p>Jzatarski: Added some additional basic information on the construction of the CPU on the KA650 module.</p>
<hr />
<div>{{InfoboxVAXCPU-Data<br />
| name = KA650<br />
| OS-support-VMS = V4.7A or later<br />
| OS-support-ULTRIX = ULTRIX V2.2<br />
| CPU-name-VMS = KA650<br />
| CPU-module = KA650<br />
| Module = M7620 [[#ref_3|[3]]]<br />
| Num-proc = 1<br />
| VMS-CPU = 10<br />
| VMS-XCPU = 1<br />
| SID = 0A000005<br />
| XSID = 01530101<br />
| CPU-chip = 78034 (CVAX) [[#ref_1|[1]]]<br />
| FPU-chip = 78132<br />
| CPU-technology = CMOS<br />
| CPU-cycle = 90ns [[#ref_4|[4]]]<br />
| Instruction-buffer = 12 bytes [[#ref_1|[1]]]<br />
| Translation-buffer = 28 entries [[#ref_1|[1]]]<br />
| Cache = 1KB (90ns) [[#ref_1|[1]]]<br />
| Backup-cache = 64KB (180ns longword, 270ns quadword) [[#ref_4|[4]]]<br />
| Compatibility-mode = No<br />
| Console-processor = CPU<br />
| Console-device = None<br />
| Firmware-version = V5.3<br />
| Console-speed = 300 to 38400<br />
| Minimum-memory = 8MB<br />
| Maximum-memory = 64MB<br />
| Memory-checking = 32 + 7 bit ECC [[#ref_4|[4]]]<br />
| Memory-cycle = 450ns longword, 720ns quadword [[#ref_4|[4]]]<br />
| BUS-Qbus = 1 @ 3.3MB/s<br />
| VUPs = 2.7 [[#ref_2|[2]]]<br />
}}<br />
<br />
The KA650 CPU module is a quad-height [[QBUS]] [[VAX]] CPU produced by [[DEC]]. [[#ref_4|[4]]]<br />
<br />
The KA650 is implemented using the [[CVAX]] with floating point instruction support provided by the [[CFPA]] and main memory control provided by [[CMCTL]]. <br />
<br />
== References ==<br />
<br />
<div id="ref_1">[1] "CVAX-based Systems", Digital Technical Journal, Vol 1 No 7, August 1988. </div><br />
<div id="ref_2">[2] VAXcluster Systems. Guidelines for VAXCluster System Configurations. EK-VAXCT-CG-006</div><br />
<div id="ref_3">[3] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="ref_4">[4] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div><br />
<br />
{{stub}}</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA630_CPU&diff=21846
KA630 CPU
2019-11-23T20:00:14Z
<p>Jzatarski: add to DEC VAX Processor category</p>
<hr />
<div>[[Image:M7606.jpg|150px|right]]<br />
DEC M7606A MicroVAX Processor<br />
<br />
DEC VAX Minicomputer MicroVAX KA630 Processor Card uVAX<br />
<br />
the '''KA630''' is the CPU used in the [[MicroVAX II]]. A unique implementation.<br />
<br />
[[Category: DEC Boards]]<br />
[[Category: DEC VAX Processors]]</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_CPU&diff=21845
KA650 CPU
2019-11-23T19:55:25Z
<p>Jzatarski: change template to new VAX CPU infobox template.</p>
<hr />
<div>{{InfoboxVAXCPU-Data<br />
| name = KA650<br />
| OS-support-VMS = V4.7A or later<br />
| OS-support-ULTRIX = ULTRIX V2.2<br />
| CPU-name-VMS = KA650<br />
| CPU-module = KA650<br />
| Module = M7620 [[#ref_3|[3]]]<br />
| Num-proc = 1<br />
| VMS-CPU = 10<br />
| VMS-XCPU = 1<br />
| SID = 0A000005<br />
| XSID = 01530101<br />
| CPU-chip = 78034 (CVAX) [[#ref_1|[1]]]<br />
| FPU-chip = 78132<br />
| CPU-technology = CMOS<br />
| CPU-cycle = 90ns [[#ref_4|[4]]]<br />
| Instruction-buffer = 12 bytes [[#ref_1|[1]]]<br />
| Translation-buffer = 28 entries [[#ref_1|[1]]]<br />
| Cache = 1KB (90ns) [[#ref_1|[1]]]<br />
| Backup-cache = 64KB (180ns longword, 270ns quadword) [[#ref_4|[4]]]<br />
| Compatibility-mode = No<br />
| Console-processor = CPU<br />
| Console-device = None<br />
| Firmware-version = V5.3<br />
| Console-speed = 300 to 38400<br />
| Minimum-memory = 8MB<br />
| Maximum-memory = 64MB<br />
| Memory-checking = 32 + 7 bit ECC [[#ref_4|[4]]]<br />
| Memory-cycle = 450ns longword, 720ns quadword [[#ref_4|[4]]]<br />
| BUS-Qbus = 1 @ 3.3MB/s<br />
| VUPs = 2.7 [[#ref_2|[2]]]<br />
}}<br />
<br />
== References ==<br />
<br />
<div id="ref_1">[1] "CVAX-based Systems", Digital Technical Journal, Vol 1 No 7, August 1988. </div><br />
<div id="ref_2">[2] VAXcluster Systems. Guidelines for VAXCluster System Configurations. EK-VAXCT-CG-006</div><br />
<div id="ref_3">[3] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="ref_4">[4] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div><br />
<br />
{{stub}}</div>
Jzatarski
https://gunkies.org/w/index.php?title=Template:InfoboxVAXCPU-Data&diff=21844
Template:InfoboxVAXCPU-Data
2019-11-23T19:54:52Z
<p>Jzatarski: move to VAX processors category</p>
<hr />
<div><noinclude><br />
This template is for any VAX CPU. It is based off of Template:InfoboxVAX-Data. Some of the fields thus may not apply directly to a CPU.<br />
<br />
<pre><br />
name = the name of the CPU<br />
Announcement = Announcement date<br />
FRS-date = First revenue ship date<br />
FCS-date = First customer ship date<br />
Last-order = Last order date<br />
Last-ship = Last ship date<br />
EOSL = End of service life<br />
Codename = Codename<br />
Desc-name = Descriptive name<br />
Sys-class = System class<br />
OS-support-VMS = Range of VMS versions that support this system<br />
OS-support-MDM = Range of MDM releases that support this system<br />
OS-support-ELN = Range of VAXELN releases that support this system<br />
OS-support-ULTRIX = Range of ULTRIX versions that support this system<br />
CPU-name-VMS = CPU name as reported by ANALYZE/ERROR under VMS<br />
CPU-name-console = CPU name as reported by the console<br />
CPU-module = The CPU module<br />
Module = The system module part number<br />
Num-proc = Number of processors<br />
VMS-CPU = The hexadecimal value returned by the DCL function F$GETSYI("SID") under VMS.<br />
VMS-XCPU = The hexadecimal value returned by the DCL function F$GETSYI("XSID") under VMS.<br />
SID = The System Identification register<br />
XSID = The System Extended Identification register<br />
CPU-chip = The chip that implements the I-box (CPU)<br />
FPU-chip = The chip that implements the F-box (FPU)<br />
CPU-technology = The technology with which the CPU is fabricated<br />
CPU-cycle = The CPU cycle time<br />
CPU-clock = The CPU clock rate<br />
CPU-clock-rate = The raw clock that is supplied to the CPU<br />
Vector-processor = Vector processor<br />
Instruction-buffer = Instruction prefetch queue size<br />
Translation-buffer = The CPU translation buffer size<br />
Control-store = Microcode control store details<br />
Gate-delay = Gate delay<br />
WCS = Writable Control Store<br />
UWCS = User Writable Control Store<br />
Cache = Cache<br />
Primary-cache = Primary cache<br />
Secondary-Cache = Secondary cache<br />
Backup-cache = Backup cache<br />
Compatibility-mode = Whether compatibility mode is implemented or not<br />
Console-processor = Console processor<br />
Console-device = Console storage device<br />
Firmware-version = Firmware version<br />
Console-speed = Console speed<br />
CPU-names = For a multiprocessor system, the list of possible CPU designations<br />
Minimum-memory = Minimum memory<br />
Maximum-memory = Maximum memory<br />
Physical-address-lines = The number of physical address lines<br />
Memory-checking = Memory checking<br />
Memory-cycle = Memory cycle<br />
on-board-memory = On-board memory<br />
Max-I/O-throughput = Max I/O throughput<br />
BUS-SBI = SBI bus details<br />
BUS-MASSBUS = MASSBUS details<br />
BUS-UNIBUS = UNIBUS details<br />
BUS-Qbus = Q-bus details<br />
BUS-vaxbi = VAXBI bus details<br />
BUS-XMI = XMI bus details<br />
BUS-LSB = Laserbus details<br />
BUS-FB = Futurebus details<br />
BUS-TC = TURBOchannel bus details<br />
BUS-DSSI = DSSI bus details<br />
BUS-SCSI = SCSI bus details<br />
LAN-support = Ethernet support details<br />
VUPs = VAX Units of Performance<br />
SPECmarks = SPECmark details<br />
TPC-A = TPC-A details<br />
SPECint89 = SPECint89 details<br />
SPECfp89 = SPECfp89 details<br />
SPECint92 = SPECint92 details<br />
SPECfp92 = SPECfp92 details<br />
SPECint95 = SPECint95 details<br />
SPECfp95 = SPECfp95 details<br />
</pre><br />
</noinclude><br />
<includeonly><br />
{| class="infobox bordered" style="width: 40em; text-align: left; font-size: 90%" align="right"<br />
|-<br />
| colspan="2" style="text-align:center; font-size: large;background-color: lightsteelblue; color: black;" | '''{{{name}}}'''<br />
|-<br />
<br />
{{#if: {{{Announcement|}}} {{{FRS-date|}}} {{{FCS-date|}}} {{{Last-order|}}} {{{Last-ship|}}} {{{EOSL|}}} {{{Codename|}}} {{{Desc-name|}}} {{{Sys-class|}}} {{{OS-support-VMS|}}} {{{OS-support-MDM|}}} {{{OS-support-ELN|}}} {{{OS-support-ULTRIX|}}} |<br />
! colspan="2" style="text-align:center; background-color: powderblue; color: black;" {{!}} Summary }}<br />
|-<br />
<br />
{{#if: {{{Announcement|}}} |<br />
! Announcement date:<br />
{{!}} {{{Announcement}}} }}<br />
|-<br />
<br />
{{#if: {{{FRS-date|}}} |<br />
! FRS date:<br />
{{!}} {{{FRS-date}}} }}<br />
|-<br />
<br />
{{#if: {{{FCS-date|}}} |<br />
! FCS date:<br />
{{!}} {{{FCS-date}}} }}<br />
|-<br />
<br />
{{#if: {{{Last-order|}}} |<br />
! Last order date:<br />
{{!}} {{{Last-order}}} }}<br />
|-<br />
<br />
{{#if: {{{Last-ship|}}} |<br />
! Last ship date:<br />
{{!}} {{{Last-ship}}} }}<br />
|-<br />
<br />
{{#if: {{{EOSL|}}} |<br />
! End of service life:<br />
{{!}} {{{EOSL}}} }}<br />
|-<br />
<br />
{{#if: {{{Codename|}}} |<br />
! Codename:<br />
{{!}} {{{Codename}}} }}<br />
|-<br />
<br />
{{#if: {{{Desc-name|}}} |<br />
! Descriptive name:<br />
{{!}} {{{Desc-name}}} }}<br />
|-<br />
<br />
{{#if: {{{Sys-class|}}} |<br />
! System class:<br />
{{!}} {{{Sys-class}}} }}<br />
|-<br />
<br />
{{#if: {{{OS-support-VMS|}}} |<br />
! OS support (VMS):<br />
{{!}} {{{OS-support-VMS}}} }}<br />
|-<br />
<br />
{{#if: {{{OS-support-MDM|}}} |<br />
! OS support (MDM):<br />
{{!}} {{{OS-support-MDM}}} }}<br />
|-<br />
<br />
{{#if: {{{OS-support-ELN|}}} |<br />
! OS support (ELN):<br />
{{!}} {{{OS-support-ELN}}} }}<br />
|-<br />
<br />
{{#if: {{{OS-support-ULTRIX|}}} |<br />
! OS support (ULTRIX):<br />
{{!}} {{{OS-support-ULTRIX}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-name-VMS|}}} {{{CPU-name-console|}}} {{{CPU-module|}}} {{{Module|}}} {{{Num-proc|}}} {{{VMS-CPU|}}} {{{VMS-XCPU|}}} {{{SID|}}} {{{XSID|}}} {{{CPU-chip|}}} {{{FPU-chip|}}} {{{CPU-technology|}}} {{{CPU-cycle|}}} {{{CPU-clock|}}} {{{CPU-clock-rate|}}} {{{Vector-processor|}}} {{{Instruction-buffer|}}} {{{Translation-buffer|}}} {{{Control-store|}}} {{{Gate-delay|}}} {{{WCS|}}} {{{UWCS|}}} {{{Cache|}}} {{{Primary-cache|}}} {{{Secondary-Cache|}}} {{{Backup-cache|}}} {{{Compatibility-mode|}}} {{{Console-processor|}}} {{{Console-device|}}} {{{Firmware-version|}}} {{{Console-speed|}}} {{{CPU-names|}}} |<br />
! colspan="2" style="text-align:center; background-color: powderblue; color: black;" {{!}} CPU Details }}<br />
|-<br />
<br />
{{#if: {{{CPU-name-VMS|}}} |<br />
! CPU name (VMS):<br />
{{!}} {{{CPU-name-VMS}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-name-console|}}} |<br />
! CPU name (console):<br />
{{!}} {{{CPU-name-console}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-module|}}} |<br />
! CPU module:<br />
{{!}} {{{CPU-module}}} }}<br />
|-<br />
<br />
{{#if: {{{Module|}}} |<br />
! Module:<br />
{{!}} {{{Module}}} }}<br />
|-<br />
<br />
{{#if: {{{Num-proc|}}} |<br />
! Number of processors:<br />
{{!}} {{{Num-proc}}} }}<br />
|-<br />
<br />
{{#if: {{{VMS-CPU|}}} |<br />
! VMS DCL CPU:<br />
{{!}} {{{VMS-CPU}}} }}<br />
|-<br />
<br />
{{#if: {{{VMS-XCPU|}}} |<br />
! VMS DCL XCPU:<br />
{{!}} {{{VMS-XCPU}}} }}<br />
|-<br />
<br />
{{#if: {{{SID|}}} |<br />
! SID:<br />
{{!}} {{{SID}}} }}<br />
|-<br />
<br />
{{#if: {{{XSID|}}} |<br />
! XSID:<br />
{{!}} {{{XSID}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-chip|}}} |<br />
! CPU chip:<br />
{{!}} {{{CPU-chip}}} }}<br />
|-<br />
<br />
{{#if: {{{FPU-chip|}}} |<br />
! FPU chip:<br />
{{!}} {{{FPU-chip}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-technology|}}} |<br />
! CPU technology:<br />
{{!}} {{{CPU-technology}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-cycle|}}} |<br />
! CPU cycle time:<br />
{{!}} {{{CPU-cycle}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-clock|}}} |<br />
! CPU clock:<br />
{{!}} {{{CPU-clock}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-clock-rate|}}} |<br />
! CPU clock rate:<br />
{{!}} {{{CPU-clock-rate}}} }}<br />
|-<br />
<br />
{{#if: {{{Vector-processor|}}} |<br />
! Vector processor:<br />
{{!}} {{{Vector-processor}}} }}<br />
|-<br />
<br />
{{#if: {{{Instruction-buffer|}}} |<br />
! Instruction-buffer:<br />
{{!}} {{{Instruction-buffer}}} }}<br />
|-<br />
<br />
{{#if: {{{Translation-buffer|}}} |<br />
! Translation-buffer:<br />
{{!}} {{{Translation-buffer}}} }}<br />
|-<br />
<br />
{{#if: {{{Control-store|}}} |<br />
! Control store:<br />
{{!}} {{{Control-store}}} }}<br />
|-<br />
<br />
{{#if: {{{Gate-delay|}}} |<br />
! Gate delay:<br />
{{!}} {{{Gate-delay}}} }}<br />
|-<br />
<br />
{{#if: {{{WCS|}}} |<br />
! Writable Control Store:<br />
{{!}} {{{WCS}}} }}<br />
|-<br />
<br />
{{#if: {{{UWCS|}}} |<br />
! User Writable Control Store:<br />
{{!}} {{{UWCS}}} }}<br />
|-<br />
<br />
{{#if: {{{Cache|}}} |<br />
! Cache:<br />
{{!}} {{{Cache}}} }}<br />
|-<br />
<br />
{{#if: {{{Primary-cache|}}} |<br />
! Primary cache:<br />
{{!}} {{{Primary-cache}}} }}<br />
|-<br />
<br />
{{#if: {{{Secondary-Cache|}}} |<br />
! Secondary cache:<br />
{{!}} {{{Secondary-Cache}}} }}<br />
|-<br />
<br />
{{#if: {{{Backup-cache|}}} |<br />
! Backup cache:<br />
{{!}} {{{Backup-cache}}} }}<br />
|-<br />
<br />
{{#if: {{{Compatibility-mode|}}} |<br />
! Compatibility mode:<br />
{{!}} {{{Compatibility-mode}}} }}<br />
|-<br />
<br />
{{#if: {{{Console-processor|}}} |<br />
! Console processor:<br />
{{!}} {{{Console-processor}}} }}<br />
|-<br />
<br />
{{#if: {{{Console-device|}}} |<br />
! Console device:<br />
{{!}} {{{Console-device}}} }}<br />
|-<br />
<br />
{{#if: {{{Firmware-version|}}} |<br />
! Firmware version:<br />
{{!}} {{{Firmware-version}}} }}<br />
|-<br />
<br />
{{#if: {{{Console-speed|}}} |<br />
! Console speed:<br />
{{!}} {{{Console-speed}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-names|}}} |<br />
! CPU-names:<br />
{{!}} {{{CPU-names}}} }}<br />
|-<br />
<br />
{{#if: {{{Minimum-memory|}}} {{{Maximum-memory|}}} {{{Physical-address-lines|}}} {{{Memory-checking|}}} {{{Memory-cycle|}}} {{{on-board-memory|}}} |<br />
! colspan="2" style="text-align:center; background-color: powderblue; color: black;" {{!}} Memory }}<br />
|-<br />
<br />
{{#if: {{{Minimum-memory|}}} |<br />
! Minimum memory:<br />
{{!}} {{{Minimum-memory}}} }}<br />
|-<br />
<br />
{{#if: {{{Maximum-memory|}}} |<br />
! Maximum memory:<br />
{{!}} {{{Maximum-memory}}} }}<br />
|-<br />
<br />
{{#if: {{{Physical-address-lines|}}} |<br />
! Physical address lines:<br />
{{!}} {{{Physical-address-lines}}} }}<br />
|-<br />
<br />
{{#if: {{{Memory-checking|}}} |<br />
! Memory checking:<br />
{{!}} {{{Memory-checking}}} }}<br />
|-<br />
<br />
{{#if: {{{Memory-cycle|}}} |<br />
! Memory cycle:<br />
{{!}} {{{Memory-cycle}}} }}<br />
|-<br />
<br />
{{#if: {{{on-board-memory|}}} |<br />
! On-board memory:<br />
{{!}} {{{on-board-memory}}} }}<br />
|-<br />
<br />
{{#if: {{{Max-I/O-throughput|}}} {{{BUS-SBI|}}} {{{BUS-MASSBUS|}}} {{{BUS-UNIBUS|}}} {{{BUS-Qbus|}}} {{{BUS-vaxbi|}}} {{{BUS-XMI|}}} {{{BUS-LSB|}}} {{{BUS-FB|}}} {{{BUS-TC|}}} {{{BUS-DSSI|}}} {{{BUS-SCSI|}}} {{{LAN-support|}}} |<br />
! colspan="2" style="text-align:center; background-color: powderblue; color: black;" {{!}} I/O }}<br />
|-<br />
<br />
{{#if: {{{Max-I/O-throughput|}}} |<br />
! Max I/O throughput:<br />
{{!}} {{{Max-I/O-throughput}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-SBI|}}} |<br />
! SBI:<br />
{{!}} {{{BUS-SBI}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-MASSBUS|}}} |<br />
! MASSBUS:<br />
{{!}} {{{BUS-MASSBUS}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-UNIBUS|}}} |<br />
! UNIBUS:<br />
{{!}} {{{BUS-UNIBUS}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-Qbus|}}} |<br />
! Q-bus:<br />
{{!}} {{{BUS-Qbus}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-vaxbi|}}} |<br />
! VAXBI:<br />
{{!}} {{{BUS-vaxbi}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-XMI|}}} |<br />
! XMI:<br />
{{!}} {{{BUS-XMI}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-LSB|}}} |<br />
! Laserbus:<br />
{{!}} {{{BUS-LSB}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-FB|}}} |<br />
! Futurebus:<br />
{{!}} {{{BUS-FB}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-TC|}}} |<br />
! TURBOchannel:<br />
{{!}} {{{BUS-TC}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-DSSI|}}} |<br />
! BUS-DSSI:<br />
{{!}} {{{BUS-DSSI}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-SCSI|}}} |<br />
! BUS SCSI:<br />
{{!}} {{{BUS-SCSI}}} }}<br />
|-<br />
<br />
{{#if: {{{LAN-support|}}} |<br />
! LAN support:<br />
{{!}} {{{LAN-support}}} }}<br />
|-<br />
<br />
{{#if: {{{VUPs|}}} {{{SPECmarks|}}} {{{TPC-A|}}} {{{SPECint89|}}} {{{SPECfp89|}}} {{{SPECint92|}}} {{{SPECfp92|}}} {{{SPECint95|}}} {{{SPECfp95|}}} |<br />
! colspan="2" style="text-align:center; background-color: powderblue; color: black;" {{!}} Performance }}<br />
|-<br />
<br />
{{#if: {{{VUPs|}}} |<br />
! [[VUP|VUPs]]:<br />
{{!}} {{{VUPs}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECmarks|}}} |<br />
! SPECmarks:<br />
{{!}} {{{SPECmarks}}} }}<br />
|-<br />
<br />
{{#if: {{{TPC-A|}}} |<br />
! TPC-A:<br />
{{!}} {{{TPC-A}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECint89|}}} |<br />
! SPECint89:<br />
{{!}} {{{SPECint89}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECfp89|}}} |<br />
! SPECfp89:<br />
{{!}} {{{SPECfp89}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECint92|}}} |<br />
! SPECint92:<br />
{{!}} {{{SPECint92}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECfp92|}}} |<br />
! SPECfp92:<br />
{{!}} {{{SPECfp92}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECint95|}}} |<br />
! SPECint95:<br />
{{!}} {{{SPECint95}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECfp95|}}} |<br />
! SPECfp95:<br />
{{!}} {{{SPECfp95}}} }}<br />
|}<br />
<br />
[[Category:DEC VAX Processors|{{{name}}}]]<br />
</includeonly></div>
Jzatarski
https://gunkies.org/w/index.php?title=Category:VAX_Processors&diff=21843
Category:VAX Processors
2019-11-23T19:54:04Z
<p>Jzatarski: Undo revision 21842 by Jzatarski (talk)</p>
<hr />
<div>#REDIRECT [[:Category:DEC VAX Processors]]</div>
Jzatarski
https://gunkies.org/w/index.php?title=Category:VAX_Processors&diff=21842
Category:VAX Processors
2019-11-23T19:53:53Z
<p>Jzatarski: Blanked the page</p>
<hr />
<div></div>
Jzatarski
https://gunkies.org/w/index.php?title=Category:DEC_VAX_Processors&diff=21840
Category:DEC VAX Processors
2019-11-23T19:53:08Z
<p>Jzatarski: Jzatarski moved page Category:VAX Processors to Category:DEC VAX Processors</p>
<hr />
<div>[[VAX]] [[Central Processing Unit|CPUs]]<br />
<br />
[[Category: VAXen]]<br />
[[Category: DEC Processors]]</div>
Jzatarski
https://gunkies.org/w/index.php?title=Category:VAX_Processors&diff=21841
Category:VAX Processors
2019-11-23T19:53:08Z
<p>Jzatarski: Jzatarski moved page Category:VAX Processors to Category:DEC VAX Processors</p>
<hr />
<div>#REDIRECT [[:Category:DEC VAX Processors]]</div>
Jzatarski
https://gunkies.org/w/index.php?title=Category:DEC_VAX_Processors&diff=21839
Category:DEC VAX Processors
2019-11-23T19:51:53Z
<p>Jzatarski: Creation of category</p>
<hr />
<div>[[VAX]] [[Central Processing Unit|CPUs]]<br />
<br />
[[Category: VAXen]]<br />
[[Category: DEC Processors]]</div>
Jzatarski
https://gunkies.org/w/index.php?title=Template:InfoboxVAXCPU-Data&diff=21838
Template:InfoboxVAXCPU-Data
2019-11-23T19:43:20Z
<p>Jzatarski: Creation of the template, based on InfoboxVAX-Data</p>
<hr />
<div><noinclude><br />
This template is for any VAX CPU. It is based off of Template:InfoboxVAX-Data. Some of the fields thus may not apply directly to a CPU.<br />
<br />
<pre><br />
name = the name of the CPU<br />
Announcement = Announcement date<br />
FRS-date = First revenue ship date<br />
FCS-date = First customer ship date<br />
Last-order = Last order date<br />
Last-ship = Last ship date<br />
EOSL = End of service life<br />
Codename = Codename<br />
Desc-name = Descriptive name<br />
Sys-class = System class<br />
OS-support-VMS = Range of VMS versions that support this system<br />
OS-support-MDM = Range of MDM releases that support this system<br />
OS-support-ELN = Range of VAXELN releases that support this system<br />
OS-support-ULTRIX = Range of ULTRIX versions that support this system<br />
CPU-name-VMS = CPU name as reported by ANALYZE/ERROR under VMS<br />
CPU-name-console = CPU name as reported by the console<br />
CPU-module = The CPU module<br />
Module = The system module part number<br />
Num-proc = Number of processors<br />
VMS-CPU = The hexadecimal value returned by the DCL function F$GETSYI("SID") under VMS.<br />
VMS-XCPU = The hexadecimal value returned by the DCL function F$GETSYI("XSID") under VMS.<br />
SID = The System Identification register<br />
XSID = The System Extended Identification register<br />
CPU-chip = The chip that implements the I-box (CPU)<br />
FPU-chip = The chip that implements the F-box (FPU)<br />
CPU-technology = The technology with which the CPU is fabricated<br />
CPU-cycle = The CPU cycle time<br />
CPU-clock = The CPU clock rate<br />
CPU-clock-rate = The raw clock that is supplied to the CPU<br />
Vector-processor = Vector processor<br />
Instruction-buffer = Instruction prefetch queue size<br />
Translation-buffer = The CPU translation buffer size<br />
Control-store = Microcode control store details<br />
Gate-delay = Gate delay<br />
WCS = Writable Control Store<br />
UWCS = User Writable Control Store<br />
Cache = Cache<br />
Primary-cache = Primary cache<br />
Secondary-Cache = Secondary cache<br />
Backup-cache = Backup cache<br />
Compatibility-mode = Whether compatibility mode is implemented or not<br />
Console-processor = Console processor<br />
Console-device = Console storage device<br />
Firmware-version = Firmware version<br />
Console-speed = Console speed<br />
CPU-names = For a multiprocessor system, the list of possible CPU designations<br />
Minimum-memory = Minimum memory<br />
Maximum-memory = Maximum memory<br />
Physical-address-lines = The number of physical address lines<br />
Memory-checking = Memory checking<br />
Memory-cycle = Memory cycle<br />
on-board-memory = On-board memory<br />
Max-I/O-throughput = Max I/O throughput<br />
BUS-SBI = SBI bus details<br />
BUS-MASSBUS = MASSBUS details<br />
BUS-UNIBUS = UNIBUS details<br />
BUS-Qbus = Q-bus details<br />
BUS-vaxbi = VAXBI bus details<br />
BUS-XMI = XMI bus details<br />
BUS-LSB = Laserbus details<br />
BUS-FB = Futurebus details<br />
BUS-TC = TURBOchannel bus details<br />
BUS-DSSI = DSSI bus details<br />
BUS-SCSI = SCSI bus details<br />
LAN-support = Ethernet support details<br />
VUPs = VAX Units of Performance<br />
SPECmarks = SPECmark details<br />
TPC-A = TPC-A details<br />
SPECint89 = SPECint89 details<br />
SPECfp89 = SPECfp89 details<br />
SPECint92 = SPECint92 details<br />
SPECfp92 = SPECfp92 details<br />
SPECint95 = SPECint95 details<br />
SPECfp95 = SPECfp95 details<br />
</pre><br />
</noinclude><br />
<includeonly><br />
{| class="infobox bordered" style="width: 40em; text-align: left; font-size: 90%" align="right"<br />
|-<br />
| colspan="2" style="text-align:center; font-size: large;background-color: lightsteelblue; color: black;" | '''{{{name}}}'''<br />
|-<br />
<br />
{{#if: {{{Announcement|}}} {{{FRS-date|}}} {{{FCS-date|}}} {{{Last-order|}}} {{{Last-ship|}}} {{{EOSL|}}} {{{Codename|}}} {{{Desc-name|}}} {{{Sys-class|}}} {{{OS-support-VMS|}}} {{{OS-support-MDM|}}} {{{OS-support-ELN|}}} {{{OS-support-ULTRIX|}}} |<br />
! colspan="2" style="text-align:center; background-color: powderblue; color: black;" {{!}} Summary }}<br />
|-<br />
<br />
{{#if: {{{Announcement|}}} |<br />
! Announcement date:<br />
{{!}} {{{Announcement}}} }}<br />
|-<br />
<br />
{{#if: {{{FRS-date|}}} |<br />
! FRS date:<br />
{{!}} {{{FRS-date}}} }}<br />
|-<br />
<br />
{{#if: {{{FCS-date|}}} |<br />
! FCS date:<br />
{{!}} {{{FCS-date}}} }}<br />
|-<br />
<br />
{{#if: {{{Last-order|}}} |<br />
! Last order date:<br />
{{!}} {{{Last-order}}} }}<br />
|-<br />
<br />
{{#if: {{{Last-ship|}}} |<br />
! Last ship date:<br />
{{!}} {{{Last-ship}}} }}<br />
|-<br />
<br />
{{#if: {{{EOSL|}}} |<br />
! End of service life:<br />
{{!}} {{{EOSL}}} }}<br />
|-<br />
<br />
{{#if: {{{Codename|}}} |<br />
! Codename:<br />
{{!}} {{{Codename}}} }}<br />
|-<br />
<br />
{{#if: {{{Desc-name|}}} |<br />
! Descriptive name:<br />
{{!}} {{{Desc-name}}} }}<br />
|-<br />
<br />
{{#if: {{{Sys-class|}}} |<br />
! System class:<br />
{{!}} {{{Sys-class}}} }}<br />
|-<br />
<br />
{{#if: {{{OS-support-VMS|}}} |<br />
! OS support (VMS):<br />
{{!}} {{{OS-support-VMS}}} }}<br />
|-<br />
<br />
{{#if: {{{OS-support-MDM|}}} |<br />
! OS support (MDM):<br />
{{!}} {{{OS-support-MDM}}} }}<br />
|-<br />
<br />
{{#if: {{{OS-support-ELN|}}} |<br />
! OS support (ELN):<br />
{{!}} {{{OS-support-ELN}}} }}<br />
|-<br />
<br />
{{#if: {{{OS-support-ULTRIX|}}} |<br />
! OS support (ULTRIX):<br />
{{!}} {{{OS-support-ULTRIX}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-name-VMS|}}} {{{CPU-name-console|}}} {{{CPU-module|}}} {{{Module|}}} {{{Num-proc|}}} {{{VMS-CPU|}}} {{{VMS-XCPU|}}} {{{SID|}}} {{{XSID|}}} {{{CPU-chip|}}} {{{FPU-chip|}}} {{{CPU-technology|}}} {{{CPU-cycle|}}} {{{CPU-clock|}}} {{{CPU-clock-rate|}}} {{{Vector-processor|}}} {{{Instruction-buffer|}}} {{{Translation-buffer|}}} {{{Control-store|}}} {{{Gate-delay|}}} {{{WCS|}}} {{{UWCS|}}} {{{Cache|}}} {{{Primary-cache|}}} {{{Secondary-Cache|}}} {{{Backup-cache|}}} {{{Compatibility-mode|}}} {{{Console-processor|}}} {{{Console-device|}}} {{{Firmware-version|}}} {{{Console-speed|}}} {{{CPU-names|}}} |<br />
! colspan="2" style="text-align:center; background-color: powderblue; color: black;" {{!}} CPU Details }}<br />
|-<br />
<br />
{{#if: {{{CPU-name-VMS|}}} |<br />
! CPU name (VMS):<br />
{{!}} {{{CPU-name-VMS}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-name-console|}}} |<br />
! CPU name (console):<br />
{{!}} {{{CPU-name-console}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-module|}}} |<br />
! CPU module:<br />
{{!}} {{{CPU-module}}} }}<br />
|-<br />
<br />
{{#if: {{{Module|}}} |<br />
! Module:<br />
{{!}} {{{Module}}} }}<br />
|-<br />
<br />
{{#if: {{{Num-proc|}}} |<br />
! Number of processors:<br />
{{!}} {{{Num-proc}}} }}<br />
|-<br />
<br />
{{#if: {{{VMS-CPU|}}} |<br />
! VMS DCL CPU:<br />
{{!}} {{{VMS-CPU}}} }}<br />
|-<br />
<br />
{{#if: {{{VMS-XCPU|}}} |<br />
! VMS DCL XCPU:<br />
{{!}} {{{VMS-XCPU}}} }}<br />
|-<br />
<br />
{{#if: {{{SID|}}} |<br />
! SID:<br />
{{!}} {{{SID}}} }}<br />
|-<br />
<br />
{{#if: {{{XSID|}}} |<br />
! XSID:<br />
{{!}} {{{XSID}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-chip|}}} |<br />
! CPU chip:<br />
{{!}} {{{CPU-chip}}} }}<br />
|-<br />
<br />
{{#if: {{{FPU-chip|}}} |<br />
! FPU chip:<br />
{{!}} {{{FPU-chip}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-technology|}}} |<br />
! CPU technology:<br />
{{!}} {{{CPU-technology}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-cycle|}}} |<br />
! CPU cycle time:<br />
{{!}} {{{CPU-cycle}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-clock|}}} |<br />
! CPU clock:<br />
{{!}} {{{CPU-clock}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-clock-rate|}}} |<br />
! CPU clock rate:<br />
{{!}} {{{CPU-clock-rate}}} }}<br />
|-<br />
<br />
{{#if: {{{Vector-processor|}}} |<br />
! Vector processor:<br />
{{!}} {{{Vector-processor}}} }}<br />
|-<br />
<br />
{{#if: {{{Instruction-buffer|}}} |<br />
! Instruction-buffer:<br />
{{!}} {{{Instruction-buffer}}} }}<br />
|-<br />
<br />
{{#if: {{{Translation-buffer|}}} |<br />
! Translation-buffer:<br />
{{!}} {{{Translation-buffer}}} }}<br />
|-<br />
<br />
{{#if: {{{Control-store|}}} |<br />
! Control store:<br />
{{!}} {{{Control-store}}} }}<br />
|-<br />
<br />
{{#if: {{{Gate-delay|}}} |<br />
! Gate delay:<br />
{{!}} {{{Gate-delay}}} }}<br />
|-<br />
<br />
{{#if: {{{WCS|}}} |<br />
! Writable Control Store:<br />
{{!}} {{{WCS}}} }}<br />
|-<br />
<br />
{{#if: {{{UWCS|}}} |<br />
! User Writable Control Store:<br />
{{!}} {{{UWCS}}} }}<br />
|-<br />
<br />
{{#if: {{{Cache|}}} |<br />
! Cache:<br />
{{!}} {{{Cache}}} }}<br />
|-<br />
<br />
{{#if: {{{Primary-cache|}}} |<br />
! Primary cache:<br />
{{!}} {{{Primary-cache}}} }}<br />
|-<br />
<br />
{{#if: {{{Secondary-Cache|}}} |<br />
! Secondary cache:<br />
{{!}} {{{Secondary-Cache}}} }}<br />
|-<br />
<br />
{{#if: {{{Backup-cache|}}} |<br />
! Backup cache:<br />
{{!}} {{{Backup-cache}}} }}<br />
|-<br />
<br />
{{#if: {{{Compatibility-mode|}}} |<br />
! Compatibility mode:<br />
{{!}} {{{Compatibility-mode}}} }}<br />
|-<br />
<br />
{{#if: {{{Console-processor|}}} |<br />
! Console processor:<br />
{{!}} {{{Console-processor}}} }}<br />
|-<br />
<br />
{{#if: {{{Console-device|}}} |<br />
! Console device:<br />
{{!}} {{{Console-device}}} }}<br />
|-<br />
<br />
{{#if: {{{Firmware-version|}}} |<br />
! Firmware version:<br />
{{!}} {{{Firmware-version}}} }}<br />
|-<br />
<br />
{{#if: {{{Console-speed|}}} |<br />
! Console speed:<br />
{{!}} {{{Console-speed}}} }}<br />
|-<br />
<br />
{{#if: {{{CPU-names|}}} |<br />
! CPU-names:<br />
{{!}} {{{CPU-names}}} }}<br />
|-<br />
<br />
{{#if: {{{Minimum-memory|}}} {{{Maximum-memory|}}} {{{Physical-address-lines|}}} {{{Memory-checking|}}} {{{Memory-cycle|}}} {{{on-board-memory|}}} |<br />
! colspan="2" style="text-align:center; background-color: powderblue; color: black;" {{!}} Memory }}<br />
|-<br />
<br />
{{#if: {{{Minimum-memory|}}} |<br />
! Minimum memory:<br />
{{!}} {{{Minimum-memory}}} }}<br />
|-<br />
<br />
{{#if: {{{Maximum-memory|}}} |<br />
! Maximum memory:<br />
{{!}} {{{Maximum-memory}}} }}<br />
|-<br />
<br />
{{#if: {{{Physical-address-lines|}}} |<br />
! Physical address lines:<br />
{{!}} {{{Physical-address-lines}}} }}<br />
|-<br />
<br />
{{#if: {{{Memory-checking|}}} |<br />
! Memory checking:<br />
{{!}} {{{Memory-checking}}} }}<br />
|-<br />
<br />
{{#if: {{{Memory-cycle|}}} |<br />
! Memory cycle:<br />
{{!}} {{{Memory-cycle}}} }}<br />
|-<br />
<br />
{{#if: {{{on-board-memory|}}} |<br />
! On-board memory:<br />
{{!}} {{{on-board-memory}}} }}<br />
|-<br />
<br />
{{#if: {{{Max-I/O-throughput|}}} {{{BUS-SBI|}}} {{{BUS-MASSBUS|}}} {{{BUS-UNIBUS|}}} {{{BUS-Qbus|}}} {{{BUS-vaxbi|}}} {{{BUS-XMI|}}} {{{BUS-LSB|}}} {{{BUS-FB|}}} {{{BUS-TC|}}} {{{BUS-DSSI|}}} {{{BUS-SCSI|}}} {{{LAN-support|}}} |<br />
! colspan="2" style="text-align:center; background-color: powderblue; color: black;" {{!}} I/O }}<br />
|-<br />
<br />
{{#if: {{{Max-I/O-throughput|}}} |<br />
! Max I/O throughput:<br />
{{!}} {{{Max-I/O-throughput}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-SBI|}}} |<br />
! SBI:<br />
{{!}} {{{BUS-SBI}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-MASSBUS|}}} |<br />
! MASSBUS:<br />
{{!}} {{{BUS-MASSBUS}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-UNIBUS|}}} |<br />
! UNIBUS:<br />
{{!}} {{{BUS-UNIBUS}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-Qbus|}}} |<br />
! Q-bus:<br />
{{!}} {{{BUS-Qbus}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-vaxbi|}}} |<br />
! VAXBI:<br />
{{!}} {{{BUS-vaxbi}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-XMI|}}} |<br />
! XMI:<br />
{{!}} {{{BUS-XMI}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-LSB|}}} |<br />
! Laserbus:<br />
{{!}} {{{BUS-LSB}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-FB|}}} |<br />
! Futurebus:<br />
{{!}} {{{BUS-FB}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-TC|}}} |<br />
! TURBOchannel:<br />
{{!}} {{{BUS-TC}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-DSSI|}}} |<br />
! BUS-DSSI:<br />
{{!}} {{{BUS-DSSI}}} }}<br />
|-<br />
<br />
{{#if: {{{BUS-SCSI|}}} |<br />
! BUS SCSI:<br />
{{!}} {{{BUS-SCSI}}} }}<br />
|-<br />
<br />
{{#if: {{{LAN-support|}}} |<br />
! LAN support:<br />
{{!}} {{{LAN-support}}} }}<br />
|-<br />
<br />
{{#if: {{{VUPs|}}} {{{SPECmarks|}}} {{{TPC-A|}}} {{{SPECint89|}}} {{{SPECfp89|}}} {{{SPECint92|}}} {{{SPECfp92|}}} {{{SPECint95|}}} {{{SPECfp95|}}} |<br />
! colspan="2" style="text-align:center; background-color: powderblue; color: black;" {{!}} Performance }}<br />
|-<br />
<br />
{{#if: {{{VUPs|}}} |<br />
! [[VUP|VUPs]]:<br />
{{!}} {{{VUPs}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECmarks|}}} |<br />
! SPECmarks:<br />
{{!}} {{{SPECmarks}}} }}<br />
|-<br />
<br />
{{#if: {{{TPC-A|}}} |<br />
! TPC-A:<br />
{{!}} {{{TPC-A}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECint89|}}} |<br />
! SPECint89:<br />
{{!}} {{{SPECint89}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECfp89|}}} |<br />
! SPECfp89:<br />
{{!}} {{{SPECfp89}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECint92|}}} |<br />
! SPECint92:<br />
{{!}} {{{SPECint92}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECfp92|}}} |<br />
! SPECfp92:<br />
{{!}} {{{SPECfp92}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECint95|}}} |<br />
! SPECint95:<br />
{{!}} {{{SPECint95}}} }}<br />
|-<br />
<br />
{{#if: {{{SPECfp95|}}} |<br />
! SPECfp95:<br />
{{!}} {{{SPECfp95}}} }}<br />
|}<br />
<br />
[[Category:DEC VAX systems|{{{name}}}]]<br />
</includeonly></div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_CPU&diff=21837
KA650 CPU
2019-11-23T17:43:14Z
<p>Jzatarski: Remove VAX computer nav section, does not belong on CPU page.</p>
<hr />
<div>{{InfoboxVAX-Data<br />
| name = KA650<br />
| OS-support-VMS = V4.7A or later<br />
| OS-support-ULTRIX = ULTRIX V2.2<br />
| CPU-name-VMS = KA650<br />
| CPU-module = KA650<br />
| Module = M7620 [[#ref_3|[3]]]<br />
| Num-proc = 1<br />
| VMS-CPU = 10<br />
| VMS-XCPU = 1<br />
| SID = 0A000005<br />
| XSID = 01530101<br />
| CPU-chip = 78034 (CVAX) [[#ref_1|[1]]]<br />
| FPU-chip = 78132<br />
| CPU-technology = CMOS<br />
| CPU-cycle = 90ns [[#ref_4|[4]]]<br />
| Instruction-buffer = 12 bytes [[#ref_1|[1]]]<br />
| Translation-buffer = 28 entries [[#ref_1|[1]]]<br />
| Cache = 1KB (90ns) [[#ref_1|[1]]]<br />
| Backup-cache = 64KB (180ns longword, 270ns quadword) [[#ref_4|[4]]]<br />
| Compatibility-mode = No<br />
| Console-processor = CPU<br />
| Console-device = None<br />
| Firmware-version = V5.3<br />
| Console-speed = 300 to 38400<br />
| Minimum-memory = 8MB<br />
| Maximum-memory = 64MB<br />
| Memory-checking = 32 + 7 bit ECC [[#ref_4|[4]]]<br />
| Memory-cycle = 450ns longword, 720ns quadword [[#ref_4|[4]]]<br />
| BUS-Qbus = 1 @ 3.3MB/s<br />
| VUPs = 2.7 [[#ref_2|[2]]]<br />
}}<br />
<br />
== References ==<br />
<br />
<div id="ref_1">[1] "CVAX-based Systems", Digital Technical Journal, Vol 1 No 7, August 1988. </div><br />
<div id="ref_2">[2] VAXcluster Systems. Guidelines for VAXCluster System Configurations. EK-VAXCT-CG-006</div><br />
<div id="ref_3">[3] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="ref_4">[4] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div><br />
<br />
{{stub}}</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_CPU&diff=21836
KA650 CPU
2019-11-23T17:41:21Z
<p>Jzatarski: lost a ']' on a citation reference</p>
<hr />
<div>{{InfoboxVAX-Data<br />
| name = KA650<br />
| OS-support-VMS = V4.7A or later<br />
| OS-support-ULTRIX = ULTRIX V2.2<br />
| CPU-name-VMS = KA650<br />
| CPU-module = KA650<br />
| Module = M7620 [[#ref_3|[3]]]<br />
| Num-proc = 1<br />
| VMS-CPU = 10<br />
| VMS-XCPU = 1<br />
| SID = 0A000005<br />
| XSID = 01530101<br />
| CPU-chip = 78034 (CVAX) [[#ref_1|[1]]]<br />
| FPU-chip = 78132<br />
| CPU-technology = CMOS<br />
| CPU-cycle = 90ns [[#ref_4|[4]]]<br />
| Instruction-buffer = 12 bytes [[#ref_1|[1]]]<br />
| Translation-buffer = 28 entries [[#ref_1|[1]]]<br />
| Cache = 1KB (90ns) [[#ref_1|[1]]]<br />
| Backup-cache = 64KB (180ns longword, 270ns quadword) [[#ref_4|[4]]]<br />
| Compatibility-mode = No<br />
| Console-processor = CPU<br />
| Console-device = None<br />
| Firmware-version = V5.3<br />
| Console-speed = 300 to 38400<br />
| Minimum-memory = 8MB<br />
| Maximum-memory = 64MB<br />
| Memory-checking = 32 + 7 bit ECC [[#ref_4|[4]]]<br />
| Memory-cycle = 450ns longword, 720ns quadword [[#ref_4|[4]]]<br />
| BUS-Qbus = 1 @ 3.3MB/s<br />
| VUPs = 2.7 [[#ref_2|[2]]]<br />
}}<br />
<br />
== References ==<br />
<br />
<div id="ref_1">[1] "CVAX-based Systems", Digital Technical Journal, Vol 1 No 7, August 1988. </div><br />
<div id="ref_2">[2] VAXcluster Systems. Guidelines for VAXCluster System Configurations. EK-VAXCT-CG-006</div><br />
<div id="ref_3">[3] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="ref_4">[4] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div><br />
<br />
{{stub}}<br />
<br />
{{Nav VAX}}</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_CPU&diff=21834
KA650 CPU
2019-11-23T17:20:36Z
<p>Jzatarski: Added some specs</p>
<hr />
<div>{{InfoboxVAX-Data<br />
| name = KA650<br />
| OS-support-VMS = V4.7A or later<br />
| OS-support-ULTRIX = ULTRIX V2.2<br />
| CPU-name-VMS = KA650<br />
| CPU-module = KA650<br />
| Module = M7620 [[#ref_3|[3]]]<br />
| Num-proc = 1<br />
| VMS-CPU = 10<br />
| VMS-XCPU = 1<br />
| SID = 0A000005<br />
| XSID = 01530101<br />
| CPU-chip = 78034 (CVAX) [[#ref_1|[1]]]<br />
| FPU-chip = 78132<br />
| CPU-technology = CMOS<br />
| CPU-cycle = 90ns [[#ref_4|[4]]]<br />
| Instruction-buffer = 12 bytes [[#ref_1|[1]]]<br />
| Translation-buffer = 28 entries [[#ref_1|[1]]]<br />
| Cache = 1KB (90ns) [[#ref_1|[1]]]<br />
| Backup-cache = 64KB (180ns longword, 270ns quadword) [[#ref_4|[4]]<br />
| Compatibility-mode = No<br />
| Console-processor = CPU<br />
| Console-device = None<br />
| Firmware-version = V5.3<br />
| Console-speed = 300 to 38400<br />
| Minimum-memory = 8MB<br />
| Maximum-memory = 64MB<br />
| Memory-checking = 32 + 7 bit ECC [[#ref_4|[4]]]<br />
| Memory-cycle = 450ns longword, 720ns quadword [[#ref_4|[4]]]<br />
| BUS-Qbus = 1 @ 3.3MB/s<br />
| VUPs = 2.7 [[#ref_2|[2]]]<br />
}}<br />
<br />
== References ==<br />
<br />
<div id="ref_1">[1] "CVAX-based Systems", Digital Technical Journal, Vol 1 No 7, August 1988. </div><br />
<div id="ref_2">[2] VAXcluster Systems. Guidelines for VAXCluster System Configurations. EK-VAXCT-CG-006</div><br />
<div id="ref_3">[3] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="ref_4">[4] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div><br />
<br />
{{stub}}<br />
<br />
{{Nav VAX}}</div>
Jzatarski
https://gunkies.org/w/index.php?title=KA650_CPU&diff=21833
KA650 CPU
2019-11-23T16:58:25Z
<p>Jzatarski: copy KA650 data from MicroVAX 3500/3600 page (with some cleanup for CPU-centric page)</p>
<hr />
<div>{{InfoboxVAX-Data<br />
| name = KA650<br />
| OS-support-VMS = V4.7A or later<br />
| OS-support-ULTRIX = ULTRIX V2.2<br />
| CPU-name-VMS = KA650<br />
| CPU-module = KA650<br />
| Module = M7620 [[#ref_3|[3]]]<br />
| Num-proc = 1<br />
| VMS-CPU = 10<br />
| VMS-XCPU = 1<br />
| SID = 0A000005<br />
| XSID = 01530101<br />
| CPU-chip = 78034 (CVAX) [[#ref_1|[1]]]<br />
| FPU-chip = 78132<br />
| CPU-technology = CMOS<br />
| CPU-cycle = 90ns [[#ref_4|[4]]]<br />
| Instruction-buffer = 12 bytes [[#ref_1|[1]]]<br />
| Translation-buffer = 28 entries [[#ref_1|[1]]]<br />
| Cache = 1KB (90ns) [[#ref_1|[1]]]<br />
| Backup-cache = 64KB (180ns) [[#ref_1|[1]]]<br />
| Compatibility-mode = No<br />
| Console-processor = CPU<br />
| Console-device = None<br />
| Firmware-version = V5.3<br />
| Minimum-memory = 8MB<br />
| Maximum-memory = 64MB<br />
| BUS-Qbus = 1 @ 3.3MB/s<br />
| VUPs = 2.7 [[#ref_2|[2]]]<br />
}}<br />
<br />
== References ==<br />
<br />
<div id="ref_1">[1] "CVAX-based Systems", Digital Technical Journal, Vol 1 No 7, August 1988. </div><br />
<div id="ref_2">[2] VAXcluster Systems. Guidelines for VAXCluster System Configurations. EK-VAXCT-CG-006</div><br />
<div id="ref_3">[3] Field Maintenance Print Set: 650QS Pedestal, BA213. MP-02538-01</div><br />
<div id="ref_4">[4] KA650 CPU Module Technical Manual. EK-KA650-UG.003</div><br />
<br />
{{stub}}<br />
<br />
{{Nav VAX}}</div>
Jzatarski
https://gunkies.org/w/index.php?title=MicroVAX_3500/3600&diff=21832
MicroVAX 3500/3600
2019-11-23T16:57:17Z
<p>Jzatarski: fixed VUPs in data table. was not appearing.</p>
<hr />
<div>{{InfoboxVAX-Data<br />
| name = MicroVAX 3500/3600<br />
| Announcement = 9 September 1987<br />
| Codename = Mayfair<br />
| OS-support-VMS = V4.7A or later<br />
| OS-support-ULTRIX = ULTRIX V2.2<br />
| CPU-name-VMS = KA650<br />
| CPU-name-console = KA650-A<br />
| CPU-module = KA650<br />
| Module = M7620<br />
| Num-proc = 1<br />
| VMS-CPU = 10<br />
| VMS-XCPU = 1<br />
| SID = 0A000005<br />
| XSID = 01530101<br />
| CPU-chip = 78034 (CVAX) [[#ref_2|[2]]]<br />
| FPU-chip = 78132<br />
| CPU-technology = CMOS<br />
| CPU-cycle = 90ns [[#ref_2|[2]]]<br />
| Instruction-buffer = 12 bytes [[#ref_2|[2]]]<br />
| Translation-buffer = 28 entries [[#ref_2|[2]]]<br />
| Cache = 1KB (90ns) [[#ref_2|[2]]]<br />
| Backup-cache = 64KB (180ns) [[#ref_2|[2]]]<br />
| Compatibility-mode = No<br />
| Console-processor = CPU<br />
| Console-device = None<br />
| Firmware-version = V5.3<br />
| Minimum-memory = 2MB<br />
| Maximum-memory = 64MB<br />
| BUS-Qbus = 1 @ 3.3MB/s<br />
| LAN-support = optional<br />
| VUPs = 2.7 [[#ref_4|[4]]]<br />
}}<br />
<br />
[[Image:MicrVAX 3600.jpg|thumb|left|150px|A MicroVAX 3600]]<br />
<br />
The '''MicroVAX 3500''' and '''MicroVAX 3600''' are very similar; the only distinction appears to be the enclosure: the 3500 was available in the BA213, and the 3600 in the H9644. The bus used was the [[QBUS]].<br />
<br />
==External links==<br />
<br />
* [http://www.ext.zx.net.nz/computers/dec/microvax3500/docs MicroVAX 3500 documentation]<br />
<br />
== References ==<br />
<br />
<div id="ref_1">[1] Special Sales Update. Sep 1987. </div><br />
<div id="ref_2">[2] "CVAX-based Systems", Digital Technical Journal, Vol 1 No 7, August 1988. </div><br />
<div id="ref_3">[3] VAX Systems Hardware Handbook -- VAXBI Systems. EB-31692-46</div><br />
<div id="ref_4">[4] VAXcluster Systems. Guidelines for VAXCluster System Configurations. EK-VAXCT-CG-006</div><br />
<br />
{{stub}}<br />
<br />
{{Nav VAX}}</div>
Jzatarski
https://gunkies.org/w/index.php?title=User:Jzatarski&diff=21831
User:Jzatarski
2019-11-23T16:21:22Z
<p>Jzatarski: </p>
<hr />
<div>I've always had an interest in electronics for as long as I can remember. I started with Radioshack kits and the like when I was younger, where I learned about analog and digital electronics. Between these kits, my own research on the internet, and help from my father (a degreed electrical engineer), I was able to gain a firm footing in electronics years ahead of attending the University of Illinois at Urbana-Champaign where I earned my BSEE. Some time in high school, I purchased a used Atari 400 computer to mess around with software development and later hardware modifications. I now own several Atari computers and have since expanded into whatever I find interesting that I can get my hands on for a reasonable price.<br />
<br />
==Interests==<br />
<br />
This list is far from complete, and is not presented in any particular order.<br />
<br />
* DEC VAX and PDP-11 systems<br />
* Atari 8-bit computers (400/800/XL/XE)<br />
* Motorola 68000<br />
* Intel 8080/8085 and Zilog Z-80<br />
* Analog and TDM digital telephony (VoIP is only a necessary evil)<br />
* Dumb terminals (E.g. DEC VT line)<br />
* Vintage data networking (E.g. 10BASE5, T1 data connections, voiceband telephone modems)<br />
* Electronic test equipment</div>
Jzatarski
https://gunkies.org/w/index.php?title=User:Jzatarski&diff=21830
User:Jzatarski
2019-11-23T16:19:02Z
<p>Jzatarski: Created page with "I've always had an interest in electronics for as long as I can remember. I started with Radioshack kits and the like when I was younger, where I learned about analog and digi..."</p>
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<div>I've always had an interest in electronics for as long as I can remember. I started with Radioshack kits and the like when I was younger, where I learned about analog and digital electronics. Between these kits, my own research on the internet, and help from my father (a degreed electrical engineer), I was able to gain a firm footing in electronics years ahead of attending the University of Illinois at Urbana-Champaign where I earned my BSEE. Some time in high school, I purchased a used Atari 400 computer to mess around with software development and later hardware modifications. I now own several Atari computers and have since expanded into whatever I find interesting that I can get my hands on for a reasonable price.<br />
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==Interests==<br />
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This list is far from complete, and is not presented in any particular order.<br />
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* DEC VAX and PDP-11 systems<br />
* Atari 8-bit computers (400/800/XL/XE)<br />
* Motorola 68000<br />
* Intel 8080/8085 and Zilog Z-80<br />
* Analog and TDM digital telephony (VoIP is only a necessary evil)<br />
* Dumb terminals (E.g. DEC VT line)<br />
* Vintage data networking (E.g. 10BASE5, T1 data connections, voiceband telephone modems)</div>
Jzatarski