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ANTS/ISI IMP Interface - Revision history
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Jnc: What we've got for now
2021-11-12T21:27:43Z
<p>What we've got for now</p>
<p><b>New page</b></p><div>The '''ANTS IMP Interface''' and '''ISI IMP Interface''' were two mostly-[[program compatible]] [[IMP interface]]s, the former produced as part of the [[ANTS terminal system|ARPA Network Terminal System]] project, the latter at [[Information Sciences Institute|ISI]].<br />
<br />
Little is currently known of their physical implementation, and in particular if they shared a [[logic]] design, or just their programming interface specification. They provided an [[1822 interface]] for the [[UNIBUS]] which used [[Direct Memory Access|DMA]] to transfer data to/from [[main memory]].<br />
<br />
==Differences==<br />
<br />
The ANTS and ISI versions have only minor differences:<br />
<br />
* The [[register]] which specifies the extent of a transfer; the ANTS one gives the ending [[address]], the ISI one gives the transfer size <br />
* The ISI one has two extra bits of transfer memory address; without those, the ANTS one is restricted to using [[buffer]]s in the lowest 64KB of memory<br />
<br />
==Registers==<br />
<br />
{| border=1<br />
! Register !! Abbreviation !! Address<br />
|-<br />
|Input Start Pointer Register || IMPSPI || 0764000<br />
|-<br />
|Input End Pointer/Byte Count Register || IMPEPI/IMPBCI || 0764002<br />
|-<br />
|Input Status Register 1 || IMPS1I || 0764004<br />
|-<br />
|Input Status Register 2 || IMPS2I || 0764006<br />
|-<br />
|Output Start Pointer Register || IMPSPO || 0764010<br />
|-<br />
|Output End Pointer/Byte Count Register || IMPEPO/IMPBCO || 0764012<br />
|-<br />
|Output Status Register 1 || IMPS1O || 0764014<br />
|-<br />
|Output Status Register 2 || IMPS2O || 0764016<br />
|}<br />
<br />
===0764000: Input Start Pointer Register (IMPSPI)===<br />
{{16bit-header}}<br />
| colspan=16 | SP15 <---> SP00<br />
{{16bit-bitout}}<br />
<br />
===0764002: Input End Pointer (IMPEPI) ANTS===<br />
{{16bit-header}}<br />
| colspan=16 | EP15 <---> EP00<br />
{{16bit-bitout}}<br />
<br />
===0764002: Input Byte Count Register (IMPBCI) ISI===<br />
{{16bit-header}}<br />
| colspan=16 | BC15 <---> BC00<br />
{{16bit-bitout}}<br />
<br />
===0764004: Input Status Register 1 (IMPS1I)===<br />
{{16bit-header}}<br />
| IMPERR || NEXMEM || Unused || BCEQ0 || BUSY || colspan=2 | Unused || ENDMSG || BUFULL || INTENA || Unused || NOSWAP || Unused || colspan=2 | MEMEX || Unused <br />
{{16bitoctal-bitout}}<br />
<br />
*IMPERR - IMP error<br />
*NEXMEM - Non-existent memory<br />
*BCEQ0 - Byte count=0<br />
*ENDMSG - End of message<br />
*BUFULL - Buffer full<br />
*INTENA - Interrupt enable<br />
*NOSWAP - Suppress byte swapping<br />
*MEMEX - Memory address extension (ISI only)<br />
<br />
===0764006: Input Status Register 2 (IMPS2I)===<br />
{{16bit-header}}<br />
| colspan=5 | Unused || TSTINC || LOCK || LOOP || IMPRDY || colspan=6 | Unused || SCOSYN<br />
{{16bitoctal-bitout}}<br />
<br />
*TSTINC - Test increment<br />
*LOCK - Lock interface (don't start when EPI/BCI is loaded)<br />
*LOOP - Loop output to input<br />
*IMPRDY - IMP master ready<br />
*SCOSYN - Scope sync<br />
<br />
===0764000: Output Start Pointer Register (IMPSPO)===<br />
{{16bit-header}}<br />
| colspan=16 | SP15 <---> SP00<br />
{{16bit-bitout}}<br />
<br />
===0764002: Output End Pointer (IMPEPO) ANTS===<br />
{{16bit-header}}<br />
| colspan=16 | EP15 <---> EP00<br />
{{16bit-bitout}}<br />
<br />
===0764002: Output Byte Count Register (IMPBCO) ISI===<br />
{{16bit-header}}<br />
| colspan=16 | BC15 <---> BC00<br />
{{16bit-bitout}}<br />
<br />
===0764004: Output Status Register 1 (IMPS1O)===<br />
{{16bit-header}}<br />
| Unused || NEXMEM || Unused || BCEQ0 || BUSY || colspan=3 | Unused || DONE || INTENA || Unused || NOSWAP || Unused || colspan=2 | MEMEX || DISEOM <br />
{{16bitoctal-bitout}}<br />
<br />
*NEXMEM - Non-existent memory<br />
*BCEQ0 - Byte count=0<br />
*INTENA - Interrupt enable<br />
*NOSWAP - Suppress byte swapping<br />
*MEMEX - Memory address extension (ISI only)<br />
*DISEOM - Disable end of message<br />
<br />
===0764006: Output Status Register 2 (IMPS2O)===<br />
{{16bit-header}}<br />
| colspan=7 | Unused || IRESET || colspan=7 | Unused || HOSRDY <br />
{{16bitoctal-bitout}}<br />
<br />
*IRESET - Interface reset<br />
*HOSRDY - Host master ready<br />
<br />
==External links==<br />
<br />
* [https://github.com/larsbrinkhoff/elf-operating-system/blob/master/files/ucbmac.m11%5Btmp%2Ctvr%5D130 ucbmac.m11] - [[ELF operating system|ELF]] [[macro]] definitions, including registers<br />
* [https://github.com/larsbrinkhoff/elf-operating-system/blob/master/files/elfnio.o11%5Btmp%2Ctvr%5D114 elfnio.o11] - ELF [[device driver]]<br />
<br />
[[Category: 1822 Interfaces‎]]<br />
[[Category: UNIBUS Network Interfaces]]</div>
Jnc