Able ENABLE - Revision history

Jnc: +New category

2024-02-06T13:47:58Z

+New category

Jnc: /* Technical details */ better link target

2022-12-05T16:49:59Z

‎Technical details: better link target

Jnc: /* Programming model */ grammar

2022-12-05T16:12:05Z

‎Programming model: grammar

Jnc: /* External links */ +user man, +cat

2022-12-05T16:09:37Z

‎External links: +user man, +cat

Jnc: clarify

2021-01-27T22:36:21Z

clarify

Jnc: clarify

2019-09-10T01:32:20Z

clarify

Jnc: /* External links */ +cat

2018-12-06T20:04:28Z

‎External links: +cat

Jnc: Add image from brochure

2018-07-22T13:08:27Z

Add image from brochure

Jnc: Minor tweaks

2018-05-06T12:49:13Z

Minor tweaks

Jnc: Minor copyedits

2018-01-05T14:12:45Z

Minor copyedits

← Older revision		Revision as of 13:47, 6 February 2024
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	[[Category: PDP-11s]]		[[Category: PDP-11s]]
	[[Category: UNIBUS]]		[[Category: UNIBUS]]
		+	[[Category: Extended UNIBUS]]

@@ Line 83: / Line 83: @@
 The still-extant documentation does not cover the details of how the ENABLE could tell whether a bus cycle was from the CPU, or a DMA device, but it is possible to analyze the framework.
-The ENABLE, being behind all the DMA devices, will of course not see the [[bus grant line|NPG grant]] signal, but it can observe NPR, SACK and BBSY, and from this work out that when BBSY is re-asserted after it sees SACK, all bus read/write cycles during that assertion of BBSY must be from a DMA device. (Technically, a device can also do DMA cycles after gaining control of the bus with a BRn signal, usually used for an [[interrupt]], so perhaps the ENABLE only monitored SACK and BBSY.)
+The ENABLE, being behind all the DMA devices, will of course not see the [[Non-Processor Request and Grant|NPG grant]] signal, but it can observe NPR, SACK and BBSY, and from this work out that when BBSY is re-asserted after it sees SACK, all bus read/write cycles during that assertion of BBSY must be from a DMA device. (Technically, a device can also do DMA cycles after gaining control of the bus with a BRn signal, usually used for an [[interrupt]], so perhaps the ENABLE only monitored SACK and BBSY.)
 ==Optional cache==

@@ Line 19: / Line 19: @@
 Also, the method for deciding which ABLE PAR to use for any given CPU memory cycle was different.
-In the basic PDP-11 [[memory management]], the PAR to use for any given memory cycle is selected based the [[virtual address]], the CPU's current mode (Kerner, User, etc), and, for machines which support [[PDP-11 Memory Management|Split I+D]], whether it is an instruction or data fetch.
+In the basic PDP-11 [[memory management]], the PAR to use for any given memory cycle is selected based on the [[virtual address]], the CPU's current mode (Kernel, User, etc), and, for machines which support [[PDP-11 Memory Management|Split I+D]], whether it is an instruction or data fetch.
 The ENABLE, being a UNIBUS device, had access to none of the information about CPU mode, fetch type, etc. Instead, the ENABLE chose which of its PARs to use for any given memory cycle based solely on the UNIBUS address. For 256KB of [[address space]], it had 32 PARs, each one thus applying to 8KB of address space - the same size as with the PDP-11's native PARs.
@@ Line 25: / Line 25: @@
 One simple programming model for using all this was to set up the native PARs to statically map different CPU address spaces (e.g. Kernel I space) to distinct blocks of the UNIBUS address space, and from then on, leave the native PARs untouched, using only the ABLE PARs, as the [[operating system]] ran.
-For [[Unix]], this was particularly easy to achieve; the file which contained the definition of the PAR addresses was modified, the OS was recompiled, and no other changes (other than properly initializing the ENABLE and the CPU's PARs) were needed.
+For [[UNIX]], this was particularly easy to achieve; the file which contained the definition of the PAR addresses was modified, the OS was recompiled, and no other changes (other than properly initializing the ENABLE and the CPU's PARs) were needed.
 The only disadvantage of this simple approach was that with 3 CPU modes; instruction and data fetches; and a 64KB virtual address, there is no way to statically map all of them to fixed UNIBUS addresses; that would require 3*2*64KB, or 384KB of address space, and the UNIBUS only has 256KB available.

@@ Line 105: / Line 105: @@
 ==External links==
 * [http://gopher.quux.org:70/Archives/usenet-a-news/FA.unix-wizards/81.07.09_ucbvax.2202_fa.unix-wizards.txt Adding additional memory to 11/45s]
 * [http://gopher.quux.org:70/Archives/usenet-a-news/FA.unix-wizards/81.07.12_ucbvax.2254_fa.unix-wizards.txt More ENABLE/34 Info...]
 [[Category: PDP-11s]]

@@ Line 1: / Line 1: @@
-[[Image:BrochureAbleENABLE.jpg|250px|thumb|right|Able ENABLE as shown in an Able brochure]]
+[[Image:BrochureAbleENABLE.jpg|250px|thumb|right|Able ENABLE, as shown in an Able brochure]]
-The '''ENABLE''' from [[Able Computer]] (also variously given in Able documentation as the '''EnABLE''' and '''ENABLE/34''') was a [[UNIBUS]] device which allowed the smaller [[PDP-11]]'s to have up to 4 MBytes of [[main memory]].
+The '''ENABLE''' from [[Able Computer]] (also variously given in Able documentation as the '''EnABLE''' and '''ENABLE/34''') was a [[UNIBUS]] device which allowed the smaller [[PDP-11]]'s ([[PDP-11/34]] through [[PDP-11/45]]) to have up to 4 MBytes of [[main memory]].
-The ENABLE took an incoming UNIBUS segment, containing the [[Central Processing Unit|CPU]] and all [[Direct Memory Access|DMA]] devices, and ran all memory read-write cycles on it through two different sets of relocation [[register]]s - one set for the CPU, and a separate set for the devices (the ENABLE was able to tell, by watching the details of the bus cycles, the source of any given cycle) - and produced cycles to a relocated address on an [[Extended UNIBUS]]. This could hold stock EUB memory cards, up to the 4MB standard on the EUB.
+The ENABLE took an incoming UNIBUS segment, containing the [[Central Processing Unit|CPU]] and all [[Direct Memory Access|DMA]] [[peripheral controller|devices]], and ran all read-write cycles from them to memory through two different sets of relocation [[register]]s - one set for the CPU, and a separate set for the devices (the ENABLE was able to tell, by watching the details of the bus cycles, the source of any given cycle). It then produced cycles to relocated [[address]]es on a separate [[Extended UNIBUS]]; the latter could hold stock EUB memory cards, up to the 4MB standard on the EUB.
 Physically, the ENABLE was a [[DEC card form factor|hex]]-width card which plugged into a standard [[Modified UNIBUS Device]] [[backplane]], which was used in EUB mode. (Since the EUB re-purposed existing bus lines, which were bussed to all the slots in an MUD backplane, this worked.) The stock EUB memory cards plugged into this backplane.
@@ Line 9: / Line 9: @@
 The incoming UNIBUS segment was introduced to the ENABLE via a standard UNIBUS connector on the back edge of the ENABLE card, into which a standard [[BC11A UNIBUS cable]] from the rest of the machine was plugged. The ENABLE's EUB interface was via the card's [[DEC edge connector contact identification|edge connectors]] where the card plugged into the MUD/EUB backplane.
-There was also an optional 8KB [[cache]] card; and an optional 'Memory Adapter' card, from which came another UNIBUS segment, to which could be attached other non-DMA devices, and/or up to 128KB of existing UNIBUS memory. (The reason for the limitation is not clear.) Details on both are given below.
+There was also an optional 8KB [[cache]] card; and also an optional 'Memory Adapter' card, from which came another UNIBUS segment, to which could be attached other non-DMA devices, and/or up to 128KB of existing UNIBUS memory. (The reason for the limitation is not clear.) Details on both are given below.
 ==Programming model==
@@ Line 87: / Line 87: @@
 ==Optional cache==
-The cache came on a [[DEC card form factor|quad]]-width card which plugged into the [[DEC edge connector contact identification|C-F connectors]] of the first slot of the MUD/EUB backplane holding the ENABLE main card. All "necessary" signals between the ENABLE and cache were carried by a [[flat cable]] which plugged into connectors on the tops of both cards; the backplane provided only power.
+The cache came on a [[DEC card form factor|quad]]-width card which plugged into the [[DEC edge connector contact identification|C-F connectors]] of the first slot of the MUD/EUB backplane holding the ENABLE main card. All "necessary" signals between the ENABLE and cache were carried by an [[over the back]] [[flat cable]] which plugged into connectors on the tops of both cards; the backplane provided only power.
 (It is possible that the data lines and/or lower address lines of the EUB, which are accessible on the lower connectors of the EUB/MUD backplane in the [[Small Peripheral Controller|SPC]] portion of the slot, were used, but the still-extant documentation does not cover this level of detail.)

← Older revision		Revision as of 20:04, 6 December 2018
Line 107:		Line 107:
	* [http://gopher.quux.org:70/Archives/usenet-a-news/FA.unix-wizards/81.07.09_ucbvax.2202_fa.unix-wizards.txt Adding additional memory to 11/45s]		* [http://gopher.quux.org:70/Archives/usenet-a-news/FA.unix-wizards/81.07.09_ucbvax.2202_fa.unix-wizards.txt Adding additional memory to 11/45s]
	* [http://gopher.quux.org:70/Archives/usenet-a-news/FA.unix-wizards/81.07.12_ucbvax.2254_fa.unix-wizards.txt More ENABLE/34 Info...]		* [http://gopher.quux.org:70/Archives/usenet-a-news/FA.unix-wizards/81.07.12_ucbvax.2254_fa.unix-wizards.txt More ENABLE/34 Info...]
		+
		+	[[Category: PDP-11s]]

← Older revision		Revision as of 13:08, 22 July 2018
Line 1:		Line 1:
		+	[[Image:BrochureAbleENABLE.jpg\|250px\|thumb\|right\|Able ENABLE as shown in an Able brochure]]
		+
	The '''ENABLE''' from [[Able Computer]] (also variously given in Able documentation as the '''EnABLE''' and '''ENABLE/34''') was a [[UNIBUS]] device which allowed the smaller [[PDP-11]]'s to have up to 4 MBytes of [[main memory]].		The '''ENABLE''' from [[Able Computer]] (also variously given in Able documentation as the '''EnABLE''' and '''ENABLE/34''') was a [[UNIBUS]] device which allowed the smaller [[PDP-11]]'s to have up to 4 MBytes of [[main memory]].

@@ Line 1: / Line 1: @@
 The '''ENABLE''' from [[Able Computer]] (also variously given in Able documentation as the '''EnABLE''' and '''ENABLE/34''') was a [[UNIBUS]] device which allowed the smaller [[PDP-11]]'s to have up to 4 MBytes of [[main memory]].
-The ENABLE took an incoming UNIBUS segment, containing the [[Central Processing Unit|CPU]] and all [[Direct Memory Access|DMA]] devices, and ran all memory read-write cycles on it through two different sets of relocation [[register]]s (one set for the CPU, and a separate set for the devices - the ENABLE was able to tell, by watching the details of the bus cycles, the source of any given cycle) and produced cycles to a relocated address on an [[Extended UNIBUS]]. This could hold stock EUB memory cards, up to the 4MB standard on the EUB.
+The ENABLE took an incoming UNIBUS segment, containing the [[Central Processing Unit|CPU]] and all [[Direct Memory Access|DMA]] devices, and ran all memory read-write cycles on it through two different sets of relocation [[register]]s - one set for the CPU, and a separate set for the devices (the ENABLE was able to tell, by watching the details of the bus cycles, the source of any given cycle) - and produced cycles to a relocated address on an [[Extended UNIBUS]]. This could hold stock EUB memory cards, up to the 4MB standard on the EUB.
 Physically, the ENABLE was a [[DEC card form factor|hex]] card which plugged into a standard [[Modified UNIBUS Device]] [[backplane]], which was used in EUB mode. (Since the EUB re-purposed existing bus lines, which were bussed to all the slots in an MUD backplane, this worked.) The stock EUB memory cards plugged into this backplane.
@@ Line 13: / Line 13: @@
 The register set used for mapping DMA cycles exactly emulated the [[UNIBUS map]], as in the [[PDP-11/70]] and later [[PDP-11/44]], and was used in exactly the same way.
-The register set used for mapping CPU cycles was indentical in function to the PAR's of the standard [[PDP-11 Memory Management]] system, but had different addresses from the ones built into the CPU. (The ENABLE did not have PDRs; the standard PDRs in the CPU were used.)
+The register set used for mapping CPU cycles was indentical in function to the PAR's of the standard [[PDP-11 Memory Management]] system, but had different addresses from the ones built into the CPU. (The ENABLE did not have PDRs; the PDRs in the CPU were used.)
 Also, the method for deciding which ABLE PAR to use for any given CPU memory cycle was different.
-In the basic PDP-11 memory management, the PAR to use for any given memory cycle is selected based the [[virtual address]], the CPU's current mode (Kerner, User, etc), and, for machines which support [[PDP-11 Memory Management|Split I+D]], whether it is an instruction or data fetch.
+In the basic PDP-11 [[memory management]], the PAR to use for any given memory cycle is selected based the [[virtual address]], the CPU's current mode (Kerner, User, etc), and, for machines which support [[PDP-11 Memory Management|Split I+D]], whether it is an instruction or data fetch.
 The ENABLE, being a UNIBUS device, had access to none of the information about CPU mode, fetch type, etc. Instead, the ENABLE chose which of its PARs to use for any given memory cycle based solely on the UNIBUS address. For 256KB of [[address space]], it had 32 PARs, each one thus applying to 8KB of address space - the same size as with the PDP-11's native PARs.

@@ Line 1: / Line 1: @@
 The '''ENABLE''' from [[Able Computer]] (also variously given in Able documentation as the '''EnABLE''' and '''ENABLE/34''') was a [[UNIBUS]] device which allowed the smaller [[PDP-11]]'s to have up to 4 MBytes of [[main memory]].
-The ENABLE took an incoming UNIBUS segment, containing the [[Central Processing Unit|CPU]] and all [[Direct Memory Access|DMA]] devices, and ran all memory read-write cycles on it through two different sets of relocation [[register]]s (one set for the CPU, and a separate set for the devices - the ENABLE was able to tell, by watching the details of the bus cycles, the source of any given cycle) and produced cycles, to a relocated address on an [[Extended UNIBUS|EUB]]. This could hold stock EUB memory cards, up to the 4MB standard on the EUB.
+The ENABLE took an incoming UNIBUS segment, containing the [[Central Processing Unit|CPU]] and all [[Direct Memory Access|DMA]] devices, and ran all memory read-write cycles on it through two different sets of relocation [[register]]s (one set for the CPU, and a separate set for the devices - the ENABLE was able to tell, by watching the details of the bus cycles, the source of any given cycle) and produced cycles to a relocated address on an [[Extended UNIBUS]]. This could hold stock EUB memory cards, up to the 4MB standard on the EUB.
-Physically, the ENABLE was a [[DEC card form factor|hex]] card which plugged into a standard [[Modified UNIBUS Device|MUD]] [[backplane]], which was used in EUB mode. (Since the EUB re-purposed existing bus lines, which were bussed to all the slots in an MUD backplane, this worked.) The stock EUB memory cards plugged into this backplane.
+Physically, the ENABLE was a [[DEC card form factor|hex]] card which plugged into a standard [[Modified UNIBUS Device]] [[backplane]], which was used in EUB mode. (Since the EUB re-purposed existing bus lines, which were bussed to all the slots in an MUD backplane, this worked.) The stock EUB memory cards plugged into this backplane.
-The incoming UNIBUS segment was introduced to the ENABLE via a standard UNIBUS connector on the back edge of the ENABLE card, into which a standard [[BC11A UNIBUS cable]] from the rest of the machine was plugged. The ENABLE's EUB interface was via the card's [[DEC edge connector contact identification|edge connectors]] where the card plugs into the backplane.
+The incoming UNIBUS segment was introduced to the ENABLE via a standard UNIBUS connector on the back edge of the ENABLE card, into which a standard [[BC11A UNIBUS cable]] from the rest of the machine was plugged. The ENABLE's EUB interface was via the card's [[DEC edge connector contact identification|edge connectors]] where the card plugged into the MUD/EUB backplane.
 There was also an optional 8KB [[cache]] card; and an optional 'Memory Adapter' card, from which came another UNIBUS segment, to which could be attached other non-DMA devices, and/or up to 128KB of existing UNIBUS memory. (The reason for the limitation is not clear.)
@@ Line 81: / Line 81: @@
 The still-extant documentation does not cover the details of how the ENABLE could tell whether a bus cycle was from the CPU, or a DMA device, but it is possible to analyze the framework.
-The ENABLE, being behind all the DMA devices, will of course not see the [[bus grant line|NPG grant]] signal, but it can observe NPR, SACK and BBSY, and from this work out that when BBSY is re-asserted after it sees SACK, all bus read/write cycles during that assertion of BBSY must be from a DMA device. (Technically, a device can also do DMA cycles after gaining control of the bus with a BRn signal, usually used for an [[interrupt]], so perhaps the ENABLE only monitors SACK and BBSY.)
+The ENABLE, being behind all the DMA devices, will of course not see the [[bus grant line|NPG grant]] signal, but it can observe NPR, SACK and BBSY, and from this work out that when BBSY is re-asserted after it sees SACK, all bus read/write cycles during that assertion of BBSY must be from a DMA device. (Technically, a device can also do DMA cycles after gaining control of the bus with a BRn signal, usually used for an [[interrupt]], so perhaps the ENABLE only monitored SACK and BBSY.)
 ==Optional cache==
@@ Line 95: / Line 95: @@
 A 4-wide [[Dual Inline Package|DIP]] switch on the MemDap card indicated where the address space of the secondary UNIBUS appeared, in the full EUB address space. (This was apparently so that the UNIBUS memory, if it started at 0 on the secondary UNIBUS, would appear contiguously with the EUB memory.)
-The working of it was apparently fairly simple; when an address in the range designated by the configuration switch appeared on the EUB, the MemDap card passed that cycle to the secondary UNIBUS, with the high address bits stripped out, but otherwise un-modified.
+The functioning of it was apparently fairly simple; when an address in the range designated by the configuration switch appeared on the EUB, the MemDap card passed that cycle through to the secondary UNIBUS, with the high address bits stripped out, but otherwise un-modified.
 ==Additional EUB backplanes==