Jnc: Multi-processor support, associative register re-use algorithm, core status table

2024-01-06T13:38:08Z

Multi-processor support, associative register re-use algorithm, core status table

← Older revision		Revision as of 13:38, 6 January 2024
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	The '''BBN Pager''' was an add-on device for the [[KA10]] [[CPU\|Central Processing Unit]] to provide [[virtual memory]] capability, designed and built by [[Bolt, Beranek, and Newman\|BBN]] (much as the [[MIT Artificial Intelligence Laboratory\|MIT AI Lab]] added hardware to their KA10 for the same purpose). [[Digital Equipment Corporation\|DEC]] had provided only basic [[memory management]] capabilities on the KA10 - a pair of [[base and bounds]] [[register]]s, one for each half of the [[address space]].		The '''BBN Pager''' was an add-on device for the [[KA10]] [[CPU\|Central Processing Unit]] to provide [[virtual memory]] capability, designed and built by [[Bolt, Beranek, and Newman\|BBN]] (much as the [[MIT Artificial Intelligence Laboratory\|MIT AI Lab]] added hardware to their KA10 for the same purpose). [[Digital Equipment Corporation\|DEC]] had provided only basic [[memory management]] capabilities on the KA10 - a pair of [[base and bounds]] [[register]]s, one for each half of the [[address space]].

	It ~~supported splitting~~ the ~~address space into 512 pages, each 512~~ [[~~word~~]]~~s long; 'user' and 'executive' modes on~~ the KA10 had ~~separate page tables~~.		It was used to support the [[TENEX]] [[operating system]] - although one was also added to the KA10 at [[Stanford Artificial Intelligence Laboratory\|SAIL]], which ran [[WAITS]]. Quite a few were built for other organizations which had KA10's, to allow them to run TENEX.

	~~It was used to support~~ the [[~~TENEX~~]] [[~~operating system~~]] ~~- although one was also added to~~ the KA10 at [[~~Stanford Artificial Intelligence Laboratory\|SAIL~~]], which ~~ran~~ [[~~WAITS~~]]~~. Quite a few~~ were ~~built for other organizations which had~~ KA10~~'s, to allow them to run TENEX~~.		The BBN Pager supported splitting the address space into 512 pages, each 512 [[word]]s long; '[[user]]' and 'executive' modes on the KA10 had separate page tables. It also provided for [[multi-processor]] systems (which were possible on PDP-10's with the 'external' [[PDP-10 Memory Bus]]); although multi-processor [[KI10]]-based TENEX systems were eventually done, it is not known whether any multi-processor KA10 systems with the BBN Pager were ever produced.

	==Technical Details==		==Technical Details==
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	The Pager was a separate unit inserted into the [[PDP-10 Memory Bus]] between the CPU and the system's [[:Category:PDP-10 Memories\|memories]]. It also required minor changes to the KA10; both to provide [[signal]]s required for the operation of the Pager (which were carried to the Pager by two separate cables), and also to make changes to the CPU required by the operating system (such as extra, specialized, [[instruction]]s).		The Pager was a separate unit inserted into the [[PDP-10 Memory Bus]] between the CPU and the system's [[:Category:PDP-10 Memories\|memories]]. It also required minor changes to the KA10; both to provide [[signal]]s required for the operation of the Pager (which were carried to the Pager by two separate cables), and also to make changes to the CPU required by the operating system (such as extra, specialized, [[instruction]]s).

	The pager contained a [[cache]] of [[page table]] translation entries held in 'associative registers'; ~~the~~ basic complement was 16 associative registers, but it would operate with as few as 1, or it could be expanded to up to 54 associative registers.		The pager contained a [[cache]] of [[page table]] translation entries held in 'associative registers'; they were used in a simple 'round robin' scheme, no complex [[Least Recently Used replacement algorithm\|LRU]] system was used. The basic complement was 16 associative registers, but it would operate with as few as 1, or it could be expanded to up to 54 associative registers.

			In addition to a complex multi-level mapping scheme (intended to allow easy sharing of pages between multiple [[process]]es), which included a 'copy on write' mechanism, it also had a "core status table", which recorded "a time-stamp of the last reference, and .. an identification of the processes that had referenced the page".

	==External links==		==External links==
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	** [http://www.bitsavers.org/pdf/bbn/pager/BBN_Pager_196812.pdf Arithmetic Processor Paging]		** [http://www.bitsavers.org/pdf/bbn/pager/BBN_Pager_196812.pdf Arithmetic Processor Paging]
	** [http://www.bitsavers.org/pdf/bbn/pager/Technical_Details_of_the_BBN_Pager_Model_701_197007.pdf Technical Details of the BBN Pager Model 701]		** [http://www.bitsavers.org/pdf/bbn/pager/Technical_Details_of_the_BBN_Pager_Model_701_197007.pdf Technical Details of the BBN Pager Model 701]
			* [https://opost.com/tenex/hbook.html Origins and Development of TOPS-20] - contains useful overview of the core status table

	[[Category: PDP-10s]]		[[Category: PDP-10s]]

Jnc: A good start

2024-01-06T04:16:59Z

A good start

New page

[[Image:TenexPager.jpg|150px|thumb|right|BBN Pager]]

The '''BBN Pager''' was an add-on device for the [[KA10]] [[CPU|Central Processing Unit]] to provide [[virtual memory]] capability, designed and built by [[Bolt, Beranek, and Newman|BBN]] (much as the [[MIT Artificial Intelligence Laboratory|MIT AI Lab]] added hardware to their KA10 for the same purpose). [[Digital Equipment Corporation|DEC]] had provided only basic [[memory management]] capabilities on the KA10 - a pair of [[base and bounds]] [[register]]s, one for each half of the [[address space]].

It supported splitting the address space into 512 pages, each 512 [[word]]s long; 'user' and 'executive' modes on the KA10 had separate page tables.

It was used to support the [[TENEX]] [[operating system]] - although one was also added to the KA10 at [[Stanford Artificial Intelligence Laboratory|SAIL]], which ran [[WAITS]]. Quite a few were built for other organizations which had KA10's, to allow them to run TENEX.

==Technical Details==

The Pager was a separate unit inserted into the [[PDP-10 Memory Bus]] between the CPU and the system's [[:Category:PDP-10 Memories|memories]]. It also required minor changes to the KA10; both to provide [[signal]]s required for the operation of the Pager (which were carried to the Pager by two separate cables), and also to make changes to the CPU required by the operating system (such as extra, specialized, [[instruction]]s).

The pager contained a [[cache]] of [[page table]] translation entries held in 'associative registers'; the basic complement was 16 associative registers, but it would operate with as few as 1, or it could be expanded to up to 54 associative registers.

==External links==

* [http://www.bitsavers.org/pdf/bbn/pager/ BBN pager] - documentation at [[Bitsavers]]
** [http://www.bitsavers.org/pdf/bbn/pager/BBN_Pager_196812.pdf Arithmetic Processor Paging]
** [http://www.bitsavers.org/pdf/bbn/pager/Technical_Details_of_the_BBN_Pager_Model_701_197007.pdf Technical Details of the BBN Pager Model 701]

[[Category: PDP-10s]]

BBN Pager - Revision history

Jnc: Multi-processor support, associative register re-use algorithm, core status table

Jnc: A good start