BCC 500 - Revision history

Larsbrinkhoff: Link to macrocode.

2025-07-13T05:06:19Z

Link to macrocode.

Larsbrinkhoff: Typo.

2025-01-14T15:27:44Z

Typo.

Jnc: Initial design done at Project GENIE; and links to files at Github; adjust tense

2025-01-14T13:09:32Z

Initial design done at Project GENIE; and links to files at Github; adjust tense

Larsbrinkhoff: /* External links */ As gleaned from documentation.

2024-04-29T15:44:54Z

‎External links: As gleaned from documentation.

Larsbrinkhoff: Also 940 instruction set.

2024-03-11T11:59:09Z

Also 940 instruction set.

Larsbrinkhoff: Sold 1971, back online 1973.

2024-03-11T11:58:01Z

Sold 1971, back online 1973.

Jnc: Add some links, interesting Bitsavers material

2024-03-08T12:41:03Z

Add some links, interesting Bitsavers material

Larsbrinkhoff: Front ends.

2024-03-08T09:05:03Z

Front ends.

Larsbrinkhoff: /* External links */ 1979 tape from U Hawaii.

2024-03-08T08:46:09Z

‎External links: 1979 tape from U Hawaii.

Larsbrinkhoff: Last page of log book posted to Bitsavers; it's from February 1980.

2024-03-07T17:01:18Z

Last page of log book posted to Bitsavers; it's from February 1980.

@@ Line 3: / Line 3: @@
 The '''BCC 500''' was a computer made by the [[Berkeley Computer Corporation]], from an initial design at [[Project GENIE]].  When the company went bankrupt in 1971, the prototype was sold to University of Hawaii.  After two years of refurbishment it was successfully deployed as an [[ARPANET]] host until 1980.  It was also the hub of the [[ALOHA network]] which inspired [[Ethernet]].
-The computer consisted of six independent [[microcode]]d processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory.  The microcode implemented an [[instruction set]] with a 6-bit [[operation code|opcode]] and 18-bit [[address]] field, as well as a subset of the [[SDS 940|940]] instruction set.  Two of the processors had expanded hardware capabilities and ran user code.  The other four were each responsible for implementing their own part of the [[operating system]]; part in microcode and part in macrocode.
+The computer consisted of six independent [[microcode]]d processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory.  The microcode implemented an [[instruction set]] with a 6-bit [[operation code|opcode]] and 18-bit [[address]] field, as well as a subset of the [[SDS 940|940]] instruction set.  Two of the processors had expanded hardware capabilities and ran user code.  The other four were each responsible for implementing their own part of the [[operating system]]; part in microcode and part in [[macrocode]].
 At BCC, an [[IBM System/360|IBM 360/30]] acted as a [[front end]], handling tape drives, card readers, and printers.  This was replaced by an [[HP2100]]A at Hawaii.  A [[PDP-11/10]] running [[ELF operating system|ELF]] connected to the ARPANET.

@@ Line 3: / Line 3: @@
 The '''BCC 500''' was a computer made by the [[Berkeley Computer Corporation]], from an initial design at [[Project GENIE]].  When the company went bankrupt in 1971, the prototype was sold to University of Hawaii.  After two years of refurbishment it was successfully deployed as an [[ARPANET]] host until 1980.  It was also the hub of the [[ALOHA network]] which inspired [[Ethernet]].
-The computer consistd of six independent [[microcode]]d processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory.  The microcode implemented an [[instruction set]] with a 6-bit [[operation code|opcode]] and 18-bit [[address]] field, as well as a subset of the [[SDS 940|940]] instruction set.  Two of the processors had expanded hardware capabilities and ran user code.  The other four were each responsible for implementing their own part of the [[operating system]]; part in microcode and part in macrocode.
+The computer consisted of six independent [[microcode]]d processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory.  The microcode implemented an [[instruction set]] with a 6-bit [[operation code|opcode]] and 18-bit [[address]] field, as well as a subset of the [[SDS 940|940]] instruction set.  Two of the processors had expanded hardware capabilities and ran user code.  The other four were each responsible for implementing their own part of the [[operating system]]; part in microcode and part in macrocode.
 At BCC, an [[IBM System/360|IBM 360/30]] acted as a [[front end]], handling tape drives, card readers, and printers.  This was replaced by an [[HP2100]]A at Hawaii.  A [[PDP-11/10]] running [[ELF operating system|ELF]] connected to the ARPANET.

@@ Line 1: / Line 1: @@
 [[Image:BCC-500_1.jpg|300px|right|thumb|BCC 500]]
-The '''BCC 500''' was a computer made by the [[Berkeley Computer Corporation]].  When the company went bankrupt in 1971, the prototype was sold to University of Hawaii.  After two years of refurbishment it was successfully deployed as an [[ARPANET]] host until 1980.  It was also the hub of the [[ALOHA network]] which inspired [[Ethernet]].
+The '''BCC 500''' was a computer made by the [[Berkeley Computer Corporation]], from an initial design at [[Project GENIE]].  When the company went bankrupt in 1971, the prototype was sold to University of Hawaii.  After two years of refurbishment it was successfully deployed as an [[ARPANET]] host until 1980.  It was also the hub of the [[ALOHA network]] which inspired [[Ethernet]].
-The computer consists of six independent [[microcode]]d processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory.  The microcode implements an [[instruction set]] with a 6-bit [[operation code|opcode]] and 18-bit [[address]] field, as well as a subset of the [[SDS 940|940]] instruction set.  Two of the processors have expanded hardware capabilities and run user code.  The other four are each responsible for implementing their own part of the [[operating system]]; part in microcode and part in macrocode.
+The computer consistd of six independent [[microcode]]d processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory.  The microcode implemented an [[instruction set]] with a 6-bit [[operation code|opcode]] and 18-bit [[address]] field, as well as a subset of the [[SDS 940|940]] instruction set.  Two of the processors had expanded hardware capabilities and ran user code.  The other four were each responsible for implementing their own part of the [[operating system]]; part in microcode and part in macrocode.
-At BCC, an [[IBM System/360|IBM 360/30]] acted as a [[front end]], handling tape drives, card readers, and printers.  This was replaced by a [[Hewlett-Packard|HP]]2100A at Hawaii.  A [[PDP-11/10]] running [[ELF operating system|ELF]] connected to the [[ARPANET]].
+At BCC, an [[IBM System/360|IBM 360/30]] acted as a [[front end]], handling tape drives, card readers, and printers.  This was replaced by an [[HP2100]]A at Hawaii.  A [[PDP-11/10]] running [[ELF operating system|ELF]] connected to the ARPANET.
 {{semi-stub}}
 == External links ==
@@ Line 15: / Line 19: @@
 ** [http://www.bitsavers.org/pdf/univOfHawaii/R-1_BCC500_DesignFeatures_Rev_Mar74.pdf Design Features of the BCC 500 CPU]
 ** [http://www.bitsavers.org/pdf/univOfHawaii/Aloha_BCC-500/pictures/hawaii_bcc500_block_diagram.jpg BCC500 block diagram]
 ** [http://www.bitsavers.org/pdf/univOfHawaii/Aloha_BCC-500/logbooks/Last_BCC500_HW_Log_Entry_19800229.pdf Last BCC500 Log Entry]
-** [http://www.bitsavers.org/bits/UniversityOfHawaii/BCC-500/ Tape image "BCC 500 Proof Tape]
+** [http://www.bitsavers.org/bits/UniversityOfHawaii/BCC-500/ Tape image "BCC 500 Proof Tape"]
 * [http://bwlampson.site/06a-BCC500Notes/06a-BCC500Notes.pdf Some Remarks on a Large New Time-Sharing System]
 * [http://bwlampson.site/06-DynamicProtect/06-DynamicProtect.pdf Dynamic protection structures]

@@ Line 15: / Line 15: @@
 ** [http://www.bitsavers.org/pdf/univOfHawaii/R-1_BCC500_DesignFeatures_Rev_Mar74.pdf Design Features of the BCC 500 CPU]
 ** [http://www.bitsavers.org/pdf/univOfHawaii/Aloha_BCC-500/pictures/hawaii_bcc500_block_diagram.jpg BCC500 block diagram]
 ** [http://www.bitsavers.org/pdf/univOfHawaii/Aloha_BCC-500/logbooks/Last_BCC500_HW_Log_Entry_19800229.pdf Last BCC500 Log Entry]
 ** [http://www.bitsavers.org/bits/UniversityOfHawaii/BCC-500/ Tape image "BCC 500 Proof Tape]

@@ Line 3: / Line 3: @@
 The '''BCC 500''' was a computer made by the [[Berkeley Computer Corporation]].  When the company went bankrupt in 1971, the prototype was sold to University of Hawaii.  After two years of refurbishment it was successfully deployed as an [[ARPANET]] host until 1980.  It was also the hub of the [[ALOHA network]] which inspired [[Ethernet]].
-The computer consists of six independent [[microcode]]d processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory.  The microcode implements an [[instruction set]] with a 6-bit [[operation code|opcode]] and 18-bit [[address]] field.  Two of the processors have expanded hardware capabilities and run user code.  The other four are each responsible for implementing their own part of the [[operating system]]; part in microcode and part in macrocode.
+The computer consists of six independent [[microcode]]d processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory.  The microcode implements an [[instruction set]] with a 6-bit [[operation code|opcode]] and 18-bit [[address]] field, as well as a subset of the [[SDS 940|940]] instruction set.  Two of the processors have expanded hardware capabilities and run user code.  The other four are each responsible for implementing their own part of the [[operating system]]; part in microcode and part in macrocode.
 At BCC, an [[IBM System/360|IBM 360/30]] acted as a [[front end]], handling tape drives, card readers, and printers.  This was replaced by a [[Hewlett-Packard|HP]]2100A at Hawaii.  A [[PDP-11/10]] running [[ELF operating system|ELF]] connected to the [[ARPANET]].

← Older revision		Revision as of 09:05, 8 March 2024
Line 4:		Line 4:

	The computer consists of six independent microcoded processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory. The microcode implements a machine code with a 6-bit opcode and 18-bit address field. Two of the processors have expanded hardware capabilities and run user code. The other four are each responsible for implementing their own part of the operating system; part in microcode and part in macrocode.		The computer consists of six independent microcoded processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory. The microcode implements a machine code with a 6-bit opcode and 18-bit address field. Two of the processors have expanded hardware capabilities and run user code. The other four are each responsible for implementing their own part of the operating system; part in microcode and part in macrocode.
		+
		+	At BCC, an [[IBM_System/360\|IBM 360/30]] acted as a front end, handling tape drives, card readers, and printers. This was replaced by a [[Hewlett-Packard\|HP]]2100A at Hawaii. A [[PDP-11/10]] running [[ELF]] connected to [[ARPANET]].

	{{semi-stub}}		{{semi-stub}}

@@ Line 1: / Line 1: @@
 [[Image:BCC-500_1.jpg|300px|right|thumb|BCC 500]]
-The '''BCC 500''' was a computer made by the [[Berkeley Computer Corporation]].  When the company went bankrupt, the prototype went to Hawaii and was successfully deployed as an [[ARPANET]] host.  It was also the hub of the [[ALOHA network]] which inspired [[Ethernet]].
+The '''BCC 500''' was a computer made by the [[Berkeley Computer Corporation]].  When the company went bankrupt, the prototype went to Hawaii and was successfully deployed as an [[ARPANET]] host until 1980.  It was also the hub of the [[ALOHA network]] which inspired [[Ethernet]].
 The computer consists of six independent microcoded processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory.  The microcode implements a machine code with a 6-bit opcode and 18-bit address field.  Two of the processors have expanded hardware capabilities and run user code.  The other four are each responsible for implementing their own part of the operating system; part in microcode and part in macrocode.