Chaosnet interface - Revision history

Jnc: /* 764140: Control Status Register (CSR) */ Typo

2024-11-24T18:59:25Z

764140: Control Status Register (CSR): Typo

← Older revision		Revision as of 18:59, 24 November 2024
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	\| LSTCN \|\| Count of messages lost		\| LSTCN \|\| Count of messages lost
	\|-		\|-
	\| TCL \|\| ~~Receiver~~ clear		\| TCL \|\| Transmitter clear
	\|-		\|-
	\| TDN \|\| Transmitter done		\| TDN \|\| Transmitter done

Jnc: Move to new sub-cat

2024-08-01T21:32:46Z

Move to new sub-cat

← Older revision		Revision as of 21:32, 1 August 2024
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	[[Category: UNIBUS Network Interfaces]]		[[Category: UNIBUS Network Interfaces]]
	[[Category: QBUS Network Interfaces]]		[[Category: QBUS Network Interfaces]]
	[[Category: ~~Chaos~~]]		[[Category: Chaosnet Hardware]]

Larsbrinkhoff: Category: Chaos

2024-07-30T05:56:44Z

Category: Chaos

← Older revision		Revision as of 05:56, 30 July 2024
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	[[Category: UNIBUS Network Interfaces]]		[[Category: UNIBUS Network Interfaces]]
	[[Category: QBUS Network Interfaces]]		[[Category: QBUS Network Interfaces]]
			[[Category: Chaos]]

Jnc: Add Load Interval Timer Register

2023-09-17T16:28:18Z

Add Load Interval Timer Register

← Older revision		Revision as of 16:28, 17 September 2023
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	\| RCL \|\| Receiver clear		\| RCL \|\| Receiver clear
	\|-		\|-
	\| SPY \|\| ~~Spy - accept any~~ messages		\| SPY \|\| Accept all messages
	\|-		\|-
	\| LPBK \|\| Loop back in interface		\| LPBK \|\| Loop back in interface
Line 87:		Line 87:
	===764142: Write Buffer Register (WBF)===		===764142: Write Buffer Register (WBF)===
	{{16bit-header}}		{{16bit-header}}
	\| colspan=16 \| '''OutData15 <--- OutData00'''		\| colspan=16 \| '''OutData15 <---> OutData00'''
	{{16bitoctal-bitout}}		{{16bitoctal-bitout}}

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	{{16bit-header}}		{{16bit-header}}
	\| colspan=16 \| ''InData15 <--- InData0''		\| colspan=16 \| ''InData15 <---> InData0''
	{{16bitoctal-bitout}}		{{16bitoctal-bitout}}

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	{{16bit-header}}		{{16bit-header}}
	\| colspan=4 \| Unused \|\| colspan=12 \| ''BitCount11 <--- BitCount0''		\| colspan=4 \| Unused \|\| colspan=12 \| ''BitCount11 <---> BitCount0''
	{{16bitoctal-bitout}}		{{16bitoctal-bitout}}

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	On the Chaosnet UNIBUS interface, a read-only register; ''reading'' it initiates transmission of a packet. (The data returned is the interface's network address.)		On the Chaosnet UNIBUS interface, a read-only register; ''reading'' it initiates transmission of a packet. (The data returned is the interface's network address.)

			===764160: Load Interval Timer Register (TIM)===
			{{16bit-header}}
			\| colspan=16 \| '''Timer15 <---> Timer00'''
			{{16bitoctal-bitout}}

			Write-only register.

	==External links ==		==External links ==

Jnc: Interrupt vector; add operation to start transmission

2023-09-16T03:06:47Z

Interrupt vector; add operation to start transmission

← Older revision		Revision as of 03:06, 16 September 2023
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	I am not certain of this; I think cards with pins on the back did this, which is why they made card with pins on the package side. -->		I am not certain of this; I think cards with pins on the back did this, which is why they made card with pins on the package side. -->

	Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches; <!-- to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. --> the ~~default is~~ 0764140~~<!--~~ and ~~0340 -->~~. The [[network address]] is also set via a DIP switch.		Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches; <!-- to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. --> the defaults are 0764140 and 0270. The [[network address]] is also set via a DIP switch.

	==Device registers==		==Device registers==
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	{{16bitoctal-bitout}}		{{16bitoctal-bitout}}

	~~Read~~-only register.		On the Chaosnet UNIBUS interface, a read-only register.

			On the QBCHNI, ''writing'' the interface's network address into this register initiates transmission of a packet.

			===764152: Initiate Transmission Register (XMT)===
			{{16bit-header}}
			\| colspan=8 \| ''Subnet7 <---> Subnet0'' \|\| colspan=8 \| ''Host7 <---> Host0''
			{{16bitoctal-bitout}}

			On the Chaosnet UNIBUS interface, a read-only register; ''reading'' it initiates transmission of a packet. (The data returned is the interface's network address.)

	==External links ==		==External links ==

Jnc: Add registers

2023-09-15T23:58:27Z

Add registers

← Older revision		Revision as of 23:58, 15 September 2023
Line 8:		Line 8:
	I am not certain of this; I think cards with pins on the back did this, which is why they made card with pins on the package side. -->		I am not certain of this; I think cards with pins on the back did this, which is why they made card with pins on the package side. -->

	Their [[bus]] [[address]] ~~<!--~~ and [[interrupt vector]]s ~~-->~~ can be set via [[Dual Inline Package\|DIP]] switches; <!-- to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. --> the default is 0764140<!-- and 0340 ~~- looks like there are enough DIPs for the vector too, but no docs~~ -->. The [[network address]] is also set via a DIP switch.		Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches; <!-- to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. --> the default is 0764140<!-- and 0340 -->. The [[network address]] is also set via a DIP switch.

	==Device registers==		==Device registers==
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	In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics'', and those which are write-only are shown in '''bold'''.		In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics'', and those which are write-only are shown in '''bold'''.
	~~<!--~~ ===~~764000~~: Control Status Register (CSR)===
			===764140: Control Status Register (CSR)===
	{{16bit-header}}		{{16bit-header}}
	\| ~~colspan=2~~ \| '''XM''' \|\| colspan=6 \| '''~~FUNC~~''' \|\| ''~~CDN~~'' \|\| ~~CIE~~ \|\| ''~~RDN~~'' \|\| ~~RIE~~ \|\| ~~colspan=4~~ \| ''~~STAT~~''		\| RDN \|\| ''ERR'' \|\| '''RST''' \|\| colspan=4 \| ''LSTCN'' \|\| '''TCL''' \|\| TDN \|\| ''TAB'' \|\| TEN \|\| REN \|\| '''RCL''' \|\| SPY \|\| LPBK \|\| TIE
	{{16bitoctal-bitout}}		{{16bitoctal-bitout}}

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	! Bits !! Use		! Bits !! Use
	\|-		\|-
	\| XM \|\| ~~Extended address bits A17 and A16~~		\| RDN \|\| Receive done
	\|-		\|-
	\| ~~FUNC~~ \|\| ~~Command Function Code~~		\| ERR \|\| [[Cyclic redundancy check\|CRC]] error
	\|-		\|-
	\| ~~CDN~~ \|\| ~~Command Done~~		\| RST \|\| I/O reset for interface
	\|-		\|-
	\| ~~CIE~~ \|\| ~~Command Done Interrupt Enable~~		\| LSTCN \|\| Count of messages lost
	\|-		\|-
	\| ~~RDN~~ \|\| ~~Receive DMA Done~~		\| TCL \|\| Receiver clear
	\|-		\|-
	\| ~~RIE~~ \|\| ~~Receive DMA Done Interrupt Enable~~		\| TDN \|\| Transmitter done
	\|-		\|-
	\| ~~STAT~~ \|\| ~~Command Status Code~~		\| TAB \|\| Transmit aborted by conflict
			\|-
			\| TEN \|\| Transmit interrupt enable
			\|-
			\| REN \|\| Receive interrupt enable
			\|-
			\| RCL \|\| Receiver clear
			\|-
			\| SPY \|\| Spy - accept any messages
			\|-
			\| LPBK \|\| Loop back in interface
			\|-
			\| TIE \|\| Timer interrupt enable<br>(was Transmitter busy)
	\|}		\|}

	~~#define CH_TBSY 01 /* Transmitter busy */~~		===764142: My Address Register (MYN)===
			{{16bit-header}}
			\| colspan=8 \| ''Subnet7 <---> Subnet0'' \|\| colspan=8 \| ''Host7 <---> Host0''
			{{16bitoctal-bitout}}

	~~#define CH_LPBK 02 /* Loop back in interface */~~		Read-only register.
	~~#define CH_SPY 04 /* Spy~~ - ~~accept any messages */~~

	~~#define CH_REN 010 /* Receive enable */~~		===764142: Write Buffer Register (WBF)===
			{{16bit-header}}
			\| colspan=16 \| '''OutData15 <--- OutData00'''
			{{16bitoctal-bitout}}

	~~#define CH_RIEN 020 /* Receive interrupt enable */~~		Write-only register.
	~~#define CH_TIEN 040 /* Transmit interrupt enable */~~

	~~#define CH_ABRT 0100 /* Transmit aborted by conflict */~~		===764144: Read Buffer Register (RBF)===

	~~#define CH_TDN 0200 /* Transmission done */~~

	~~#define CH_TCLR 0400 /* Transmitter clear */~~

	~~#define CH_LC1 01000 /* Count of messages lost */~~
	~~#define CH_LC2 02000~~
	~~#define CH_LC3 04000~~
	~~#define CH_LC4 010000~~
	~~#define CH_LC (CH_LC1 \| CH_LC2 \| CH_LC3 \| CH_LC4)~~

	~~#define CH_RST 020000 /* I/O reset for interface */~~
	~~#define CH_CRC 040000 /* CRC error */~~
	~~#define CH_RDN 0100000 /* Input done */~~

	~~===764002: Bus Address Register (BAR)===~~
	{{16bit-header}}		{{16bit-header}}
	\| colspan=16 \| ''~~'BA15~~ <--- ~~BA00'~~''		\| colspan=16 \| ''InData15 <--- InData0''
	{{16bitoctal-bitout}}		{{16bitoctal-bitout}}

	~~Write~~-only register.		Read-only register.

	===~~764004~~: ~~Byte Count~~ Register (~~BCR~~)===		===764146: Read Bit Counter Register (RBC)===

	{{16bit-header}}		{{16bit-header}}
	\| colspan=16 \| ''~~'BC15~~ <--- ~~BC0'~~''		\| colspan=4 \| Unused \|\| colspan=12 \| ''BitCount11 <--- BitCount0''
	{{16bitoctal-bitout}}		{{16bitoctal-bitout}}

	~~Write~~-only register. ~~-->~~		Read-only register.

	==External links ==		==External links ==

Larsbrinkhoff: /* External links */ Converted SUDS drawings.

2023-09-15T18:42:46Z

External links: Converted SUDS drawings.

← Older revision		Revision as of 18:42, 15 September 2023
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	** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/quad.eco QUAD ECO] - "ECO to .. Change cable speed to 4 MHz"		** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/quad.eco QUAD ECO] - "ECO to .. Change cable speed to 4 MHz"
	** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/qadchs.note QADCHS NOTE] - random jottings		** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/qadchs.note QADCHS NOTE] - random jottings
			* [https://github.com/larsbrinkhoff/chaos-schematics/tree/master/converted SUDS drawings converted to PNG pictures]

	[[Category: UNIBUS Network Interfaces]]		[[Category: UNIBUS Network Interfaces]]
	[[Category: QBUS Network Interfaces]]		[[Category: QBUS Network Interfaces]]

Jnc: A start; will add register defs later

2023-09-15T17:26:22Z

A start; will add register defs later

@@ Line 1: / Line 1: @@
-The '''QBCHNI''' is a [[QBUS]] card with a [[CHAOSnet]] interface.
+[[Image:CH11-board.png|thumb|right|250px|CH11 Unibus board]]
-== External Links ==
+The '''Chaosnet UNIBUS interface''' (also called the '''CHAOS-11''', '''CH11''', '''QUAD''' and '''QAD'''; there was no generally-used name) and '''QBCHNI''' are [[Chaosnet]] [[network interface]]s, for the [[UNIBUS]] and [[QBUS]] respectively. (The two [[device controller]]s are identical in [[program]]ming terms, so they are both covered in this single article.)
-* [https://github.com/hanshuebner/cadr2/blob/master/mit/chaos/quad.setup "how to setup ... QBCHNI Chaosnet Interfaces (the LSI-11 Q-Bus version)"]
+They use [[programmed I/O]] to transfer data to and from [[buffer]]s in [[main memory]]. They have on-board buffers (one each for inbound and outbound) which can hold one [[packet]] of data.
-{{stub}}
+They are both a single [[DEC card form factor|quad]] [[wire-wrap]]ped card. <!-- They therefore take up two slots; a [[grant continuity card]] is required, to plug into the second slot, to carry the QBUS' [[bus grant line]]s through the second slot, if there are any devices down-bus from them.
 [[Category: QBUS Network Interfaces]]

Jnc: Jnc moved page QBCHNI to Chaosnet interface: QBUS and UNIBUS interfaces are very similar, will cover on the same page

2023-09-15T15:07:04Z

Jnc moved page QBCHNI to Chaosnet interface: QBUS and UNIBUS interfaces are very similar, will cover on the same page

← Older revision	Revision as of 15:07, 15 September 2023
(No difference)

Jnc: rm dup cat

2021-08-27T09:23:17Z

rm dup cat

← Older revision		Revision as of 09:23, 27 August 2021
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	[[Category: QBUS Network Interfaces]]		[[Category: QBUS Network Interfaces]]
	~~[[Category: QBUS Peripherals]]~~