Condition codes - Revision history

Jnc: /* External links */ +A Case Study of How Not to Design Condition Codes

2024-07-23T14:21:07Z

‎External links: +A Case Study of How Not to Design Condition Codes

Jnc: +cat

2018-12-15T14:24:44Z

+cat

Jnc: Move list of branches to conditonal branch article

2017-11-06T01:35:36Z

Move list of branches to conditonal branch article

Jnc: Typo

2017-10-21T10:52:18Z

Typo

Jnc: typo

2017-10-21T01:36:19Z

typo

Jnc: A pretty good start

2017-10-21T01:14:56Z

A pretty good start

New page

'''Condition codes''' are a way of recording high-level information about the results of arithmetic operations in a [[Central Processing Unit|CPU]], to allow later [[conditional branch]es to divert the [[control flow]] in the program, depending on the results of the arithmetic operation.

Combinations of various condition code bits can be interpreted for both [[two's complement]] signed computations as well as unsigned.

The basic set of condition code bits are:

* Z (Zero) - the result was 0
* N or S (Negative or Sign) - the result was negative
* V or O (OVerflow) - the result produced an overflow
* C (Carry) - the result produced a carry

'Negative' means that the result had the high bit set (i.e. when considered as a signed numbet, was negative). 'Carry' means that a carry occurred out of the top bit (e.g. a unsigned result that could not fit in the word length being used); 'Overflow' means that result, considered as a signed number, had a different sign from the operands (e.g. adding one to the largest possible positive number on a two's complement machine).

The concept was first used in the [[PDP-11]]. Some machines (e.g. the [[Motorola M68000 Family]]) use this scheme exactly; others (e.g. the [[Intel 8086]] and descendants) add more condition code bits, e.g.:

* P - Parity
* A - Auxiliary carry

Some machines carry the condition codes in the [[Processor Status Word]] [[register]], others (e.g. the Intel 8086) have a special 'Flags' register for them.

===Conditional branches===

By testing these bits, the complete complement of signed and unsigned conditional branches can be produced. E.g., on the PDP-11,
this includes:

* BEQ - Zero, or equal (after comparing two quantities)
* BNE - Non-zero, or not equal
* BPL - Positive
* BMI - Negative
* BCS - Carry
* BCC - No Carry
* BVS - Overflow
* BVC - No Oveflow

Signed:

* BGE - Greater or Equal
* BGT - Greater
* BLE - Lesser or Equal
* BLT - Lesser

Unsigned:

* BLOS - Lower or the same
* BLO - Lower
* BHIS - Higher or the same
* BHI - Higher

@@ Line 1: / Line 1: @@
 '''Condition codes''' are a way of recording high-level information about the results of arithmetic operations in a [[Central Processing Unit|CPU]], to allow later [[conditional branch]]es to divert the [[control flow]] in the program, depending on the results of the arithmetic operation.
-Combinations of various condition code bits can be interpreted for both [[two's complement]] signed computations as well as unsigned.
+Combinations of various condition code bits can be interpreted for both [[two's complement]] signed computations as well as unsigned. By testing these bits, the complete set of signed and unsigned conditional branches can be produced.
-The basic set of condition code bits are:
+The basic group of condition code bits are:
 * Z (Zero) - the result was 0
@@ Line 19: / Line 18: @@
 Some machines carry the condition codes in the [[Processor Status Word]] [[register]], others (e.g. the Intel 8086) have a special 'Flags' register for them.
 [[Category: CPU Basics]]

← Older revision		Revision as of 14:24, 15 December 2018
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	Some machines carry the condition codes in the [[Processor Status Word]] [[register]], others (e.g. the Intel 8086) have a special 'Flags' register for them.		Some machines carry the condition codes in the [[Processor Status Word]] [[register]], others (e.g. the Intel 8086) have a special 'Flags' register for them.
		+
		+	[[Category: CPU Basics]]

← Older revision		Revision as of 01:36, 21 October 2017
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−	'''Condition codes''' are a way of recording high-level information about the results of arithmetic operations in a [[Central Processing Unit\|CPU]], to allow later [[conditional branch]es to divert the [[control flow]] in the program, depending on the results of the arithmetic operation.	+	'''Condition codes''' are a way of recording high-level information about the results of arithmetic operations in a [[Central Processing Unit\|CPU]], to allow later [[conditional branch]]es to divert the [[control flow]] in the program, depending on the results of the arithmetic operation.

	Combinations of various condition code bits can be interpreted for both [[two's complement]] signed computations as well as unsigned.		Combinations of various condition code bits can be interpreted for both [[two's complement]] signed computations as well as unsigned.

@@ Line 10: / Line 10: @@
 * C (Carry) - the result produced a carry
-'Negative' means that the result had the high bit set (i.e. when considered as a signed numbet, was negative). 'Carry' means that a carry occurred out of the top bit (e.g. a unsigned result that could not fit in the word length being used); 'Overflow' means that result, considered as a signed number, had a different sign from the operands (e.g. adding one to the largest possible positive number on a two's complement machine).
+'Negative' means that the result had the high bit set (i.e. when considered as a signed number, was negative). 'Carry' means that a carry occurred out of the top bit (e.g. a unsigned result that could not fit in the word length being used); 'Overflow' means that result, considered as a signed number, had a different sign from the operands (e.g. adding one to the largest possible positive number on a two's complement machine).
 The concept was first used in the [[PDP-11]]. Some machines (e.g. the [[Motorola M68000 Family]]) use this scheme exactly; others (e.g. the [[Intel 8086]] and descendants) add more condition code bits, e.g.:
@@ Line 19: / Line 19: @@
 Some machines carry the condition codes in the [[Processor Status Word]] [[register]], others (e.g. the Intel 8086) have a special 'Flags' register for them.
-===Conditional branches===
+==Conditional branches==
 By testing these bits, the complete complement of signed and unsigned conditional branches can be produced. E.g., on the PDP-11,