DL10 PDP-11 Data Link - Revision history

Jnc: /* External links */ +KL10-Based Physical Description

2023-11-07T15:27:53Z

‎External links: +KL10-Based Physical Description

Jnc: Used in DN87

2023-11-07T14:28:10Z

Used in DN87

Jnc: On the KL10, needs both Memory and I/O bus adapters

2023-11-06T12:11:50Z

On the KL10, needs both Memory and I/O bus adapters

Jnc: +cat

2022-11-26T00:24:23Z

+cat

Jnc: Fix missing register bit errs; link to new pages

2022-10-25T13:21:48Z

Fix missing register bit errs; link to new pages

Jnc: Jnc moved page DL10 to DL10 PDP-11 Data Link: Formal DEC name

2022-09-23T19:51:23Z

Jnc moved page DL10 to DL10 PDP-11 Data Link: Formal DEC name

Jnc: typo

2022-09-23T19:50:55Z

typo

Jnc: DEC-10-XSRMA-A-D says this is its official name

2022-09-23T19:50:27Z

DEC-10-XSRMA-A-D says this is its official name

Jnc: /* External links */ hardcopy pages

2022-09-23T18:11:59Z

‎External links: hardcopy pages

Jnc: /* External links */ new cat

2022-09-21T18:20:31Z

‎External links: new cat

@@ Line 113: / Line 113: @@
 * [http://pdp-10.trailing-edge.com/bb-d549g-sb/01/boot11.mem.html BOOT11 - PDP-11 Bootstrap From PDP-10] - contains general description of the DL10 in section 4.0
 * [http://bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-XSRMA-A-D%20DECsystem10%20System%20Reference%20Manual.pdf DECsystem-10 System Reference Manual] - documents the PDP-10's DL10 control instructions in Appendix C (on pp. 365-368 of the PDF)
 * [http://www.bitsavers.org/pdf/dec/pdp10/periph/MP00068_DN87_Universal_Comm_System_Front_End_Jan76.pdf DN87 Field Maintenance Print Set] - contains complete engineering drawings for the DL10 (on pp. 100-212 of the PDF)

← Older revision		Revision as of 14:28, 7 November 2023
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	On the PDP-11 side, PDP-11's connected to the DL10 have a special console which has a cable which goes to the DL10, which allows the PDP-10 to start and stop the PDP-11; the PDP-11's [[UNIBUS]] runs into the DL10 and is plugged into the DL10's backplane.		On the PDP-11 side, PDP-11's connected to the DL10 have a special console which has a cable which goes to the DL10, which allows the PDP-10 to start and stop the PDP-11; the PDP-11's [[UNIBUS]] runs into the DL10 and is plugged into the DL10's backplane.
		+
		+	The DL10 is used in the [[DN87 Universal Synchronous/Asynchronous Communications Front End Subsystem]].

	There is little remaining DL10 documentation, alas; see below for links to what exists online.		There is little remaining DL10 documentation, alas; see below for links to what exists online.

@@ Line 1: / Line 1: @@
 The '''DL10 PDP-11 Data Link''' connects [[PDP-10]] [[mainframe]]s to [[PDP-11]]s used as communication [[front end]]s; up to 4 PDP-11's per DL10. It allows the PDP-10 to 'see' into the PDP-11's [[main memory]], and vice versa (although the ability of the PDP-11 to do so is limited by the DL10's settings).
-On the PDP-10 side, it connected to the [[PDP-10 Memory Bus]], and also up to two [[PDP-10 I/O Bus]]ses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connected to [[KA10]]s and [[KI10]]s, but only to [[KL10]]s with the optional old-style I/O busses (via a [[DIA20 IBus Adapter‎]]).
+On the PDP-10 side, it connected to the [[PDP-10 Memory Bus]], and also up to two [[PDP-10 I/O Bus]]ses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connected to [[KA10]]s and [[KI10]]s, but only to [[KL10]]s with the optional old-style Memory and I/O [[bus]]ses (provided by the [[DMA20 Memory Bus Adapter]] and [[DIA20 IBus Adapter‎]] respectively).
 On the PDP-11 side, PDP-11's connected to the DL10 have a special console which has a cable which goes to the DL10, which allows the PDP-10 to start and stop the PDP-11; the PDP-11's [[UNIBUS]] runs into the DL10 and is plugged into the DL10's backplane.

← Older revision		Revision as of 00:24, 26 November 2022
Line 115:		Line 115:

	[[Category: PDP-10 Machine Interfaces]]		[[Category: PDP-10 Machine Interfaces]]
		+	[[Category: UNIBUS Machine Interfaces]]

@@ Line 1: / Line 1: @@
 The '''DL10 PDP-11 Data Link''' connects [[PDP-10]] [[mainframe]]s to [[PDP-11]]s used as communication [[front end]]s; up to 4 PDP-11's per DL10. It allows the PDP-10 to 'see' into the PDP-11's [[main memory]], and vice versa (although the ability of the PDP-11 to do so is limited by the DL10's settings).
-On the PDP-10 side, it connected to the PDP-10 memory bus, and also to two I/O busses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connected to [[KA10]]s and [[KI10]]s, but only to [[KL10]]s with the optional old-style I/O busses (via a [[DIA20 IBus Adapter‎]]).
+On the PDP-10 side, it connected to the [[PDP-10 Memory Bus]], and also up to two [[PDP-10 I/O Bus]]ses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connected to [[KA10]]s and [[KI10]]s, but only to [[KL10]]s with the optional old-style I/O busses (via a [[DIA20 IBus Adapter‎]]).
 On the PDP-11 side, PDP-11's connected to the DL10 have a special console which has a cable which goes to the DL10, which allows the PDP-10 to start and stop the PDP-11; the PDP-11's [[UNIBUS]] runs into the DL10 and is plugged into the DL10's backplane.
@@ Line 90: / Line 90: @@
 | 11 interrupt || || 10 interrupt || || Nonex memory || ||  Set parity error ||  || Word count overflow || || This port enabled || || Error interrupt enable || 11 interrupt enable || colspan=2 | Interrupt assignment
 {{16bit-bitout}}
 ==PDP-10 standard instructions==
@@ Line 101: / Line 100: @@
 CONO DLC,
 {{36bithalf-header}}
-| Clear DL10 || Lock DL10 || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || colspan=3 | Priority interrupt assignment
+| Clear DL10 || Lock DL10 || Action of 1s ||| 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || colspan=3 | Priority interrupt assignment
 {{36bithalf-bitout}}
 CONI DLB,
 {{36bit-header}}
-| Diag || Diag msyn || Diag C0 || Diag C1 || Diag R2 || Diag R1 || Diag INH CYC || || 11-3 8K option || 11-2 8K option || 11-1 8K option || 11-0 8K option || IOC lock on || ~IOC lock delay on || ~IOC lock 1 out || ~IOC lock 0 out || 18-bit address || ||  Got DL10 locked || || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || colspan=3 | Priority interrupt assignment
+| Diag || Diag msyn || Diag C0 || Diag C1 || Diag R2 || Diag R1 || Diag INH CYC || || 11-3 8K option || 11-2 8K option || 11-1 8K option || 11-0 8K option || IOC lock on || ~IOC lock delay on || ~IOC lock 1 out || ~IOC lock 0 out || 18-bit address || Standard interrupt || || Got DL10 locked || || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || colspan=3 | Priority interrupt assignment
 {{36bit-bitout}}

← Older revision	Revision as of 19:51, 23 September 2022
(No difference)

← Older revision		Revision as of 19:50, 23 September 2022
Line 1:		Line 1:
−	The '''DL10 PDP-11 ~~Dara~~ Link''' connects [[PDP-10]] [[mainframe]]s to [[PDP-11]]s used as communication [[front end]]s; up to 4 PDP-11's per DL10. It allows the PDP-10 to 'see' into the PDP-11's [[main memory]], and vice versa (although the ability of the PDP-11 to do so is limited by the DL10's settings).	+	The '''DL10 PDP-11 Data Link''' connects [[PDP-10]] [[mainframe]]s to [[PDP-11]]s used as communication [[front end]]s; up to 4 PDP-11's per DL10. It allows the PDP-10 to 'see' into the PDP-11's [[main memory]], and vice versa (although the ability of the PDP-11 to do so is limited by the DL10's settings).

	On the PDP-10 side, it connected to the PDP-10 memory bus, and also to two I/O busses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit\|CPU]] system). So, it could be connected to [[KA10]]s and [[KI10]]s, but only to [[KL10]]s with the optional old-style I/O busses (via a [[DIA20 IBus Adapter‎]]).		On the PDP-10 side, it connected to the PDP-10 memory bus, and also to two I/O busses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit\|CPU]] system). So, it could be connected to [[KA10]]s and [[KI10]]s, but only to [[KL10]]s with the optional old-style I/O busses (via a [[DIA20 IBus Adapter‎]]).

@@ Line 1: / Line 1: @@
-The '''DL10 PDP-10/PDP-11 Interface Channel''' connects [[PDP-10]] [[mainframe]]s to [[PDP-11]]s used as communication [[front end]]s; up to 4 PDP-11's per DL10. It allows the PDP-10 to 'see' into the PDP-11's [[main memory]], and vice versa (although the ability of the PDP-11 to do so is limited by the DL10's settings).
+The '''DL10 PDP-11 Dara Link''' connects [[PDP-10]] [[mainframe]]s to [[PDP-11]]s used as communication [[front end]]s; up to 4 PDP-11's per DL10. It allows the PDP-10 to 'see' into the PDP-11's [[main memory]], and vice versa (although the ability of the PDP-11 to do so is limited by the DL10's settings).
 On the PDP-10 side, it connected to the PDP-10 memory bus, and also to two I/O busses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connected to [[KA10]]s and [[KI10]]s, but only to [[KL10]]s with the optional old-style I/O busses (via a [[DIA20 IBus Adapter‎]]).
@@ Line 9: / Line 9: @@
 ==Data formats==
-Note that the format is selected by the second octed in the word; the values used in that octet to select the byte size in the 'pointer' mode are disjoint from the values used in that octet for the other modes.
+Note that the format is selected by the second octet in the word; the values used in that octet to select the byte size in the 'pointer' mode are disjoint from the values used in that octet for the other modes.
 ===Immediate mode===
@@ Line 112: / Line 112: @@
 * [http://pdp-10.trailing-edge.com/bb-d549g-sb/01/boot11.mem.html BOOT11 - PDP-11 Bootstrap From PDP-10] - contains general description of the DL10 in section 4.0
-* [http://bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-XSRMA-A-D%20DECsystem10%20System%20Reference%20Manual.pdf DECsystem-10 System Reference Manual] - documents the PDP-10's DL10 control instructions Appendix C (pp. 365-368 of the PDF)
+* [http://bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-XSRMA-A-D%20DECsystem10%20System%20Reference%20Manual.pdf DECsystem-10 System Reference Manual] - documents the PDP-10's DL10 control instructions in Appendix C (on pp. 365-368 of the PDF)
-* [http://www.bitsavers.org/pdf/dec/pdp10/periph/MP00068_DN87_Universal_Comm_System_Front_End_Jan76.pdf DN87 Field Maintenance Print Set] - contains complete engineering drawings for the DL10 on pp. 100-212
+* [http://www.bitsavers.org/pdf/dec/pdp10/periph/MP00068_DN87_Universal_Comm_System_Front_End_Jan76.pdf DN87 Field Maintenance Print Set] - contains complete engineering drawings for the DL10 (on pp. 100-212 of the PDF)
 [[Category: PDP-10 Machine Interfaces]]

← Older revision		Revision as of 18:20, 21 September 2022
Line 115:		Line 115:
	* [http://www.bitsavers.org/pdf/dec/pdp10/periph/MP00068_DN87_Universal_Comm_System_Front_End_Jan76.pdf DN87 Field Maintenance Print Set] - contains complete engineering drawings for the DL10 on pp. 100-212		* [http://www.bitsavers.org/pdf/dec/pdp10/periph/MP00068_DN87_Universal_Comm_System_Front_End_Jan76.pdf DN87 Field Maintenance Print Set] - contains complete engineering drawings for the DL10 on pp. 100-212

−	[[Category: PDP-~~10s~~]]	+	[[Category: PDP-10 Machine Interfaces]]