DMA20 Memory Bus Adapter - Revision history

Jnc: Bandwidth as well as interleaving

2023-11-09T13:10:55Z

Bandwidth as well as interleaving

Jnc: interleaving cleanup

2023-07-31T01:26:23Z

interleaving cleanup

Jnc: +link

2022-10-24T15:15:24Z

+link

Jnc: Avoid use of internal page tag

2022-09-27T21:11:30Z

Avoid use of internal page tag

Jnc: /* External links */ +Eng drw

2021-10-14T21:06:16Z

‎External links: +Eng drw

Jnc: +img of KBus QL conn

2021-10-12T19:10:29Z

+img of KBus QL conn

Jnc: more details

2021-08-18T15:34:15Z

more details

Jnc: An OK start

2021-08-12T19:01:13Z

An OK start

New page

The '''DMA20 Memory Bus Adapter''' is an optional [[device controller|controller]] on [[KL10]] [[Central Processing Unit|CPUs]] which provides an old-style [[PDP-10#Busses|PDP-10 memory bus]] (termed an 'KBus' here), to allow existing [[PDP-10]] [[core memory|core]] [[main memory]] to be used on one. (In a [[multi-processor]] system, each CPU has a separate DMA20, if configured to have one; the [[multi-port memory]] banks of [[PDP-10 memories]] will allow banks to be shared between CPUs.)

==Implementation==

The DMA20 is connected to the MBox of the KL10 via the SBus. Four separate KBuses are provided per CPU, to allow maximum (for the KL10) [[interleaving]]; the DMA20 can operate in 1-, 2- or 4-bus mode.

It consists of ten [[DEC card form factor|hex]] boards plugged into an I/O [[backplane]] (one shared with the [[DIA20 IBus Adapter‎]]) of the KL10; these are connected to memory bus connectors mounted lower down in that rack.

==External links==

* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-DMA20-UD-002_Oct76.pdf DMA20 Memory Bus Adapter Unit Description]
* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-108OU-PD-002_KL10-Based_Physical_Description_Mar77.pdf KL10-Based Physical Description] - contains images of DMA20 backplanes and wiring, pp. 3-7-3-11; board configuration, pp. 3-27,3-28

[[Category: PDP-10s]]

@@ Line 1: / Line 1: @@
-The '''DMA20 Memory Bus Adapter''' is an optional [[device controller|controller]] on [[KL10]] [[Central Processing Unit|CPUs]] which converts from the KL10's native [[PDP-10 Memory Bus|SBus]] [[main memory]] [[bus]] to an old-style [[PDP-10 Memory Bus]] (termed an 'KBus' here), to allow existing [[PDP-10]] [[core memory|core]] main memory to be used on one. (In a [[multi-processor]] system, each CPU has a separate DMA20, if configured to have one; the [[multi-port memory]] banks of [[PDP-10 memories]] will allow banks to be shared between CPUs.)
+The '''DMA20 Memory Bus Adapter''' is an optional [[device controller|controller]] on [[KL10]] [[Central Processing Unit|CPUs]] which converts from the KL10's native [[PDP-10 Memory Bus|SBus]] [[main memory]] [[bus]] to up to 4 old-style [[PDP-10 Memory Bus]]ses (termed 'KBus' here), to allow existing [[PDP-10]] [[core memory|core]] main memory to be used on one. (In a [[multi-processor]] system, each CPU has a separate DMA20, if configured to have one; the [[multi-port memory]] banks of [[PDP-10 memories]] will allow banks to be shared between CPUs.)
 ==Implementation==
@@ Line 5: / Line 5: @@
 [[Image:KBusQCLatched.jpg|250px|thumb|right|Memory bus Quick Latch connector (in latched position)]]
-The DMA20 is connected to the MBox of the KL10 via the SBus. Four separate KBuses are provided per CPU, to allow maximum (for the KL10) [[memory interleaving|interleaving]]; the DMA20 can operate in 1-, 2- or 4-bus mode.
+The DMA20 is connected to the MBox of the KL10 via the SBus. As mentioned, it provides four separate KBuses per CPU, to increase memory bandwidth, as well allow maximum [[memory interleaving|interleaving]]; the DMA20 can operate in 1-, 2- or 4-bus mode.
 It consists of ten [[DEC card form factor|hex]] boards (an M8560, M8563, and eight M8558 modules) plugged into an I/O [[backplane]] (one shared with the [[DIA20 IBus Adapter‎]]) of the KL10; these are connected to memory bus connectors mounted lower down in that rack.

@@ Line 5: / Line 5: @@
 [[Image:KBusQCLatched.jpg|250px|thumb|right|Memory bus Quick Latch connector (in latched position)]]
-The DMA20 is connected to the MBox of the KL10 via the SBus. Four separate KBuses are provided per CPU, to allow maximum (for the KL10) [[interleaving]]; the DMA20 can operate in 1-, 2- or 4-bus mode.
+The DMA20 is connected to the MBox of the KL10 via the SBus. Four separate KBuses are provided per CPU, to allow maximum (for the KL10) [[memory interleaving|interleaving]]; the DMA20 can operate in 1-, 2- or 4-bus mode.
 It consists of ten [[DEC card form factor|hex]] boards (an M8560, M8563, and eight M8558 modules) plugged into an I/O [[backplane]] (one shared with the [[DIA20 IBus Adapter‎]]) of the KL10; these are connected to memory bus connectors mounted lower down in that rack.

← Older revision		Revision as of 15:15, 24 October 2022
Line 1:		Line 1:
−	The '''DMA20 Memory Bus Adapter''' is an optional [[device controller\|controller]] on [[KL10]] [[Central Processing Unit\|CPUs]] which converts from the KL10's native SBus [[main memory]] [[bus]] to an old-style [[PDP-10 Memory Bus]] (termed an 'KBus' here), to allow existing [[PDP-10]] [[core memory\|core]] main memory to be used on one. (In a [[multi-processor]] system, each CPU has a separate DMA20, if configured to have one; the [[multi-port memory]] banks of [[PDP-10 memories]] will allow banks to be shared between CPUs.)	+	The '''DMA20 Memory Bus Adapter''' is an optional [[device controller\|controller]] on [[KL10]] [[Central Processing Unit\|CPUs]] which converts from the KL10's native [[PDP-10 Memory Bus\|SBus]] [[main memory]] [[bus]] to an old-style [[PDP-10 Memory Bus]] (termed an 'KBus' here), to allow existing [[PDP-10]] [[core memory\|core]] main memory to be used on one. (In a [[multi-processor]] system, each CPU has a separate DMA20, if configured to have one; the [[multi-port memory]] banks of [[PDP-10 memories]] will allow banks to be shared between CPUs.)

	==Implementation==		==Implementation==

← Older revision		Revision as of 21:11, 27 September 2022
Line 1:		Line 1:
−	The '''DMA20 Memory Bus Adapter''' is an optional [[device controller\|controller]] on [[KL10]] [[Central Processing Unit\|CPUs]] which converts from the KL10's native SBus [[main memory]] [[bus]] to an old-style [[PDP-10~~#Busses\|PDP-10 memory bus~~]] (termed an 'KBus' here), to allow existing [[PDP-10]] [[core memory\|core]] main memory to be used on one. (In a [[multi-processor]] system, each CPU has a separate DMA20, if configured to have one; the [[multi-port memory]] banks of [[PDP-10 memories]] will allow banks to be shared between CPUs.)	+	The '''DMA20 Memory Bus Adapter''' is an optional [[device controller\|controller]] on [[KL10]] [[Central Processing Unit\|CPUs]] which converts from the KL10's native SBus [[main memory]] [[bus]] to an old-style [[PDP-10 Memory Bus]] (termed an 'KBus' here), to allow existing [[PDP-10]] [[core memory\|core]] main memory to be used on one. (In a [[multi-processor]] system, each CPU has a separate DMA20, if configured to have one; the [[multi-port memory]] banks of [[PDP-10 memories]] will allow banks to be shared between CPUs.)

	==Implementation==		==Implementation==

@@ Line 1: / Line 1: @@
-The '''DMA20 Memory Bus Adapter''' is an optional [[device controller|controller]] on [[KL10]] [[Central Processing Unit|CPUs]] which converts from the KL10's native SBus memory bus to an old-style [[PDP-10#Busses|PDP-10 memory bus]] (termed an 'KBus' here), to allow existing [[PDP-10]] [[core memory|core]] [[main memory]] to be used on one. (In a [[multi-processor]] system, each CPU has a separate DMA20, if configured to have one; the [[multi-port memory]] banks of [[PDP-10 memories]] will allow banks to be shared between CPUs.)
+The '''DMA20 Memory Bus Adapter''' is an optional [[device controller|controller]] on [[KL10]] [[Central Processing Unit|CPUs]] which converts from the KL10's native SBus [[main memory]] [[bus]] to an old-style [[PDP-10#Busses|PDP-10 memory bus]] (termed an 'KBus' here), to allow existing [[PDP-10]] [[core memory|core]] main memory to be used on one. (In a [[multi-processor]] system, each CPU has a separate DMA20, if configured to have one; the [[multi-port memory]] banks of [[PDP-10 memories]] will allow banks to be shared between CPUs.)
 ==Implementation==
 The DMA20 is connected to the MBox of the KL10 via the SBus. Four separate KBuses are provided per CPU, to allow maximum (for the KL10) [[interleaving]]; the DMA20 can operate in 1-, 2- or 4-bus mode.

@@ Line 12: / Line 12: @@
 * [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-DMA20-UD-002_Oct76.pdf DMA20 Memory Bus Adapter Unit Description]
 * [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-108OU-PD-002_KL10-Based_Physical_Description_Mar77.pdf KL10-Based Physical Description] - contains images of DMA20 backplanes and wiring, pp. 3-7-3-11; board configuration, pp. 3-27,3-28
 [[Category: PDP-10s]]