DMA Request and Grant - Revision history

Jnc: /* Further reading */ +DMA Request/Grant Timing

2024-07-27T17:37:23Z

‎Further reading: +DMA Request/Grant Timing

Jnc: typo

2021-11-21T02:01:08Z

typo

Jnc: Fairly complete

2021-11-21T02:00:29Z

Fairly complete

New page

'''DMA Grant Input''' ('''

The '''DMA Request''' and '''DMA Grant''' (usually given as their acronyms, '''DMR''' and '''DMG''') are the two [[conductor|lines]] on the [[QBUS]] used in one of the two kinds of [[bus grant|bus requests]] there; they are for a [[peripheral|device]] to gain control of the QBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle.

The [[Central Processing Unit|CPU]] may not perform ''any'' action (i.e. an [[interrupt]]) while the device has control of the [[bus]] for a DMA request; a device gaining control of the bus via such a request ''may'' perform more than one [[master-slave cycle]] before relinquishing control of the bus, however.

DMR is a normal 'wired-OR' broadcast bus line; DMG is a unidirectional [[bus grant line|grant line]]. In an QBUS [[backplane]] slot, there are a ''pair'' of pins for DMG: AR2 for 'DMG In' (BDMGI), and AS2 for 'DMG Out' (BDMGO). In an empty slot there must be a [[M9047 grant continuity card]] installed, to carry the [[bus grant|grant]] across that slot.

The [[UNIBUS]] has a set of lines with identical functionality, [[Non-Processor Request and Grant]].

[[Category: QBUS]]

← Older revision		Revision as of 17:37, 27 July 2024
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	The [[UNIBUS]] has a set of lines with identical functionality, [[Non-Processor Request and Grant]].		The [[UNIBUS]] has a set of lines with identical functionality, [[Non-Processor Request and Grant]].
		+
		+	==Further reading==
		+
		+	* ''DMA Request/Grant Timing'', [[MicroNote]] #039

	[[Category: QBUS]]		[[Category: QBUS]]

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−	~~'''DMA Grant Input''' ('''~~
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	The '''DMA Request''' and '''DMA Grant''' (usually given as their acronyms, '''DMR''' and '''DMG''') are the two [[conductor\|lines]] on the [[QBUS]] used in one of the two kinds of [[bus grant\|bus requests]] there; they are for a [[peripheral\|device]] to gain control of the QBUS's data section so that it may perform a [[Direct Memory Access\|DMA]] cycle.		The '''DMA Request''' and '''DMA Grant''' (usually given as their acronyms, '''DMR''' and '''DMG''') are the two [[conductor\|lines]] on the [[QBUS]] used in one of the two kinds of [[bus grant\|bus requests]] there; they are for a [[peripheral\|device]] to gain control of the QBUS's data section so that it may perform a [[Direct Memory Access\|DMA]] cycle.