DR11-B parallel interface - Revision history

Jnc: /* External links */ +manual

2022-11-25T01:15:53Z

‎External links: +manual

Jnc: /* External links */ +manual

2022-01-13T22:30:21Z

‎External links: +manual

Jnc: move to new subcat

2020-06-09T11:46:55Z

move to new subcat

Jnc: /* Implementation */ swapped, err

2020-02-18T18:45:04Z

‎Implementation: swapped, err

Jnc: /* Implementation */ +link

2020-02-18T18:43:43Z

‎Implementation: +link

Jnc: /* Registers */ Note no addr overflow

2019-02-11T18:21:02Z

‎Registers: Note no addr overflow

Jnc: fmt

2018-11-30T16:58:35Z

fmt

Jnc: /* Registers */ Grr! Effing doc!

2018-11-30T16:58:02Z

‎Registers: Grr! Effing doc!

Jnc: Add registers, interface details

2018-11-30T16:47:21Z

Add registers, interface details

Jnc: Add links

2018-03-19T19:23:11Z

Add links

@@ Line 136: / Line 136: @@
 ==External links==
 * [http://www.bitsavers.org/pdf/dec/unibus/EK-DR11B-TM-004_DR11-B_DA11-B_Manual_Sep74.pdf DR11-B/DA11-B manual] (EK-DR11B-TM-004)
 [[Category: UNIBUS Parallel Interfaces]]

@@ Line 1: / Line 1: @@
 The '''DR11-B''' was a [[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data to a user device.
-It was constructed from a number of smaller [[FLIP CHIP]]s which were installed in custom 4-slot [[backplane]] [[system unit]].
+The interface between the DR11-B and the user device uses a number of unidirectional control lines (below), which control data transfer; and sets of three 'status' and 'control' lines, which appear in the Status and Command Register. By appropriate manipulation of the control lines, the user device can do byte or word cycles on the bus, perform read-modify-write bus cycles, or do block 'burst' bus transfers.
 Data going to the user device is [[buffer]]ed in a set of [[latch]]es; data coming from the user device is ''not'' buffered, and must be held valid for the duration of the resultant bus cycle.
@@ Line 94: / Line 90: @@
 ==Implementation==
 The extant DR11-B documentation does not show either the modules used in the DR11-B, or their locations in the backplane, so that information is given here.
@@ Line 131: / Line 129: @@
 Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]s).
 [[Category: UNIBUS Parallel Interfaces]]

← Older revision		Revision as of 11:46, 9 June 2020
Line 132:		Line 132:
	Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]s).		Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]s).

−	[[Category:UNIBUS ~~Peripherals~~]]	+	[[Category: UNIBUS Parallel Interfaces]]

@@ Line 107: / Line 107: @@
 * 2 x M611 - High speed power inverters
 * M796 - UNIBUS Master Control
-* [[M7821|M782 Interrupt Control]] - [[Interrupt]] Control
+* [[M782 Interrupt Control|M7821]] - [[Interrupt]] Control
 * M7219 - Bus Interface

@@ Line 107: / Line 107: @@
 * 2 x M611 - High speed power inverters
 * M796 - UNIBUS Master Control
-* M7821 - [[Interrupt]] Control
+* [[M7821|M782 Interrupt Control]] - [[Interrupt]] Control
 * M7219 - Bus Interface

← Older revision		Revision as of 18:21, 11 February 2019
Line 45:		Line 45:
	{{16bit-bitout}}		{{16bit-bitout}}

		+	Note: Unlike most DEC DMA devices, an overflow in the Bus Address Register does not carry into the Extended Memory bits in the CSR.

	==User Device Interface==		==User Device Interface==

@@ Line 44: / Line 44: @@
 | colspan=16 | Data15 <---> Data00
 {{16bit-bitout}}
 ==User Device Interface==

@@ Line 14: / Line 14: @@
 ! Register !! Abbreviation !! Address
 |-
-|Status and Command Register    || DRST || 772410
+|Word Count Register            || DRWC || 772410
 |-
-|Word Count Register            || DRWC || 772412
+|Bus Address Register           || DRBA || 772412
 |-
-|Bus Address Register           || DRBA || 772414
+|Status and Command Register    || DRST || 772414
 |-
 |Data Buffer Register           || DRDB || 772416
@@ Line 25: / Line 25: @@
 The [[address]]es shown are for the first DR11-B in a system; additional ones are normally set to be at 772430, 772450, 772470, etc.
-===772410: Status and Command Register (DRST)===
+===772410: Word Count Register (DRWC)===
 {{16bit-header}}
-| ERROR || NEX || ATTN || MAINT || colspan=3 | DSTAT A-C || CYCLE || READY || IE || colspan=2 | XBA16-17 || colspan=3 | FNCT1-3 || GO
+| colspan=16 | WC15 <---> WC00
 {{16bit-bitout}}
-===772412: Word Count Register (DRWC)===
+===772412: Bus Address Register (DRBA)===
 {{16bit-header}}
-| colspan=16 | WC15 <---> WC00
+| colspan=16 | BA15 <---> BA00
 {{16bit-bitout}}
-===772414: Bus Address Register (DRBA)===
+===772414: Status and Command Register (DRST)===
 {{16bit-header}}
-| colspan=16 | BA15 <---> BA00
+| ERROR || NEX || ATTN || MAINT || colspan=3 | DSTAT A-C || CYCLE || READY || IE || colspan=2 | XBA16-17 || colspan=3 | FNCT1-3 || GO
 {{16bit-bitout}}
@@ Line 44: / Line 44: @@
 | colspan=16 | Data15 <---> Data00
 {{16bit-bitout}}
 ==User Device Interface==

@@ Line 1: / Line 1: @@
-The '''DR11-B''' was a parallel interface for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data.
+The '''DR11-B''' was a [[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data to a user device.
 ==Implementation==
-It was constructed from a number of smaller [[FLIP CHIP]]s which were installed in custom 4-slot [[backplane]] [[system unit]]. The extant DR11-B documentation does not show either the modules used in the DR11-B, or their locations in the backplane, so that information is given here.
+The extant DR11-B documentation does not show either the modules used in the DR11-B, or their locations in the backplane, so that information is given here.
 The modules are:
@@ Line 38: / Line 129: @@
 Connection to the user device is via either a pair of M957 Split-Lug Cable boards, or via an M9760 (dual) Twisted Pair Cable Connector board. The M9680 (dual) board is a loopback test board, which can be inserted in place of the user connection board(s).
-Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]).
+Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]s).
 [[Category:UNIBUS Peripherals]]

@@ Line 1: / Line 1: @@
-The '''DR11-B''' was a parallel interface for the UNIBUS, one which used [[DMA]] to transfer data.
+The '''DR11-B''' was a parallel interface for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data.
 ==Implementation==
@@ Line 10: / Line 10: @@
 * M113 - 10 x 2-input NAND gates
 * M116 - 6 x 4-input NOR gates
-* M205 - 5 x 'D' flip flops
+* M205 - 5 x 'D' [[flip-flop]]s
 * 2 x M208 - 8-bit buffer / shift-register
 * M239 - 3 x 4-bit counter/register
 * 2 x M611 - High speed power inverters
 * M796 - UNIBUS Master Control
-* M7821 - Interrupt Control
+* M7821 - [[Interrupt]] Control
 * M7219 - Bus Interface
@@ Line 38: / Line 38: @@
 Connection to the user device is via either a pair of M957 Split-Lug Cable boards, or via an M9760 (dual) Twisted Pair Cable Connector board. The M9680 (dual) board is a loopback test board, which can be inserted in place of the user connection board(s).
-Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of PDP-11).
+Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]).
 {{PDP-11}}
 [[Category:UNIBUS Peripherals]]