DR11-B parallel interface - Revision history

Jnc: /* External links */ +manual

2022-11-25T01:15:53Z

External links: +manual

← Older revision		Revision as of 01:15, 25 November 2022
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	==External links==		==External links==

			* [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-11-HDRBA-D-D%20DR11-B&DA11-B%20Manual.pdf DR11-B/DA11-B manual] (DEC-11-HDRBA-D-D)
	* [http://www.bitsavers.org/pdf/dec/unibus/EK-DR11B-TM-004_DR11-B_DA11-B_Manual_Sep74.pdf DR11-B/DA11-B manual] (EK-DR11B-TM-004)		* [http://www.bitsavers.org/pdf/dec/unibus/EK-DR11B-TM-004_DR11-B_DA11-B_Manual_Sep74.pdf DR11-B/DA11-B manual] (EK-DR11B-TM-004)

	[[Category: UNIBUS Parallel Interfaces]]		[[Category: UNIBUS Parallel Interfaces]]

Jnc: /* External links */ +manual

2022-01-13T22:30:21Z

External links: +manual

← Older revision		Revision as of 22:30, 13 January 2022
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	The '''DR11-B''' was a [[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access\|DMA]] to transfer data to a user device.		The '''DR11-B''' was a [[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access\|DMA]] to transfer data to a user device.

	~~It was constructed from a number of smaller [[FLIP CHIP]]s which were installed in custom 4-slot [[backplane]] [[system unit]].~~		The interface between the DR11-B and the user device uses a number of unidirectional control lines (below), which control data transfer; and sets of three 'status' and 'control' lines, which appear in the Status and Command Register. By appropriate manipulation of the control lines, the user device can do byte or word cycles on the bus, perform read-modify-write bus cycles, or do block 'burst' bus transfers.

	The interface between the DR11-B and the user device uses a number of unidirectional control lines (below), which control data transfer; and sets of three 'status' and 'control' lines, which appear in the Status and Command Register.

	By appropriate manipulation of the control lines, the user device can do byte or word cycles on the bus, perform read-modify-write bus cycles, or do block 'burst' bus transfers.

	Data going to the user device is [[buffer]]ed in a set of [[latch]]es; data coming from the user device is ''not'' buffered, and must be held valid for the duration of the resultant bus cycle.		Data going to the user device is [[buffer]]ed in a set of [[latch]]es; data coming from the user device is ''not'' buffered, and must be held valid for the duration of the resultant bus cycle.
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	==Implementation==		==Implementation==

			It was constructed from a number of smaller [[FLIP CHIP]]s which were installed in custom 4-slot [[system unit]] [[backplane]].

	The extant DR11-B documentation does not show either the modules used in the DR11-B, or their locations in the backplane, so that information is given here.		The extant DR11-B documentation does not show either the modules used in the DR11-B, or their locations in the backplane, so that information is given here.
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	Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]s).		Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]s).

			==Further reading==

			* ''DRll-B Engineering Drawings'' - not online at this time

			==External links==

			* [http://www.bitsavers.org/pdf/dec/unibus/EK-DR11B-TM-004_DR11-B_DA11-B_Manual_Sep74.pdf DR11-B/DA11-B manual] (EK-DR11B-TM-004)

	[[Category: UNIBUS Parallel Interfaces]]		[[Category: UNIBUS Parallel Interfaces]]

Jnc: move to new subcat

2020-06-09T11:46:55Z

move to new subcat

← Older revision		Revision as of 11:46, 9 June 2020
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	Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]s).		Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]s).

	[[Category:UNIBUS ~~Peripherals~~]]		[[Category: UNIBUS Parallel Interfaces]]

Jnc: /* Implementation */ swapped, err

2020-02-18T18:45:04Z

Implementation: swapped, err

← Older revision		Revision as of 18:45, 18 February 2020
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	* 2 x M611 - High speed power inverters		* 2 x M611 - High speed power inverters
	* M796 - UNIBUS Master Control		* M796 - UNIBUS Master Control
	* [[~~M7821\|~~M782 Interrupt Control]] - [[Interrupt]] Control		* [[M782 Interrupt Control\|M7821]] - [[Interrupt]] Control
	* M7219 - Bus Interface		* M7219 - Bus Interface

Jnc: /* Implementation */ +link

2020-02-18T18:43:43Z

Implementation: +link

← Older revision		Revision as of 18:43, 18 February 2020
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	* 2 x M611 - High speed power inverters		* 2 x M611 - High speed power inverters
	* M796 - UNIBUS Master Control		* M796 - UNIBUS Master Control
	* M7821 - [[Interrupt]] Control		* [[M7821\|M782 Interrupt Control]] - [[Interrupt]] Control
	* M7219 - Bus Interface		* M7219 - Bus Interface

Jnc: /* Registers */ Note no addr overflow

2019-02-11T18:21:02Z

Registers: Note no addr overflow

← Older revision		Revision as of 18:21, 11 February 2019
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	{{16bit-bitout}}		{{16bit-bitout}}

			Note: Unlike most DEC DMA devices, an overflow in the Bus Address Register does not carry into the Extended Memory bits in the CSR.

	==User Device Interface==		==User Device Interface==

Jnc: fmt

2018-11-30T16:58:35Z

fmt

← Older revision		Revision as of 16:58, 30 November 2018
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	\| colspan=16 \| Data15 <---> Data00		\| colspan=16 \| Data15 <---> Data00
	{{16bit-bitout}}		{{16bit-bitout}}


	==User Device Interface==		==User Device Interface==

Jnc: /* Registers */ Grr! Effing doc!

2018-11-30T16:58:02Z

Registers: Grr! Effing doc!

← Older revision		Revision as of 16:58, 30 November 2018
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	! Register !! Abbreviation !! Address		! Register !! Abbreviation !! Address
	\|-		\|-
	\|~~Status and Command~~ Register \|\| ~~DRST~~ \|\| 772410		\|Word Count Register \|\| DRWC \|\| 772410
	\|-		\|-
	\|~~Word Count~~ Register \|\| ~~DRWC~~ \|\| 772412		\|Bus Address Register \|\| DRBA \|\| 772412
	\|-		\|-
	\|~~Bus Address~~ Register \|\| ~~DRBA~~ \|\| 772414		\|Status and Command Register \|\| DRST \|\| 772414
	\|-		\|-
	\|Data Buffer Register \|\| DRDB \|\| 772416		\|Data Buffer Register \|\| DRDB \|\| 772416
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	The [[address]]es shown are for the first DR11-B in a system; additional ones are normally set to be at 772430, 772450, 772470, etc.		The [[address]]es shown are for the first DR11-B in a system; additional ones are normally set to be at 772430, 772450, 772470, etc.

	===772410: ~~Status and Command~~ Register (~~DRST~~)===		===772410: Word Count Register (DRWC)===
	{{16bit-header}}		{{16bit-header}}
	~~\| ERROR \|\| NEX \|\| ATTN \|\| MAINT \|~~\| colspan=3 \| ~~DSTAT A~~-~~C \|\| CYCLE \|\| READY \|\| IE \|\| colspan=2 \| XBA16~~-~~17 \|\| colspan=3 \| FNCT1~~-~~3 \|\| GO~~		\| colspan=16 \| WC15 <---> WC00
	{{16bit-bitout}}		{{16bit-bitout}}

	===772412: ~~Word Count~~ Register (~~DRWC~~)===		===772412: Bus Address Register (DRBA)===
	{{16bit-header}}		{{16bit-header}}
	\| colspan=16 \| ~~WC15~~ <---> ~~WC00~~		\| colspan=16 \| BA15 <---> BA00
	{{16bit-bitout}}		{{16bit-bitout}}

	===772414: ~~Bus Address~~ Register (~~DRBA~~)===		===772414: Status and Command Register (DRST)===
	{{16bit-header}}		{{16bit-header}}
	\| colspan=16 \| ~~BA15 <~~---~~> BA00~~		\| ERROR \|\| NEX \|\| ATTN \|\| MAINT \|\| colspan=3 \| DSTAT A-C \|\| CYCLE \|\| READY \|\| IE \|\| colspan=2 \| XBA16-17 \|\| colspan=3 \| FNCT1-3 \|\| GO
	{{16bit-bitout}}		{{16bit-bitout}}

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	\| colspan=16 \| Data15 <---> Data00		\| colspan=16 \| Data15 <---> Data00
	{{16bit-bitout}}		{{16bit-bitout}}


	==User Device Interface==		==User Device Interface==

Jnc: Add registers, interface details

2018-11-30T16:47:21Z

Add registers, interface details

@@ Line 1: / Line 1: @@
-The '''DR11-B''' was a parallel interface for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data.
+The '''DR11-B''' was a [[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data to a user device.
 ==Implementation==
-It was constructed from a number of smaller [[FLIP CHIP]]s which were installed in custom 4-slot [[backplane]] [[system unit]]. The extant DR11-B documentation does not show either the modules used in the DR11-B, or their locations in the backplane, so that information is given here.
+The extant DR11-B documentation does not show either the modules used in the DR11-B, or their locations in the backplane, so that information is given here.
 The modules are:
@@ Line 38: / Line 129: @@
 Connection to the user device is via either a pair of M957 Split-Lug Cable boards, or via an M9760 (dual) Twisted Pair Cable Connector board. The M9680 (dual) board is a loopback test board, which can be inserted in place of the user connection board(s).
-Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]).
+Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]s).
 [[Category:UNIBUS Peripherals]]

Jnc: Add links

2018-03-19T19:23:11Z

Add links

← Older revision		Revision as of 19:23, 19 March 2018
Line 1:		Line 1:
	The '''DR11-B''' was a parallel interface for the UNIBUS, one which used [[DMA]] to transfer data.		The '''DR11-B''' was a parallel interface for the [[UNIBUS]], one which used [[Direct Memory Access\|DMA]] to transfer data.

	==Implementation==		==Implementation==
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	* M113 - 10 x 2-input NAND gates		* M113 - 10 x 2-input NAND gates
	* M116 - 6 x 4-input NOR gates		* M116 - 6 x 4-input NOR gates
	* M205 - 5 x 'D' flip ~~flops~~		* M205 - 5 x 'D' [[flip-flop]]s
	* 2 x M208 - 8-bit buffer / shift-register		* 2 x M208 - 8-bit buffer / shift-register
	* M239 - 3 x 4-bit counter/register		* M239 - 3 x 4-bit counter/register
	* 2 x M611 - High speed power inverters		* 2 x M611 - High speed power inverters
	* M796 - UNIBUS Master Control		* M796 - UNIBUS Master Control
	* M7821 - Interrupt Control		* M7821 - [[Interrupt]] Control
	* M7219 - Bus Interface		* M7219 - Bus Interface

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	Connection to the user device is via either a pair of M957 Split-Lug Cable boards, or via an M9760 (dual) Twisted Pair Cable Connector board. The M9680 (dual) board is a loopback test board, which can be inserted in place of the user connection board(s).		Connection to the user device is via either a pair of M957 Split-Lug Cable boards, or via an M9760 (dual) Twisted Pair Cable Connector board. The M9680 (dual) board is a loopback test board, which can be inserted in place of the user connection board(s).

	Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of PDP-11).		Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]).

	{{PDP-11}}		{{PDP-11}}

	[[Category:UNIBUS Peripherals]]		[[Category:UNIBUS Peripherals]]