DR11-L general-purpose interface - Revision history

Jnc: /* Further reading */ +manual, FMPS

2022-11-24T19:24:54Z

‎Further reading: +manual, FMPS

Jnc: /* Registers */ typo

2021-08-31T18:39:12Z

‎Registers: typo

Jnc: Save another image)

2021-08-27T09:36:49Z

Save another image)

Jnc: move to new subcat

2020-06-09T11:49:56Z

move to new subcat

Jnc: Jnc moved page DR11-L parallel interface to DR11-L general-purpose interface without leaving a redirect: offical DEC name

2020-05-13T13:17:59Z

Jnc moved page DR11-L parallel interface to DR11-L general-purpose interface without leaving a redirect: offical DEC name

Jnc: +Registers

2020-05-13T02:37:57Z

+Registers

Jnc: fix img fie name

2020-04-16T18:25:41Z

fix img fie name

Jnc: OK start

2020-04-16T17:58:11Z

OK start

New page

[[Image:DR11-L.jpeg|thumb|200px|right|DR11-L board]]

The '''DR11-L general-purpose interface''' was a [[UNIBUS]] [[device controller]] which provided a pair of 16-[[bit]] parallel ports, both input-only. It was a [[DEC card form factor|quad]] format card ('''M7864'''), and used an [[Small Peripheral Controller|SPC]] slot; it used [[programmed I/O]].

Connection to the [[user]]'s device is via a pair of 40-[[pin]] [[Berg connector]]s; each is controlled by a separate set of [[register]]s (identical for the two connectors).

The DR11-L is roughly an input-only version of the earlier [[DR11-C general device interface]], but is not [[program compatible]] with the DR11-C.


[[Category:UNIBUS Peripherals]]

@@ Line 1: / Line 1: @@
-[[Image:DR11-L.jpg|thumb|200px|right|DR11-L board]]
+[[Image:DR11-L.jpg|thumb|300px|right|DR11-L board]]
 The '''DR11-L general-purpose interface''' was a [[UNIBUS]] [[device controller]] which provided a pair of 16-[[bit]] parallel ports, both input-only. It was a [[DEC card form factor|quad]] format card ('''M7864'''), and used an [[Small Peripheral Controller|SPC]] slot; it used [[programmed I/O]].
@@ Line 8: / Line 8: @@
 ==Configuration==
 The device's [[register]] and [[interrupt vector]] [[address]]es are set by a pair of [[Dual Inline Package|DIP]] switches. Unusually for a UNIBUS device, its [[interrupt]] priority is also set by the switches. Both the vector and priority may be read in the Control and Status Register.
@@ Line 48: / Line 50: @@
 {{16bit-bitout}}
-[[Image:M7864.jpg|300px|left|thumb|Another DR11-L board]]
+==Further reading==
 [[Category: UNIBUS Parallel Interfaces]]

@@ Line 24: / Line 24: @@
 |Control and Status Register B || DRCSRB || 764004
 |-
-|Datia Buffer Register B || DBDBRB || 764006
+|Data Buffer Register B || DBDBRB || 764006
 |}

← Older revision		Revision as of 11:49, 9 June 2020
Line 48:		Line 48:
	{{16bit-bitout}}		{{16bit-bitout}}

−	[[Category:UNIBUS ~~Peripherals~~]]	+	[[Category: UNIBUS Parallel Interfaces]]

← Older revision		Revision as of 18:25, 16 April 2020
Line 1:		Line 1:
−	[[Image:DR11-L.~~jpeg~~\|thumb\|200px\|right\|DR11-L board]]	+	[[Image:DR11-L.jpg\|thumb\|200px\|right\|DR11-L board]]

	The '''DR11-L general-purpose interface''' was a [[UNIBUS]] [[device controller]] which provided a pair of 16-[[bit]] parallel ports, both input-only. It was a [[DEC card form factor\|quad]] format card ('''M7864'''), and used an [[Small Peripheral Controller\|SPC]] slot; it used [[programmed I/O]].		The '''DR11-L general-purpose interface''' was a [[UNIBUS]] [[device controller]] which provided a pair of 16-[[bit]] parallel ports, both input-only. It was a [[DEC card form factor\|quad]] format card ('''M7864'''), and used an [[Small Peripheral Controller\|SPC]] slot; it used [[programmed I/O]].

← Older revision	Revision as of 13:17, 13 May 2020
(No difference)

@@ Line 3: / Line 3: @@
 The '''DR11-L general-purpose interface''' was a [[UNIBUS]] [[device controller]] which provided a pair of 16-[[bit]] parallel ports, both input-only. It was a [[DEC card form factor|quad]] format card ('''M7864'''), and used an [[Small Peripheral Controller|SPC]] slot; it used [[programmed I/O]].
-Connection to the [[user]]'s device is via a pair of 40-[[pin]] [[Berg connector]]s; each is controlled by a separate set of [[register]]s (identical for the two connectors).
+The DR11-L is roughly an input-only version of the earlier [[DR11-C general device interface]], but is not [[program compatible]] with the DR11-C.
 ==Registers==
-The device has three control and [[buffer]] [[register]]s, which can be configured to any three sequential [[word]] locations in the I/O page; the first DR11-C is normally configured to [[address]]es 767770-767774:
+The device has two pairs of control and [[buffer]] registers, which can be configured to any four sequential [[word]] locations in the I/O page; the first DR11-L is normally configured to addresses 764000-76406:
 {| border=1
 ! Register !! Abbreviation !! Address
 |-
-|Control and Status Register || DRCSR || 767770
+|Control and Status Register A || DRCSRA || 764000
 |-
-|Output Buffer Register || DROUTBUF || 767772
+|Control and Status Register B || DRCSRB || 764004
 |-
-|Input Buffer Register || DRINBUF || 767774
+|Datia Buffer Register B || DBDBRB || 764006
 |}
 In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics''.
-===Status Register (DRCSR)===
+===Control and Status Register (DRCSR)===
 {{16bit-header}}
-| ''REQ B'' || colspan=7 | Unused || ''REQ A'' || INT ENB A || INT ENB B || colspan=3 | Unused || CSR1 || CSR0
+| ''SI'' || colspan=6 | ''Vector'' || SO || ''RQ'' || RQE || colspan=2 | ''Prority'' || ''DR'' || ''CID'' || ''DL'' || DAE
 {{16bit-bitout}}
-* REQ B - Request B - Signal from user's hardware which can be tested, or cause an [[interrupt]] (below)
+* SI - Status In: Signal from user's hardware which can be tested
-* REQ A - Request A
+* SO - Status Out: Signal to user's hardware
-* INT ENB A - Interrupt Enable A - When set, allows setting REQ A to cause an interrupt
+* RQ - Request: Signal from user's hardware which can be tested, or cause an interrupt
-* INT ENB B - Interrupt Enable B
+* RQE - Request Enable: Allows setting RQ to cause an interrupt
-* CSR1 - Signal to user's hardware (on connector 1)
+* DR - Data Ready: Monitors the Data Ready In signal
-* CSR0 - Signal to user's hardware (on connector 2)
+* CID - CSR ID
-===Input Buffer Register (INBUF)===
+===Data Buffer Register (DRDBR)===
 {{16bit-header}}
 | colspan=16 | ''IN15 <-> IN0''
 {{16bit-bitout}}
 [[Category:UNIBUS Peripherals]]