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2021-12-02T15:48:36Z

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Jnc: Jnc moved page DR11-W Direct Memory Interface to DR11-W Direct Memory Access Interface: DEC formal name

2021-12-02T15:41:56Z

Jnc moved page DR11-W Direct Memory Interface to DR11-W Direct Memory Access Interface: DEC formal name

Jnc: Fairly complete

2021-12-02T15:41:29Z

Fairly complete

New page

The '''DR11-W Direct Memory Access Interface''' was a [[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data to a user device. It was a single [[DEC card form factor|hex]] card (the '''Mxxxx''') replacement for the earlier multi-card [[DR11-B parallel interface]]. The DR11-W is somewhat [[program compatible]] with the DR11-B.

By appropriate manipulation of the control lines (below), the user device can do [[byte]] or [[word]] cycles on the [[bus]], perform read-modify-write bus cycles, or do block 'burst' bus transfers. The DR11-W can also be operated by [[programmed I/O]], potentially via [[interrupt]]s.

Like the DR11-B, the interface between the DR11-W and the user device uses a number of unidirectional control lines (below), which control data transfer; and sets of three 'status' and 'control' lines, which appear in the Status and Command Register. Data going to the user device is [[buffer]]ed in a set of [[latch]]es; data coming from the user device is also buffered, and is sampled and latched when i) the input buffer register (below) is read, or ii) either 'Cycle Request' input [[conductor|line]] is asserted.

The [[register]] [[address]]es, [[interrupt vector]], and other configuration (e.g. the [[polarity]] of the BUSY [[signal]]) are selected by setting [[Dual Inline Package|DIP]] switches on the card.

==Registers==

{| border=1
! Register !! Abbreviation !! Address
|-
|Word Count Register || DRWC || 772410
|-
|Bus Address Register || DRBA || 772412
|-
|Control and Status Register || DRCSR || 772414
|-
|Error and Information Register || DREIR || 772414
|-
|Data Buffer Register || DRDB || 772416
|}

Writes to the CSR/EIR address are always sent to the CSR. The result of a read depends on the setting of the Register Select bit, which is set by a write to the CSR.

The [[address]]es shown are for the first DR11-W in a system; additional ones are normally set to be at 772430, 772450, 772470, etc.

In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics'', and write-only in '''bold'''.

===772410: Word Count Register (DRWC)===
{{16bit-header}}
| colspan=16 | WC15 <---> WC00
{{16bit-bitout}}

Bit 0 is read-only, and is provided by the connected user device.

===772412: Bus Address Register (DRBA)===
{{16bit-header}}
| colspan=16 | BA15 <---> BA00
{{16bit-bitout}}

Bit 0 is read-only, and is provided by the connected user device.

===772414: Control and Status Register (DRCSR)===
{{16bit-header}}
| ''ERROR''/'''REGSEL''' || NXM || ATTN || MAINT || colspan=3 | ''STAT A-C'' || CYCLE || ''READY'' || IE || colspan=2 | XBA16-17 || colspan=3 | FUNC1-3 || ''REGSEL''/'''GO'''
{{16bit-bitout}}

===772414: Error and Information Register (DREIR)===
{{16bit-header}}
| ''ERROR'' || ''NXM'' || ''ATTN'' || ''MCR'' || ''ACLO'' || ''PAR'' || ''BRTE'' || ''NBS'' || colspan=7 | Unused || ''REGSEL''
{{16bit-bitout}}

===772416: Data Buffer Register (DRDB)===
{{16bit-header}}
| colspan=16 | Data15 <---> Data00
{{16bit-bitout}}

This is actually a pair of registers; a read-only input buffer register, and a write-only output buffer register.

==Implementation==

Connection to the user's device is via a pair of 40-pin [[Berg connector]] headers, into which [[flat cable]]s (such as BC06R's) plug. For [[diagnostic]] purposes, a BC05L cable can be used to loop the device's input and output together.

Both receivers and drivers are [[single-ended signalling|single-ended]], so for best results the DR11-W and the user's device should share a [[ground]].

==External links==

* [http://www.bitsavers.org/pdf/dec/unibus/DR11W_UsersMan.pdf DR11-W Direct Memory Interface Module User's Guide] (EK-DR11W-UG-001)
* [http://www.bitsavers.org/pdf/dec/unibus/EK-DR11W-UG-004.pdf DR11-W Direct Memory Access Interface Module User's Guide] (EK-DR11W-UG-004)
* [http://www.bitsavers.org/pdf/dec/unibus/MP00693_DR11-W_EngrDrws.pdf DR11-W Field Maintenance Print Set] (MP00693)

[[Category: UNIBUS Parallel Interfaces]]

← Older revision		Revision as of 15:48, 2 December 2021
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−	The '''DR11-W Direct Memory Access Interface''' was a [[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access\|DMA]] to transfer data to a user device. It was a single [[DEC card form factor\|hex]] card (the '''~~Mxxxx~~''') replacement for the earlier multi-card [[DR11-B parallel interface]]. The DR11-W is somewhat [[program compatible]] with the DR11-B.	+	[[Image:DR11-W M8716.jpg\|300px\|thumb\|right\|DR11-W card]]
		+
		+	The '''DR11-W Direct Memory Access Interface''' was a [[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access\|DMA]] to transfer data to a user device. It was a single [[DEC card form factor\|hex]] card (the '''M8716''') replacement for the earlier multi-card [[DR11-B parallel interface]]. The DR11-W is somewhat [[program compatible]] with the DR11-B.

	By appropriate manipulation of the control lines (below), the user device can do [[byte]] or [[word]] cycles on the [[bus]], perform read-modify-write bus cycles, or do block 'burst' bus transfers. The DR11-W can also be operated by [[programmed I/O]], potentially via [[interrupt]]s.		By appropriate manipulation of the control lines (below), the user device can do [[byte]] or [[word]] cycles on the [[bus]], perform read-modify-write bus cycles, or do block 'burst' bus transfers. The DR11-W can also be operated by [[programmed I/O]], potentially via [[interrupt]]s.

← Older revision	Revision as of 15:41, 2 December 2021
(No difference)

DR11-W Direct Memory Access Interface - Revision history

Jnc: +img

Jnc: Jnc moved page DR11-W Direct Memory Interface to DR11-W Direct Memory Access Interface: DEC formal name

Jnc: Fairly complete