DRV11-B Direct Memory Access Interface - Revision history

Jnc: proper sub-cat

2020-06-10T01:54:16Z

proper sub-cat

← Older revision		Revision as of 01:54, 10 June 2020
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	The '''DRV11-B Direct Memory Access Interface''' is a parallel ~~port~~ [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access\|DMA]] to transfer data.		The '''DRV11-B Direct Memory Access Interface''' is a [[parallel interface]] [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access\|DMA]] to transfer data.

	It is effectively a [[half-duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.		It is effectively a [[half-duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.
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	{{16bit-bitout}}		{{16bit-bitout}}

	[[Category:QBUS ~~Peripherals~~]]		[[Category: QBUS Parallel Interfaces]]

Jnc: Add reg contents

2020-04-21T03:29:31Z

Add reg contents

← Older revision		Revision as of 03:29, 21 April 2020
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	\|}		\|}

	~~<!--~~ In the register contents (below), bits which are read/write ~~or unused~~ are shown in normal font, those which are read-only are in ''italics''.		In the register contents (below), bits which are read/write are shown in normal font, those which are read-only are in ''italics'', and write-only in '''bold'''.

	===Word Count Register (DRWCR)===		===Word Count Register (DRWCR)===
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	===Status Register (DRCSR)===		===Status Register (DRCSR)===
	{{16bit-header}}		{{16bit-header}}
	\| ''~~REQ B~~'' \|\| colspan=7 \| ~~Unused~~ \|\| ''~~REQ A~~'' \|\| ~~INT ENB A~~ \|\| ~~INT ENB B~~ \|\| colspan=3 \| ~~Unused~~ \|\| ~~CSR1 \|\| CSR0~~		\| ''ERR'' \|\| ''NEX'' \|\| ''ATTN'' \|\| MAINT \|\| colspan=3 \| ''STATUS'' \|\| CYCLE \|\| ''RDY'' \|\| IE \|\| colspan=2 \| XAD \|\| colspan=3 \| FNCT \|\| '''GO'''
	{{16bit-bitout}}		{{16bit-bitout}}

	* ~~REQ B~~ - ~~Request B~~ - ~~Signal~~ from user's hardware which can be tested, or cause an [[interrupt]] (below)		* ERR - Error; set by NEX or ATTN
	* ~~REQ A~~ - ~~Request A~~		* NEX - Nonexistent Memory; also write-to-zero
	* ~~INT ENB A~~ - Interrupt Enable A - When set, allows setting ~~REQ A~~ to cause an interrupt		* ATTN - Attention; signal from user's hardware which can be tested, or cause an [[interrupt]] (below)
	* ~~INT ENB B~~ - ~~Interrupt Enable B~~		* MAINT - Maintenance
	* ~~CSR1~~ - ~~Signal~~ to user's hardware ~~(on connector 1)~~		* STATUS - Signals from user hardware
	* ~~CSR0~~ - ~~Signal~~ to user's hardware ~~(on connector 2)~~		* CYCLE - DMA cycle requested
			* RDY - DRV11-B is able to accept a new command; set by ERR or WCR overflow, cleared by GO
			* IE - Interrupt Enable - When set, allows setting RDY to cause an interrupt
			* XAD - Extended Address; extension of BAR
			* FNCT - Signals to user's hardware
			* GO - Enables DMA, sent to user's hardware

	===Output Buffer Register (DROUTBUF)===		===Output Buffer Register (DROUTBUF)===
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	{{16bit-header}}		{{16bit-header}}
	\| colspan=16 \| ''IN15 <-> IN0''		\| colspan=16 \| ''IN15 <-> IN0''
	{{16bit-bitout}} ~~-->~~		{{16bit-bitout}}

	[[Category:QBUS Peripherals]]		[[Category:QBUS Peripherals]]

Jnc: /* Registers */ Wrong order

2020-04-20T18:49:41Z

Registers: Wrong order

← Older revision		Revision as of 18:49, 20 April 2020
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	! Register !! Abbreviation !! Address		! Register !! Abbreviation !! Address
	\|-		\|-
	\|~~Bus Address~~ Register \|\| ~~DRBAR~~ \|\| 767770		\|Word Count Register \|\| DRWCR \|\| 767770
	\|-		\|-
	\|~~Word Count~~ Register \|\| ~~DRWCR~~ \|\| 767772		\|Bus Address Register \|\| DRBAR \|\| 767772
	\|-		\|-
	\|Control and Status Register \|\| DRCSR \|\| 767774		\|Control and Status Register \|\| DRCSR \|\| 767774
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	<!-- In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics''.		<!-- In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics''.

			===Word Count Register (DRWCR)===
			{{16bit-header}}
			\| colspan=16 \| WC15 <-> WC0
			{{16bit-bitout}}

			===Bus Address Register (DRBAR)===
			{{16bit-header}}
			\| colspan=15 \| BA15 <-> BA1 \|\| 0
			{{16bit-bitout}}

	===Status Register (DRCSR)===		===Status Register (DRCSR)===

Jnc: Avoid redir

2020-04-20T12:28:59Z

Avoid redir

← Older revision		Revision as of 12:28, 20 April 2020
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	The '''DRV11-B Direct Memory Access Interface''' is a parallel port [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access\|DMA]] to transfer data.		The '''DRV11-B Direct Memory Access Interface''' is a parallel port [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access\|DMA]] to transfer data.

	It is effectively a [[half duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.		It is effectively a [[half-duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.

	It was a [[DEC card form factor\|quad]] format card (M7950); connection to the user's device is via a pair of 40-[[pin]] [[Berg connector]]s.		It was a [[DEC card form factor\|quad]] format card (M7950); connection to the user's device is via a pair of 40-[[pin]] [[Berg connector]]s.

Jnc: Basics

2020-04-20T00:40:23Z

Basics

New page

The '''DRV11-B Direct Memory Access Interface''' is a parallel port [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data.

It is effectively a [[half duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.

It was a [[DEC card form factor|quad]] format card (M7950); connection to the user's device is via a pair of 40-[[pin]] [[Berg connector]]s.

==Registers==

The device has five control and [[buffer]] registers, which can be configured to any group of four sequential [[word]] locations in the I/O page; the first DRV11-B is normally configured to addresses 772410-72416. The two buffer registers share an address, responding to read or write cycles as the case might be.

{| border=1
! Register !! Abbreviation !! Address
|-
|Bus Address Register || DRBAR || 767770
|-
|Word Count Register || DRWCR || 767772
|-
|Control and Status Register || DRCSR || 767774
|-
|Input Data Buffer Register || DRINBUF || 767776 (read)
|-
|Output Data Buffer Register || DROUTBUF || 767776 (write)
|}



[[Category:QBUS Peripherals]]