DRV11-B Direct Memory Access Interface - Revision history

Jnc: proper sub-cat

2020-06-10T01:54:16Z

proper sub-cat

Jnc: Add reg contents

2020-04-21T03:29:31Z

Add reg contents

Jnc: /* Registers */ Wrong order

2020-04-20T18:49:41Z

‎Registers: Wrong order

Jnc: Avoid redir

2020-04-20T12:28:59Z

Avoid redir

Jnc: Basics

2020-04-20T00:40:23Z

Basics

New page

The '''DRV11-B Direct Memory Access Interface''' is a parallel port [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data.

It is effectively a [[half duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.

It was a [[DEC card form factor|quad]] format card (M7950); connection to the user's device is via a pair of 40-[[pin]] [[Berg connector]]s.

==Registers==

The device has five control and [[buffer]] registers, which can be configured to any group of four sequential [[word]] locations in the I/O page; the first DRV11-B is normally configured to addresses 772410-72416. The two buffer registers share an address, responding to read or write cycles as the case might be.

{| border=1
! Register !! Abbreviation !! Address
|-
|Bus Address Register || DRBAR || 767770
|-
|Word Count Register || DRWCR || 767772
|-
|Control and Status Register || DRCSR || 767774
|-
|Input Data Buffer Register || DRINBUF || 767776 (read)
|-
|Output Data Buffer Register || DROUTBUF || 767776 (write)
|}



[[Category:QBUS Peripherals]]

@@ Line 1: / Line 1: @@
-The '''DRV11-B Direct Memory Access Interface''' is a parallel port [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data.
+The '''DRV11-B Direct Memory Access Interface''' is a [[parallel interface]] [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data.
 It is effectively a [[half-duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.
@@ Line 62: / Line 62: @@
 {{16bit-bitout}}
-[[Category:QBUS Peripherals]]
+[[Category: QBUS Parallel Interfaces]]

@@ Line 23: / Line 23: @@
 |}
-<!-- In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics''.
+In the register contents (below), bits which are read/write are shown in normal font, those which are read-only are in ''italics'', and write-only in '''bold'''.
 ===Word Count Register (DRWCR)===
@@ Line 37: / Line 37: @@
 ===Status Register (DRCSR)===
 {{16bit-header}}
-| ''REQ B'' || colspan=7 | Unused || ''REQ A'' || INT ENB A || INT ENB B || colspan=3 | Unused || CSR1 || CSR0
+| ''ERR'' || ''NEX'' || ''ATTN'' || MAINT || colspan=3 | ''STATUS'' || CYCLE || ''RDY'' || IE || colspan=2 | XAD || colspan=3 | FNCT || '''GO'''
 {{16bit-bitout}}
-* REQ B - Request B - Signal from user's hardware which can be tested, or cause an [[interrupt]] (below)
+* ERR - Error; set by NEX or ATTN
-* REQ A - Request A
+* NEX - Nonexistent Memory; also write-to-zero
-* INT ENB A - Interrupt Enable A - When set, allows setting REQ A to cause an interrupt
+* ATTN - Attention; signal from user's hardware which can be tested, or cause an [[interrupt]] (below)
-* INT ENB B - Interrupt Enable B
+* MAINT - Maintenance
-* CSR1 - Signal to user's hardware (on connector 1)
+* STATUS - Signals from user hardware
-* CSR0 - Signal to user's hardware (on connector 2)
+* CYCLE - DMA cycle requested
 ===Output Buffer Register (DROUTBUF)===
@@ Line 55: / Line 60: @@
 {{16bit-header}}
 | colspan=16 | ''IN15 <-> IN0''
-{{16bit-bitout}} -->
+{{16bit-bitout}}
 [[Category:QBUS Peripherals]]

@@ Line 12: / Line 12: @@
 ! Register !! Abbreviation !! Address
 |-
-|Bus Address Register || DRBAR || 767770
+|Word Count Register || DRWCR || 767770
 |-
-|Word Count Register || DRWCR || 767772
+|Bus Address Register || DRBAR || 767772
 |-
 |Control and Status Register || DRCSR || 767774
@@ Line 24: / Line 24: @@
 <!-- In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics''.
 ===Status Register (DRCSR)===