DRV11-WA General Purpose DMA Interface - Revision history

Jnc: /* External links */ +Manuals, eng drws - also diag loopback

2021-12-02T17:12:02Z

‎External links: +Manuals, eng drws - also diag loopback

Jnc: proper sub-cat

2020-06-10T02:01:13Z

proper sub-cat

Jnc: +image

2020-05-19T11:31:21Z

+image

Jnc: Basic info

2020-05-18T00:31:12Z

Basic info

New page

The '''DRV11-WA Direct Memory Access Interface''' is a parallel port [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output. It uses [[Direct Memory Access|DMA]] to transfer data; it is a [[QBUS#Variable address size|Q22]] device.

It is effectively a [[half-duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.

It was a [[DEC card form factor|dual]] format card (M7651); connection to the user's device is via a pair of 40-[[pin]] [[Berg connector]]s.

==Registers==

The device has six control and [[buffer]] registers, which can be configured to any group of four sequential [[word]] locations in the I/O page (two pairs of registers share an address); the first DRV11-WA is normally configured to addresses 772410-72416.

{| border=1
! Register !! Abbreviation !! Address
|-
|Word Count Register || DRWCR || 767770
|-
|Bus Address Register || DRBAR || 767772
|-
|Bus Address Extension Register || DRBAE || 767772
|-
|Control and Status Register || DRCSR || 767774
|-
|Input Data Buffer Register || DRINBUF || 767776 (read)
|-
|Output Data Buffer Register || DROUTBUF || 767776 (write)
|}

To gain access to the BAE, reference the BAR; this sets an internal flag which sends the next reference to the BAR's address to the BAE. Referring to any register (e.g. reading the WCR) clears the flag. The two buffer registers share an address, responding to read or write cycles as the case might be.


[[Category:QBUS Peripherals]]

← Older revision		Revision as of 11:31, 19 May 2020
Line 1:		Line 1:
−	~~<!--~~ [[Image:DRV11-WA.jpg\|thumb\|200px\|right\|DRV11-WA board]] ~~-->~~	+	[[Image:DRV11-WA.jpg\|thumb\|200px\|right\|DRV11-WA board]]

	The '''DRV11-WA Direct Memory Access Interface''' is a parallel port [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output. It uses [[Direct Memory Access\|DMA]] to transfer data; it is a [[QBUS#Variable address size\|Q22]] device.		The '''DRV11-WA Direct Memory Access Interface''' is a parallel port [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output. It uses [[Direct Memory Access\|DMA]] to transfer data; it is a [[QBUS#Variable address size\|Q22]] device.

@@ Line 5: / Line 5: @@
 It is effectively a [[half-duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.
-It was a [[DEC card form factor|dual]] format card (M7651); connection to the user's device is via a pair of 40-[[pin]] [[Berg connector]]s.
+It was a [[DEC card form factor|dual]] format card (M7651); connection to the user's device is via a pair of 40-[[pin]] [[Berg connector]]s. For [[diagnostic]] purposes, a BC05L cable can be used to loop the device's input and output together.
 ==Registers==
@@ Line 68: / Line 68: @@
 {{16bit-bitout}}
 -->
 [[Category: QBUS Parallel Interfaces]]

@@ Line 1: / Line 1: @@
 [[Image:DRV11-WA.jpg|thumb|200px|right|DRV11-WA board]]
-The '''DRV11-WA Direct Memory Access Interface''' is a parallel port [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output. It uses [[Direct Memory Access|DMA]] to transfer data; it is a [[QBUS#Variable address size|Q22]] device.
+The '''DRV11-WA Direct Memory Access Interface''' is a [[parallel interface]] [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output. It uses [[Direct Memory Access|DMA]] to transfer data; it is a [[QBUS#Variable address size|Q22]] device.
 It is effectively a [[half-duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.
@@ Line 68: / Line 68: @@
 {{16bit-bitout}}
 -->
-[[Category:QBUS Peripherals]]
+[[Category: QBUS Parallel Interfaces]]