Direct Memory Access - Revision history

Jnc: +See also - Programmed I/O

2021-10-20T21:08:05Z

+See also - Programmed I/O

Jnc: +cat

2018-12-16T00:07:26Z

+cat

Jnc: Correct cat

2018-10-18T15:00:03Z

Correct cat

Jnc: Not so stubby, but it fills a need

2016-11-07T00:43:15Z

Not so stubby, but it fills a need

New page

'''Direct Memory Access''', usually abbreviated as '''DMA''', refers to a now-very-common technique used to transfer data between devices and [[main memory]]. In DMA transfers, data is not moved by the [[CPU]] (e.g. by reading it from the device, and the writing it to the memory); rather, the device transfers the data itself.

There are two main approaches for performing this. In the first, the CPU and devices share a [[bus]] which can perform read or write cycles to memory; the device must gain control of the bus, and then performs a memory cycle. In the second, the memory has multiple ports, and the device has direct access to the memory via one of the ports.

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	There are two main approaches for performing this. In the first, the CPU and devices share a [[bus]] which can perform read or write cycles to memory; the device must gain control of the bus, and then performs a memory cycle. In the second, the memory has multiple ports, and the device has direct access to the memory via one of the ports.		There are two main approaches for performing this. In the first, the CPU and devices share a [[bus]] which can perform read or write cycles to memory; the device must gain control of the bus, and then performs a memory cycle. In the second, the memory has multiple ports, and the device has direct access to the memory via one of the ports.

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