Emitter-coupled logic - Revision history

Jnc: /* External links */ + interesting DEC 'Choice of Logic' memo

2023-05-16T16:04:51Z

‎External links: + interesting DEC 'Choice of Logic' memo

Jnc: +cat

2018-12-14T18:21:29Z

+cat

Jnc: wordsmithing

2018-03-30T21:21:31Z

wordsmithing

Jnc: Typos, etc

2018-03-30T02:37:42Z

Typos, etc

Jnc: A pretty good start

2018-03-30T00:53:51Z

A pretty good start

New page

'''Emitter-coupled logic''' (almost always used as an acronym, '''ECL''') was, for several decades, the fastest logic family, reaching peak speed of less than 1 nsec.

The basic concept in ECL is that in each [[gate]], there are two paths through the gate for a constant [[current]] flow, to two different outputs. As the gate operates, the current is switched between one output and the other; the pair thus form complementary outputs.

The availability of complementary outputs has a number of advantages: individual [[inverter]]s are almost never needed, reducing the total number of gate delays; the outputs can also be fed directly into a [[differential pair]].

Since there is always a constant current flowing, ECL gates do not create spikes on the power supply line when they switch; however, they use a lot of power.

==Internals==

An ECL gate output uses a pair of [[transistor]]s, with both their emitters connected to the low voltage in the system (often ground) - hence the name ECL. The collectors on both, which are the outputs, are connected to the supply (high) voltage through small [[resistor]]s.

The base of one transistor is connected to a reference [[voltage]], roughly half-way between the high and low supply voltages. The base of the other transistor is the input. When it is slightly above the reference voltage, all the current flows through that transistor; when slightly below, all the current flows through the other.

← Older revision		Revision as of 16:04, 16 May 2023
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	The base of one transistor is connected to a reference [[voltage]], roughly half-way between the high and low supply voltages. The base of the other transistor is the input. When it is slightly above the reference voltage, all the current flows through that transistor; when slightly below, all the current flows through the other.		The base of one transistor is connected to a reference [[voltage]], roughly half-way between the high and low supply voltages. The base of the other transistor is the input. When it is slightly above the reference voltage, all the current flows through that transistor; when slightly below, all the current flows through the other.
		+
		+	==External links==
		+
		+	* [http://www.bitsavers.org/pdf/dec/pdp11/memos/700929_Choice_Of_Logic.pdf Choice of Logic] - interesting DEC memo comparing ECL and [[Schottky TTL]]

	[[Category: Technology‎]]		[[Category: Technology‎]]

← Older revision		Revision as of 18:21, 14 December 2018
Line 12:		Line 12:

	The base of one transistor is connected to a reference [[voltage]], roughly half-way between the high and low supply voltages. The base of the other transistor is the input. When it is slightly above the reference voltage, all the current flows through that transistor; when slightly below, all the current flows through the other.		The base of one transistor is connected to a reference [[voltage]], roughly half-way between the high and low supply voltages. The base of the other transistor is the input. When it is slightly above the reference voltage, all the current flows through that transistor; when slightly below, all the current flows through the other.
		+
		+	[[Category: Technology‎]]

@@ Line 1: / Line 1: @@
 '''Emitter-coupled logic''' (almost always used as an acronym, '''ECL''') was, for several decades, the fastest logic family, reaching peak speeds of less than 1 nsec delay.
-The basic concept in ECL is that in each [[gate]]'s output stage, there are two paths through it with a constant [[current]], to two different outputs. As the gate operates, the current is switched between one output and the other; the pair thus form complementary outputs.
+The basic concept in ECL is that in each [[gate]]'s output stage, there are two paths, to two different outputs, with a constant [[current]] always flowing through one of the two. As the gate operates, the current is switched between one output and the other; the pair thus form complementary outputs.
 The availability of complementary outputs has a number of advantages: individual [[inverter]]s are almost never needed, reducing the total number of gate delays; the outputs can also be fed directly into a [[differential pair]].

@@ Line 1: / Line 1: @@
-'''Emitter-coupled logic''' (almost always used as an acronym, '''ECL''') was, for several decades, the fastest logic family, reaching peak speed of less than 1 nsec.
+'''Emitter-coupled logic''' (almost always used as an acronym, '''ECL''') was, for several decades, the fastest logic family, reaching peak speeds of less than 1 nsec delay.
-The basic concept in ECL is that in each [[gate]], there are two paths through the gate for a constant [[current]] flow, to two different outputs. As the gate operates, the current is switched between one output and the other; the pair thus form complementary outputs.
+The basic concept in ECL is that in each [[gate]]'s output stage, there are two paths through it with a constant [[current]], to two different outputs. As the gate operates, the current is switched between one output and the other; the pair thus form complementary outputs.
 The availability of complementary outputs has a number of advantages: individual [[inverter]]s are almost never needed, reducing the total number of gate delays; the outputs can also be fed directly into a [[differential pair]].
-Since there is always a constant current flowing, ECL gates do not create spikes on the power supply line when they switch; however, they use a lot of power.
+Since there is always a constant current flowing, ECL gates do not create spikes on the power supply line when they switch; however, they use a lot of power (constantly).
 ==Internals==