F-11 chip set - Revision history

Jnc: /* See also */ +

2022-03-28T21:50:31Z

‎See also: +

Jnc: /* Chip versions */ Avoid redir

2021-03-12T15:43:03Z

‎Chip versions: Avoid redir

Jnc: KEF11-B details

2021-02-02T20:29:06Z

KEF11-B details

Jnc: +links

2021-01-01T02:11:26Z

+links

Jnc: /* ODT limitations */ link ODT

2019-10-04T20:30:22Z

‎ODT limitations: link ODT

Jnc: Typo

2018-11-01T19:43:53Z

Typo

Jnc: Correct supposition on float registers in MMU chip

2018-11-01T15:04:02Z

Correct supposition on float registers in MMU chip

Jnc: +picture, links

2018-10-27T12:41:28Z

+picture, links

Jnc: Proper cat

2018-02-17T20:39:22Z

Proper cat

Jnc: Not a stub any more

2018-02-17T13:44:26Z

Not a stub any more

← Older revision		Revision as of 21:50, 28 March 2022
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	The later [[KDJ11 CPUs]] do not have this limitation.		The later [[KDJ11 CPUs]] do not have this limitation.
		+
		+	==See also==
		+
		+	* [[J-11 chip set]]

	==External links==		==External links==

@@ Line 11: / Line 11: @@
 ==Chip versions==
-The data paths chip is the DC302, [[DEC part numbers‎‎|DEC part #]] 21-15541-Ax, where x is a capital letter giving the revision (B is the most common, although C has been seen), which contains the registers, [[Arithmetic logic unit|ALU]], etc. The control chip is the DC303, DEC part # 23-001C7-Ax (only the A revision has been seen), which contains microcode and a small amount of miscellaneous logic. The carrier as a whole has the DEC part # 57-00000-01-A1 or 57-00000-02 (the latter with the -AC revision of the data paths chip).
+The data paths chip is the DC302, [[DEC part number]] 21-15541-Ax, where x is a capital letter giving the revision (B is the most common, although C has been seen), which contains the registers, [[Arithmetic logic unit|ALU]], etc. The control chip is the DC303, DEC part # 23-001C7-Ax (only the A revision has been seen), which contains microcode and a small amount of miscellaneous logic. The carrier as a whole has the DEC part # 57-00000-01-A1 or 57-00000-02 (the latter with the -AC revision of the data paths chip).
 ==ODT limitations==

@@ Line 7: / Line 7: @@
 (The KEF11-A requires the KTF11-A, since the floating point [[register]]s are actually in the KTF11-A. The reason why is not known; although the KEF11-A is [[microcode]], there are enough pins for both the data [[bus]], and the microcode bus.)
-There is also a 6-chip carrier, the [[KEF11-B CIS chip]], which implements the [[PDP-11 Commercial Instruction Set]] (CIS).
+There is also a double-width 6-chip carrier, the [[KEF11-B CIS chip]], which implements the [[PDP-11 Commercial Instruction Set]] (CIS); not all KDF11 CPUs can hold this, though.
 ==Chip versions==

@@ Line 1: / Line 1: @@
 [[Image:m8186.jpg|250px|thumb|right|F-11 chip set on a [[KDF11-A CPU|KDF11-A]]]]
-The '''F-11 chip set''' (code-named 'Fonz') was [[DEC]]'s second [[microprocessor]] implementation of the [[PDP-11 architecture]]. It was used in the [[KDF11 CPUs]]. The main [[Central Processing Unit|CPU]] was implemented in two [[integrated circuit|chips]] (carried on a single DIP carrier).
+The '''F-11 chip set''' (code-named 'Fonz') was [[DEC]]'s second [[microprocessor]] implementation of the [[PDP-11 architecture]]. It was used in the [[KDF11 CPUs]]. The main [[Central Processing Unit|CPU]] was implemented in two [[integrated circuit|chips]] (carried on a single [[Dual Inline Package|DIP]] carrier).
-Unlike the first microprocessor implementation (the [[LSI-11]]), the F-11 chip set implemented the full PDP-11 architecture, including the optional [[KTF11-A memory management chip]] which implemented standard [[PDP-11 Memory Management]], and the optional [[KEF11-A floating point chip]] which implemented the [[FP11 floating point|FP11]]-compatible [[floating point]].
+Unlike the first microprocessor implementation (the [[LSI-11]]), the full F-11 chip set implemented the full PDP-11 architecture, including the optional [[KTF11-A memory management chip]] which implemented standard [[PDP-11 Memory Management]], and the optional [[KEF11-A floating point chip]] which implemented the [[FP11 floating point|FP11]]-compatible [[floating point]].
 (The KEF11-A requires the KTF11-A, since the floating point [[register]]s are actually in the KTF11-A. The reason why is not known; although the KEF11-A is [[microcode]], there are enough pins for both the data [[bus]], and the microcode bus.)
@@ Line 11: / Line 11: @@
 ==Chip versions==
-The data paths chip is the DC302, DEC part # 21-15541-Ax, where x is a capital letter giving the revision (B is the most common, although C has been seen), which contains the registers, [[Arithmetic logic unit|ALU]], etc. The control chip is the DC303, DEC part # 23-001C7-Ax (only the A revision has been seen), which contains microcode and a small amount of miscellaneous logic. The carrier as a whole has the DEC part # 57-00000-01-A1 or 57-00000-02 (the latter with the -AC revision of the data paths chip).
+The data paths chip is the DC302, [[DEC part numbers‎‎|DEC part #]] 21-15541-Ax, where x is a capital letter giving the revision (B is the most common, although C has been seen), which contains the registers, [[Arithmetic logic unit|ALU]], etc. The control chip is the DC303, DEC part # 23-001C7-Ax (only the A revision has been seen), which contains microcode and a small amount of miscellaneous logic. The carrier as a whole has the DEC part # 57-00000-01-A1 or 57-00000-02 (the latter with the -AC revision of the data paths chip).
 ==ODT limitations==

@@ Line 15: / Line 15: @@
 ==ODT limitations==
-The F-11 chip set includes microcode which provides 'front panel' functionality named 'ODT'; the ability to read and write to [[main memory]], start the processor, etc. However, the original version of the KDF11-A only supported 18-bit [[address]]ing, and even though later versions supported 22-bit addressing, ODT in the KDF11's was always limited to 18-bit addressing: i.e. it is impossible to interact with memory above 256 Kbytes from ODT.
+The F-11 chip set includes microcode which provides 'front panel' functionality named '[[QBUS CPU ODT|ODT]]'; the ability to read and write to [[main memory]], start the processor, etc. However, the original version of the KDF11-A only supported 18-bit [[address]]ing, and even though later versions supported 22-bit addressing, ODT in the KDF11's was always limited to 18-bit addressing: i.e. it is impossible to interact with memory above 256 Kbytes from ODT.
 The later [[KDJ11 CPUs]] do not have this limitation.

@@ Line 5: / Line 5: @@
 Unlike the first microprocessor implementation (the [[LSI-11]]), the F-11 chip set implemented the full PDP-11 architecture, including the optional [[KTF11-A memory management chip]] which implemented standard [[PDP-11 Memory Management]], and the optional [[KEF11-A floating point chip]] which implemented the [[FP11 floating point|FP11]]-compatible [[floating point]].
-(The KEF11-A requires the KTF11-A, since the floating point [[register]]s are actually in the KTF11-A; probably because the KEF11-A is [[microcode]], and there aren't enough pins for both the data [[bus]], and the microcode bus.)
+(The KEF11-A requires the KTF11-A, since the floating point [[register]]s are actually in the KTF11-A. The reason why is known; although the KEF11-A is [[microcode]], there are enough pins for both the data [[bus]], and the microcode bus.)
-There is also a 6-chip carrier, the [[KEF11-B]], which implements the [[PDP-11 Commercial Instruction Set]] (CIS).
+There is also a 6-chip carrier, the [[KEF11-B CIS chip]], which implements the [[PDP-11 Commercial Instruction Set]] (CIS).
 ==Chip versions==

← Older revision		Revision as of 20:39, 17 February 2018
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	{{PDP-11}}		{{PDP-11}}

−	[[Category:PDP-~~11s]]~~	+	[[Category:PDP-11 Processors]]
−	~~[[Category:DEC~~ Processors]]

← Older revision		Revision as of 13:44, 17 February 2018
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	* [http://simh.trailing-edge.com/semi/f11.html F-11 (1979)]		* [http://simh.trailing-edge.com/semi/f11.html F-11 (1979)]
−
−	~~{{stub}}~~

	{{PDP-11}}		{{PDP-11}}