FIS floating point - Revision history

Jnc: /* Architecture */ Typo; +links

2024-12-17T10:11:28Z

‎Architecture: Typo; +links

Jnc: Replace duplicate term

2024-12-16T17:38:47Z

Replace duplicate term

Jnc: /* External links */ +Use of FIS in 'Computer Engineering'

2021-12-07T15:49:59Z

‎External links: +Use of FIS in 'Computer Engineering'

Jnc: +cat

2018-12-16T04:01:36Z

+cat

Jnc: Mention use in FORTRAN

2018-05-08T12:56:09Z

Mention use in FORTRAN

Jnc: A decent start

2016-12-25T16:21:47Z

A decent start

New page

'''FIS (Floating Instruction Set) floating point''' is the term used for the floating point instructions supported by a few [[PDP-11]]s which had hardware support for floating point. (Most supported a more capable floating point capability, the [[FP11 floating point]].) It was tightly integrated with the CPU, so that the CPU processed a mix of 'regular' and floating point instructions.

==Architecture==

FIS-type floating point supported only short (32 bit) floating point numbers; it used an 8 bit exponent (in 'excess 0200' notation, giving an exponent range of +127. to -128.), a sign bit, and the remaining 23 bits were the fractional part.

It provided only the four basic arithmetic operations. Checking for underflow. overflow, and division by zero was performed in hardware, and would cause an trap if they happened; condition code bits in the main CPU recorded the outcome of operations.

The instructions used one of the [[PDP-11 architecture|regular PDP-11 registers]] as a pointer to load and store floating point data from/to memory; floating point values could only be stored in [[main memory]], generally on the stack; there was no way to store floating point values in the [[CPU]].

==Implementations==

The initial implementation was the optional [[KE11-F Floating Instruction Set]] for the [[KD11-A CPU]] for the [[PDP-11/40]]; it was later used in the optional [[KEV11-A floating point]] option for the [[LSI-11]] [[CPU]] of the [[PDP-11/03]].

@@ Line 9: / Line 9: @@
 FIS-type floating point supported only short (32 bit) floating point numbers; it used an 8 bit exponent (in 'excess 0200' notation, giving an exponent range of +127. to -128.), a sign bit, and the remaining 23 bits were the fractional part.
-It provided only the four basic arithmetic operations. Checking for underflow. overflow, and division by zero was performed in hardware, and would cause an trap if they happened; condition code bits in the main CPU recorded the outcome of operations.
+It provided only the four basic arithmetic operations. Checking for underflow. overflow, and division by zero was performed in hardware, and would cause a [[trap]] if they happened; [[condition codes|condition code bits]] in the main CPU recorded the outcome of operations.
-The instructions used one of the [[PDP-11 architecture|regular PDP-11 registers]] as a pointer to load and store floating point data from/to memory; floating point values could only be stored in [[main memory]], generally on the [[stack]]; there was no way to store floating point values in the CPU.
+The instructions used one of the [[PDP-11 architecture|regular PDP-11 registers]] as a [[pointer]] to load and store floating point data from/to [[main memory]]. Floating point values could only be stored in memory, generally on the [[stack]]; there was no way to store floating point values in the CPU.
 ==Implementations==

@@ Line 1: / Line 1: @@
 '''FIS (Floating Instruction Set) floating point''' is the term used for the optional [[floating point]] [[instruction]]s supported by a few of the [[PDP-11]]s which had [[hardware]] support for floating point.
-Most supported a more capable floating point capability, the [[FP11 floating point]]. Even though the instructions were not compatible between the two, the FIS was useful since [[Digital Equipment Corporation|DEC]]'s [[FORTRAN]] [[compiler]] (the main 'target' for the FIS) for the PDP-11 used [[threaded code]], and was thus able, via [[conditional assembly]] of the [[run-time support]], to easily make use of the low-capability, but low-cost, FIS version.
+Most supported a more powerful floating point capability, the [[FP11 floating point]]. Even though the instructions were not compatible between the two, the FIS was useful since [[Digital Equipment Corporation|DEC]]'s [[FORTRAN]] [[compiler]] (the main 'target' for the FIS) for the PDP-11 used [[threaded code]], and was thus able, via [[conditional assembly]] of the [[run-time support]], to easily make use of the low-capability, but low-cost, FIS version.
 As with the FP11 version, it was tightly integrated with the [[Central Processing Unit|CPU]], so that the CPU processed a mix of 'regular' and floating point instructions.

← Older revision		Revision as of 15:49, 7 December 2021
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	The initial implementation was the optional [[KE11-F Floating Instruction Set]] for the [[KD11-A CPU]] for the [[PDP-11/40]]; it was later used in the optional [[KEV11-A floating point]] option for the [[LSI-11]] [[CPU]] of the [[PDP-11/03]].		The initial implementation was the optional [[KE11-F Floating Instruction Set]] for the [[KD11-A CPU]] for the [[PDP-11/40]]; it was later used in the optional [[KEV11-A floating point]] option for the [[LSI-11]] [[CPU]] of the [[PDP-11/03]].
		+
		+	==External links==
		+
		+	* Ronald F. Brender, [http://gordonbell.azurewebsites.net/Computer_Engineering/00000387.htm Turning Cousins into Sisters: An Example of Software Smoothing of Hardware Differences], in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design'', Digital Press, Bedford, 1978 - Explains how DEC software made use of the FIS instructions

	[[Category: PDP-11s]]		[[Category: PDP-11s]]

← Older revision		Revision as of 04:01, 16 December 2018
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	The initial implementation was the optional [[KE11-F Floating Instruction Set]] for the [[KD11-A CPU]] for the [[PDP-11/40]]; it was later used in the optional [[KEV11-A floating point]] option for the [[LSI-11]] [[CPU]] of the [[PDP-11/03]].		The initial implementation was the optional [[KE11-F Floating Instruction Set]] for the [[KD11-A CPU]] for the [[PDP-11/40]]; it was later used in the optional [[KEV11-A floating point]] option for the [[LSI-11]] [[CPU]] of the [[PDP-11/03]].
		+
		+	[[Category: PDP-11s]]