FP11-F Floating-Point Processor - Revision history

Jnc: Better cat

2022-10-13T00:20:10Z

Better cat

Jnc: /* External links */ +FMPS, manual

2022-01-16T01:01:42Z

‎External links: +FMPS, manual

Jnc: +cat

2018-12-16T03:59:05Z

+cat

Jnc: A decent start

2018-05-11T12:35:09Z

A decent start

New page

The '''FP11-F Floating-Point Processor''' is the [[hardware]] [[floating point]] option for the [[KD11-Z CPU]] of the [[PDP-11/44]]. It implements the full [[FP11 floating point]]; it consists of a single [[DEC card form factor|hex]] card (the M7093), which plugs into a dedicated slot in the [[Central Processing Unit|CPU]]'s [[backplane]].

The CPU and the FPP interact over two [[tri-state]] [[data path]]s, one for data, and another for the [[microcode]] [[Program Counter|PC]]. The CPU and FPP each have their own microcode [[Read-only memory#PROM|PROMs]]; 48 [[bit]]s wide in the FPP, and 56 bits wide in the CPU, for a total of 104 bits.

{{PDP-11}}

← Older revision		Revision as of 00:20, 13 October 2022
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	* [http://bitsavers.org/pdf/dec/pdp11/1144/MP00810_FP11F_Jun79.pdf FP11-F Field Maintenance Print Set] (MP00810)		* [http://bitsavers.org/pdf/dec/pdp11/1144/MP00810_FP11F_Jun79.pdf FP11-F Field Maintenance Print Set] (MP00810)

−	[[Category: PDP-11 Processors]]	+	[[Category: PDP-11 UNIBUS Processors]]

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-The '''FP11-F Floating-Point Processor''' is the [[hardware]] [[floating point]] option for the [[KD11-Z CPU]] of the [[PDP-11/44]]. It implements the full [[FP11 floating point]]; it consists of a single [[DEC card form factor|hex]] card (the M7093), which plugs into a dedicated slot in the [[Central Processing Unit|CPU]]'s [[backplane]].
+The '''FP11-F Floating-Point Processor''' is the [[hardware]] [[floating point]] option for the [[KD11-Z CPU]] of the [[PDP-11/44]]. It implements the full [[FP11 floating point]]; it consists of a single [[DEC card form factor|hex]] card (the '''M7093'''), which plugs into a dedicated slot in the [[Central Processing Unit|CPU]]'s [[backplane]].
 The CPU and the FPP interact over two [[tri-state]] [[data path]]s, one for data, and another for the [[microcode]] [[Program Counter|PC]]. The CPU and FPP each have their own microcode [[Read-only memory#PROM|PROMs]]; 48 [[bit]]s wide in the FPP, and 56 bits wide in the CPU, for a total of 104 bits.
-{{PDP-11}}
+==External links==
 [[Category: PDP-11 Processors]]

← Older revision		Revision as of 03:59, 16 December 2018
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	{{PDP-11}}		{{PDP-11}}
		+
		+	[[Category: PDP-11 Processors]]