Flip-flop - Revision history

Jnc: Also called 'toggles' in some very early work

2024-04-08T19:09:43Z

Also called 'toggles' in some very early work

← Older revision		Revision as of 19:09, 8 April 2024
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	A '''flip-flop''' or '''latch''' (historically, the terms were somewhat interchangeable, but in contemporary usage they usually refer to disjoint sets of devices) is an extremely common element in digital logic; it is a store for one bit of state.		A '''flip-flop''' or '''latch''' (historically, the terms were somewhat interchangeable, but in contemporary usage they usually refer to disjoint sets of devices; they were called '''toggles''' in some very early work, such as the [[IAS computer]]) is an extremely common element in digital [[logic]]; it is a store for one bit of state.

	Unlike [[gate]]s, which are necessarily made out of [[transistor]]s, all forms of flip-flop and latch (there are quite a few) can be made out of gates. All involve feedback, from the outputs, to some of the inputs of the gates used to create them; they are thus subject to [[meta-stability]] issues.		Unlike [[gate]]s, which are necessarily made out of [[transistor]]s, all forms of flip-flop and latch (there are quite a few) can be made out of gates. All involve feedback, from the outputs, to some of the inputs of the gates used to create them; they are thus subject to [[meta-stability]] issues.
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	==Types==		==Types==

	Names exist for several of the most common forms of flip-flop; these are mostly due to Montgomery Phister, from his book "Logical Design of Digital Computers" (John Wiley & Sons, New York, 1958).		Names exist for several of the most common forms of flip-flop; these are mostly due to Montgomery Phister, from his book ''Logical Design of Digital Computers'' (John Wiley & Sons, New York, 1958).

	===S-R latch===		===S-R latch===

	The simplest is the S-R latch (called a 'S-R flip-flop' in the early period), which has only two control inputs, 'set' and 'reset' (as implied by the name). One should assert ''either'' the set or reset inputs; asserting both can drive it into a ~~metastable~~ state (depending on the exact timing of the de-assertion).		The simplest is the S-R latch (called a 'S-R flip-flop' in the early period), which has only two control inputs, 'set' and 'reset' (as implied by the name). One should assert ''either'' the set or reset inputs; asserting both can drive it into a meta-stable state (depending on the exact timing of the de-assertion).

	It usually consists of just two NAND or NOR gates. The output of each gate, in addition to being an output from the latch, is also connected to one of the inputs of the other gate.		It usually consists of just two NAND or NOR gates. The output of each gate, in addition to being an output from the latch, is also connected to one of the inputs of the other gate.
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	==Further reading==		==Further reading==

	* William Henry Eccles, Frank Wilfred Jordan, [https://www.docjava.com/cpe210/radioReview.pdf A Trigger Relay Utilizing Three-Electrode Thermionic Vacuum Tubes], The Radio Review, Vol. 1, No. 3, December 1919, pp. 143-146		* William Henry Eccles, Frank Wilfred Jordan, [https://www.docjava.com/cpe210/radioReview.pdf ''A Trigger Relay Utilizing Three-Electrode Thermionic Vacuum Tubes''], The Radio Review, Vol. 1, No. 3, December 1919, pp. 143-146

	==External links==		==External links==

Jnc: /* Further reading */ +Eccles-Jordan paper

2024-03-01T02:17:10Z

Jnc: typo

2021-03-08T19:16:59Z

typo

← Older revision		Revision as of 19:16, 8 March 2021
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	A '''flip-flop''' or '''latch''' (historically, the terms were somewhat ~~interchangeably~~, but in contemporary usage they usually refer to disjoint sets of devices) is an extremely common element in digital logic; it is a store for one bit of state.		A '''flip-flop''' or '''latch''' (historically, the terms were somewhat interchangeable, but in contemporary usage they usually refer to disjoint sets of devices) is an extremely common element in digital logic; it is a store for one bit of state.

	Unlike [[gate]]s, which are necessarily made out of [[transistor]]s, all forms of flip-flop and latch (there are quite a few) can be made out of gates. All involve feedback, from the outputs, to some of the inputs of the gates used to create them; they are thus subject to [[meta-stability]] issues.		Unlike [[gate]]s, which are necessarily made out of [[transistor]]s, all forms of flip-flop and latch (there are quite a few) can be made out of gates. All involve feedback, from the outputs, to some of the inputs of the gates used to create them; they are thus subject to [[meta-stability]] issues.

Jnc: +cat

2018-12-16T04:09:54Z

+cat

← Older revision		Revision as of 04:09, 16 December 2018
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	* [http://www.electronicsteacher.com/computer-architectures/digital-circuits/flip-flops.php Computer Architectures - Digital Circuits - Latches and flip-flops]		* [http://www.electronicsteacher.com/computer-architectures/digital-circuits/flip-flops.php Computer Architectures - Digital Circuits - Latches and flip-flops]

			[[Category: Hardware Basics]]

Jnc: +link

2018-07-17T01:22:48Z

+link

← Older revision		Revision as of 01:22, 17 July 2018
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	Unlike [[gate]]s, which are necessarily made out of [[transistor]]s, all forms of flip-flop and latch (there are quite a few) can be made out of gates. All involve feedback, from the outputs, to some of the inputs of the gates used to create them; they are thus subject to [[meta-stability]] issues.		Unlike [[gate]]s, which are necessarily made out of [[transistor]]s, all forms of flip-flop and latch (there are quite a few) can be made out of gates. All involve feedback, from the outputs, to some of the inputs of the gates used to create them; they are thus subject to [[meta-stability]] issues.

	There are many different versions, but they usually have one data or two control inputs, two data outputs (the data and its inversion, usually denoted 'Q' and 'Q-bar'), and optionally a clock input, which tells it when to store the current state of the input(s). More complex versions of most devices also have 'preset' and/or 'clear' inputs, which force the output to 1 or 0.		There are many different versions, but they usually have one data or two control inputs, two data outputs (the data and its inversion, usually denoted 'Q' and 'Q-bar'), and optionally a [[clock]] input, which tells it when to store the current state of the input(s). More complex versions of most devices also have 'preset' and/or 'clear' inputs, which force the output to 1 or 0.

	==Attributes==		==Attributes==

Jnc: /* Attributes */ punc to clarify

2018-06-11T21:04:13Z

Attributes: punc to clarify

← Older revision		Revision as of 21:04, 11 June 2018
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	Within each of the basic types (below), there are many subtle variants, based around three main characteristics:		Within each of the basic types (below), there are many subtle variants, based around three main characteristics:

	* ''When'' does the device listen to its input - at a clock edge (and if so, which one), or during a longer period?		* ''When'' does the device listen to its input - at a clock edge (and if so, which one); or during a longer period?
	* For devices which listen during an extended period, ''how'' does it do so - does it track changes in the input, or will it catch, and retain, short spikes?		* For devices which listen during an extended period, ''how'' does it do so - does it track changes in the input; or will it catch, and retain, short spikes?
	* When does the ''output'' change - at a clock edge, when the input changes (after a [[propagation delay]], of course), etc.		* When does the ''output'' change - at a clock edge; when the input changes (after a [[propagation delay]], of course); etc.

	Of the many different varieties, the chief grouping is 'edge-triggered', which only sample the input once, at either the rising or falling edge of the clock. In modern terminology, the term 'flip-flop' is usually reserved for this group; 'latch' is used for everything else. Edge-triggered devices are preferred in [[clocked logic]] systems.		Of the many different varieties, the chief grouping is 'edge-triggered', which only sample the input once, at either the rising or falling edge of the clock. In modern terminology, the term 'flip-flop' is usually reserved for this group; 'latch' is used for everything else. Edge-triggered devices are preferred in [[clocked logic]] systems.

Jnc: /* Latch */ clarify

2018-03-15T08:57:16Z

Latch: clarify

← Older revision		Revision as of 08:57, 15 March 2018
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	===Latch===		===Latch===

	A latch has a single data input, and a clock input. As long as the clock is asserted, the input data is passed through to the output(s); i.e. it is what is called a 'transparent' device, so that the output can move up and down during the period when the clock input is asserted. When the clock stops being asserted, it continues to output the data that was present at ~~that time~~, and the input is thereafter ignored.		A latch has a single data input, and a clock input. As long as the clock is asserted, the input data is passed through to the output(s); i.e. it is what is called a 'transparent' device, so that the output can move up and down during the period when the clock input is asserted.

			When the clock stops being asserted, it continues to output the data that was present at the falling edge of the clock, and the input is thereafter ignored.

	===D flip-flop===		===D flip-flop===

Jnc: Start to try and list the actual attributes in an organized way

2018-03-15T08:42:22Z

Start to try and list the actual attributes in an organized way

← Older revision		Revision as of 08:42, 15 March 2018
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	Unlike [[gate]]s, which are necessarily made out of [[transistor]]s, all forms of flip-flop and latch (there are quite a few) can be made out of gates. All involve feedback, from the outputs, to some of the inputs of the gates used to create them; they are thus subject to [[meta-stability]] issues.		Unlike [[gate]]s, which are necessarily made out of [[transistor]]s, all forms of flip-flop and latch (there are quite a few) can be made out of gates. All involve feedback, from the outputs, to some of the inputs of the gates used to create them; they are thus subject to [[meta-stability]] issues.

	~~They~~ usually have one data or two control inputs, two data outputs (the data and its inversion, usually denoted 'Q' and 'Q-bar'), and optionally a clock input, which tells it when to store the current state of the input(s).		There are many different versions, but they usually have one data or two control inputs, two data outputs (the data and its inversion, usually denoted 'Q' and 'Q-bar'), and optionally a clock input, which tells it when to store the current state of the input(s). More complex versions of most devices also have 'preset' and/or 'clear' inputs, which force the output to 1 or 0.

	Of the many different varieties, the chief grouping is 'edge-triggered', which only change the output once, at either the rising or falling edge of the clock. Of the rest, some are 'transparent', which pass the input data through whenever the clock input is asserted, so that the output can move up and down during that period.		==Attributes==

	In modern terminology, the term 'flip-flop' is usually reserved for ~~the first~~ group; 'latch' is used for everything else.		Within each of the basic types (below), there are many subtle variants, based around three main characteristics:

			* ''When'' does the device listen to its input - at a clock edge (and if so, which one), or during a longer period?
			* For devices which listen during an extended period, ''how'' does it do so - does it track changes in the input, or will it catch, and retain, short spikes?
			* When does the ''output'' change - at a clock edge, when the input changes (after a [[propagation delay]], of course), etc.

			Of the many different varieties, the chief grouping is 'edge-triggered', which only sample the input once, at either the rising or falling edge of the clock. In modern terminology, the term 'flip-flop' is usually reserved for this group; 'latch' is used for everything else. Edge-triggered devices are preferred in [[clocked logic]] systems.

	==Types==		==Types==
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	===S-R latch===		===S-R latch===

	The simplest is the S-R latch (called a 'S-R flip-flop' in the early period), which consists of just two NAND or NOR gates. The output of each gate, in addition to being an output from the latch, is also connected to one of the inputs of the other gate.		The simplest is the S-R latch (called a 'S-R flip-flop' in the early period), which has only two control inputs, 'set' and 'reset' (as implied by the name). One should assert ''either'' the set or reset inputs; asserting both can drive it into a metastable state (depending on the exact timing of the de-assertion).

			It usually consists of just two NAND or NOR gates. The output of each gate, in addition to being an output from the latch, is also connected to one of the inputs of the other gate.

	When constructed with NOR gates, the other two inputs (asserted high) are 'reset' (on the gate with the Q output), and 'set' (on the other). With NAND gates, the two inputs are asserted low, and the 'set' is on the gate providing the Q output.		When constructed with NOR gates, the other two inputs (asserted high) are 'reset' (on the gate with the Q output), and 'set' (on the other). With NAND gates, the two inputs are asserted low, and the 'set' is on the gate providing the Q output.
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	===Latch===		===Latch===

	A latch has a single data input, and a clock input. As long as the clock is asserted, the input data is passed through to the output(s). When the clock stops being asserted, it continues to output the data that was present at that time, and the input is thereafter ignored.		A latch has a single data input, and a clock input. As long as the clock is asserted, the input data is passed through to the output(s); i.e. it is what is called a 'transparent' device, so that the output can move up and down during the period when the clock input is asserted. When the clock stops being asserted, it continues to output the data that was present at that time, and the input is thereafter ignored.

	===D flip-flop===		===D flip-flop===

	A D flop-flop has a single data input, and a clock input. It samples the input on either the rising or falling edge of the clock (depending on the variety)~~. Most D flip-flops also have 'preset' and 'clear' inputs, which force the output to 1 or 0~~.		A D flop-flop has a single data input, and a clock input. It samples the input on either the rising or falling edge of the clock depending on the variety).

	It is constructed out of pair of S-R latches, one after the other, along with some additional gates.		It is usually constructed out of pair of S-R latches, one after the other, along with some additional gates.

	===J-K flip flop===		===J-K flip flop===

	A J-K flop-flop has two data/control inputs, and a clock input. ~~It too samples~~ the inputs ~~on either the rising or falling edge of the clock~~; ~~again~~, ~~most also have preset and clear inputs~~.		A J-K flop-flop has two data/control inputs, and a clock input. When the clock is asserted, with both data/control inputs low, it holds its previous state; with only J high, it sets; with only K high, it clears; with both high, it inverts its previous state.

	~~When~~ the clock ~~happens~~, ~~with both data/control~~ inputs ~~low, it holds its previous state; with only J high, it sets; with only K high, it clears; with both high, it inverts its previous state~~.		Several varieties exist: the earliest versions in [[74 series]] [[transistor-transistor logic\|TTL]] [[integrated circuit\|SSI]] listened to their inputs during the period in which the clock was asserted. Later ones, 'rising-edge triggered' and 'falling-edge triggered', sample their inputs on either the rising or falling edge of the clock.

	==External links==		==External links==

	* [http://www.electronicsteacher.com/computer-architectures/digital-circuits/flip-flops.php Computer Architectures - Digital Circuits - Latches and flip-flops]		* [http://www.electronicsteacher.com/computer-architectures/digital-circuits/flip-flops.php Computer Architectures - Digital Circuits - Latches and flip-flops]

Jnc: Add Phister ref

2018-03-14T17:14:44Z

Add Phister ref

← Older revision		Revision as of 17:14, 14 March 2018
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	In modern terminology, the term 'flip-flop' is usually reserved for the first group; 'latch' is used for everything else.		In modern terminology, the term 'flip-flop' is usually reserved for the first group; 'latch' is used for everything else.

	==S-R latch==		==Types==

			Names exist for several of the most common forms of flip-flop; these are mostly due to Montgomery Phister, from his book "Logical Design of Digital Computers" (John Wiley & Sons, New York, 1958).

			===S-R latch===

	The simplest is the S-R latch (called a 'S-R flip-flop' in the early period), which consists of just two NAND or NOR gates. The output of each gate, in addition to being an output from the latch, is also connected to one of the inputs of the other gate.		The simplest is the S-R latch (called a 'S-R flip-flop' in the early period), which consists of just two NAND or NOR gates. The output of each gate, in addition to being an output from the latch, is also connected to one of the inputs of the other gate.
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	The more complicated flip-flops are often made up of several S-R latches, along with other gates.		The more complicated flip-flops are often made up of several S-R latches, along with other gates.

	==Latch==		===Latch===

	A latch has a single data input, and a clock input. As long as the clock is asserted, the input data is passed through to the output(s). When the clock stops being asserted, it continues to output the data that was present at that time, and the input is thereafter ignored.		A latch has a single data input, and a clock input. As long as the clock is asserted, the input data is passed through to the output(s). When the clock stops being asserted, it continues to output the data that was present at that time, and the input is thereafter ignored.

	==D flip-flop==		===D flip-flop===

	A D flop-flop has a single data input, and a clock input. It samples the input on either the rising or falling edge of the clock (depending on the variety). Most D flip-flops also have 'preset' and 'clear' inputs, which force the output to 1 or 0.		A D flop-flop has a single data input, and a clock input. It samples the input on either the rising or falling edge of the clock (depending on the variety). Most D flip-flops also have 'preset' and 'clear' inputs, which force the output to 1 or 0.
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	It is constructed out of pair of S-R latches, one after the other, along with some additional gates.		It is constructed out of pair of S-R latches, one after the other, along with some additional gates.

	==J-K flip flop==		===J-K flip flop===

	A J-K flop-flop has two data/control inputs, and a clock input. It too samples the inputs on either the rising or falling edge of the clock; again, most also have preset and clear inputs.		A J-K flop-flop has two data/control inputs, and a clock input. It too samples the inputs on either the rising or falling edge of the clock; again, most also have preset and clear inputs.

Jnc: Clarify groupings

2018-03-13T23:41:48Z

Clarify groupings

← Older revision		Revision as of 23:41, 13 March 2018
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	A '''flip-flop''' or '''latch''' (historically, the terms were somewhat interchangeably, but in contemporary usage they usually refer to disjoint sets of devices) is an extremely common element in digital logic; it is a store for one bit of state.		A '''flip-flop''' or '''latch''' (historically, the terms were somewhat interchangeably, but in contemporary usage they usually refer to disjoint sets of devices) is an extremely common element in digital logic; it is a store for one bit of state.

	Unlike [[gate]]s, which are necessarily made out of [[transistor]]s, all forms of flip-flop (there are quite a few) can be made out of gates. All involve feedback, from the outputs, to some of the inputs of the gates used to create them; they are thus subject to [[meta-stability]] issues.		Unlike [[gate]]s, which are necessarily made out of [[transistor]]s, all forms of flip-flop and latch (there are quite a few) can be made out of gates. All involve feedback, from the outputs, to some of the inputs of the gates used to create them; they are thus subject to [[meta-stability]] issues.

	They usually have one data or two control inputs, two data outputs (the data and its inversion, usually denoted 'Q' and 'Q-bar'), and optionally a clock input, which tells it when to store the current state of the input(s).		They usually have one data or two control inputs, two data outputs (the data and its inversion, usually denoted 'Q' and 'Q-bar'), and optionally a clock input, which tells it when to store the current state of the input(s).

	Of the many different varieties, the chief ~~distinction~~ is ~~between so-called 'transparent', and~~ 'edge-triggered'. ~~The former passes~~ the input data through whenever the clock input is asserted, so that the output can move up and down during that period~~; the latter only changes the output once, at either the rising or falling edge of the clock~~.		Of the many different varieties, the chief grouping is 'edge-triggered', which only change the output once, at either the rising or falling edge of the clock. Of the rest, some are 'transparent', which pass the input data through whenever the clock input is asserted, so that the output can move up and down during that period.

	In modern terminology, the term 'flip-flop' is usually reserved for the ~~latter, and~~ 'latch' is used for everything else.		In modern terminology, the term 'flip-flop' is usually reserved for the first group; 'latch' is used for everything else.

	==S-R latch==		==S-R latch==

← Older revision		Revision as of 02:17, 1 March 2024
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	Several varieties exist: the earliest versions in [[74 series]] [[transistor-transistor logic\|TTL]] [[integrated circuit\|SSI]] listened to their inputs during the period in which the clock was asserted. Later ones, 'rising-edge triggered' and 'falling-edge triggered', sample their inputs on either the rising or falling edge of the clock.		Several varieties exist: the earliest versions in [[74 series]] [[transistor-transistor logic\|TTL]] [[integrated circuit\|SSI]] listened to their inputs during the period in which the clock was asserted. Later ones, 'rising-edge triggered' and 'falling-edge triggered', sample their inputs on either the rising or falling edge of the clock.

			==Further reading==

			* William Henry Eccles, Frank Wilfred Jordan, [https://www.docjava.com/cpe210/radioReview.pdf A Trigger Relay Utilizing Three-Electrode Thermionic Vacuum Tubes], The Radio Review, Vol. 1, No. 3, December 1919, pp. 143-146

	==External links==		==External links==