ITS machine configurations - Revision history

Jnc: Avoid redir

2025-04-09T15:35:18Z

Avoid redir

2024-11-17T01:15:47Z

Equalize headers

2024-11-17T01:13:26Z

‎KS10's: Add image of AI+ML/MC

2024-07-26T20:42:54Z

‎AI KA10: link Fabritek Core Memory

2024-04-24T13:11:58Z

‎See also: MC's console

2024-02-17T12:38:27Z

MC had a Gould 5200 for a while

2024-02-12T13:25:40Z

‎MC KL10: Nice photo of MC.

2024-02-12T12:51:50Z

‎AI KA10: Had two Chaosnet interfaces

2024-02-11T23:41:01Z

‎MC KL10: Update -11's after looking at IOELEV >

2024-02-11T14:09:37Z

It was a little slow, but really, "dreck"!?

← Older revision		Revision as of 15:35, 9 April 2025
Line 1:		Line 1:
−	The configuration of the various [[Incompatible Timesharing System]] [[time-sharing]] [[PDP-10]] [[mainframe]]s at [[MIT]] (in the [[MIT Artificial Intelligence Laboratory\|AI Lab]], where it was born, and in [[MIT Laboratory for Computer Science\|LCS]], only other organization to run it 'in production') are given here. They were all physically in [[Technology Square]].	+	The configuration of the various [[Incompatible Timesharing System]] [[time-sharing]] [[PDP-10]] [[mainframe]]s at [[Massachusetts Institute of Technology\|MIT]] (in the [[MIT Artificial Intelligence Laboratory\|AI Lab]], where it was born, and in [[MIT Laboratory for Computer Science\|LCS]], only other organization to run it 'in production') are given here. They were all physically in [[Technology Square]].

	==AI PDP-6==		==AI PDP-6==

@@ Line 113: / Line 113: @@
 * [[DZ11 asynchronous serial line interface|DZ11]]
-==MC KS10==
+===MC KS10===
 No tape drive; [[backup]]s must have been done over the [[Chaosnet]].
@@ Line 123: / Line 123: @@
 * DZ11
-==ML KS10==
+===ML KS10===
 * Disk RH11
@@ Line 130: / Line 130: @@
 * 4 x DZ11
-==MD KS10==
+===MD KS10===
 * Disk RH11

@@ Line 96: / Line 96: @@
 * 'KL-UDGE' LH 1822 interface (maybe a clock, too)
-==AI KS10==
+==KS10's==
-The [[KS10]]'s were all pretty stock, hardware-wise; like the KL10, they also ran custom microcode. Also:
+[[File:AI+MC_KS10s.jpg|350px|thumb|right|The AI (left) and MC (probably; perhaps ML) KS10s]]
 * Disk [[RH11 MASSBUS controller]]

@@ Line 20: / Line 20: @@
 The AI machine was the first [[KA10]] at MIT. It was initially installed as a 'slave' processor to the AI PDP-6 in a tightly-coupled [[multi-processor]]; later the two machines swapped roles. It was the first KA10 there to support [[virtual memory]] (an MIT custom modification).
-* Eventually, 512KW of core memory: the 256KW Fabritek Core Memory moby, and another 256KW [[Ampex ARM10]]. Later they both (I think) went away, and HIC added a memory box that used [[CADR]] memory boards.
+* Eventually, 512KW of core memory: the 256KW [[Fabritek Core Memory]] moby, and another 256KW [[Ampex ARM10]]. Later they both (I think) went away, and HIC added a memory box that used [[CADR]] memory boards.
 * [[Systems Concepts DC-10]] - disk controller
 ** 8 x [[CalComp Model 215 Disk Drive|Calcomp 215]] drives

@@ Line 132: / Line 132: @@
 * CH11
 * 4 x DZ11
 ==External links==

@@ Line 90: / Line 90: @@
 ** Another PDP-11/40, the 'IO-11'
 *** DH11
 *** Later, a Trident controller
 **** Initially one, eventually three [[Trident disk drives|Trident T-300 drives]]
@@ Line 139: / Line 140: @@
 ** [https://www.computerhistory.org/collections/catalog/102803892 Knight TV Controller] - at short wall end
 ** [https://www.computerhistory.org/collections/catalog/102803897 MC KL-10] - several images
 *** [https://archive.computerhistory.org/resources/access/still-image/2024/01/102803897-03-04-acc.jpg One wing] - MF10's; also RH10 and its DF10 at the far end
 *** [https://archive.computerhistory.org/resources/access/still-image/2024/01/102803897-03-03-acc.jpg Memories] - ARM10 on right, with MF10's behind

← Older revision		Revision as of 13:25, 12 February 2024
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	==MC KL10==		==MC KL10==

		+	[[Image:MIT-MC-kludge.jpg\|thumb\|right\|300px\|MC processor, with KL-UDGE to the left.]]
	The CPU was a stock Model A; it ran custom [[microcode]], though, to implement the 'MIT paging box'. The [[main memory]] and [[channel]]s were also 100% stock. Also:		The CPU was a stock Model A; it ran custom [[microcode]], though, to implement the 'MIT paging box'. The [[main memory]] and [[channel]]s were also 100% stock. Also:

@@ Line 32: / Line 32: @@
 **** [[Xerox Graphics Printer‎|XGP]]
 ** CHAOS-11 PDP-11/10
-*** [[Chaosnet interface‎|CH11]]
+*** 2 x [[Chaosnet interface‎|CH11]]'s
 *** [[UNIBUS Experimental Ethernet interface]]
 * DH [[1822 interface]]

@@ Line 84: / Line 84: @@
 * A [[DTE20 Ten-Eleven Interface|DTE20]]
 ** A [[PDP-11/40]], the '[[front end]]' -11
-*** A bunch of serial lines, I think a [[DH11 asynchronous serial line interface|DH11]]
+*** Two [[DH11 asynchronous serial line interface|DH11]]'s
 *** A [[TC11 DECtape controller|TC11]] - which I'm not sure ITS supported
 * A [[DL10 PDP-11 Data Link|DL10]]
 ** Another PDP-11/40, the 'IO-11'
-*** A DH11
+*** DH11
 *** Later, a Trident controller
 **** Initially one, eventually three [[Trident disk drives|Trident T-300 drives]]
-*** Eventually a CH11
+*** Eventually two CH11's
 * 'KL-UDGE' LH 1822 interface (maybe a clock, too)

@@ Line 38: / Line 38: @@
 * TK10 TTY scanner
-The 'Arpanet Resources Handbook' gives the speed of the two mobies as 2.8 μseconds and 1.1 μseconds; the former seems to be the Fabridreck, so the other must be the Ampex.
+The 'Arpanet Resources Handbook' gives the speed of the two mobies as 2.8 μseconds and 1.1 μseconds; the former seems to be the Fabritek, so the other must be the Ampex.
 ==DM KA10==