Interlan NI1010A/NI2010A Ethernet Communications Controller - Revision history

Jnc: typo, clarify

2022-08-17T19:11:16Z

typo, clarify

← Older revision		Revision as of 19:11, 17 August 2022
Line 5:		Line 5:
	They use [[Direct Memory Access\|DMA]] to transfer data to and from [[buffer]]s in [[main memory]]. They have an on-board [[First-In First-Out buffer\|FIFO]] buffer which can hold up to 13.5K bytes of inbound data; the [[host]] can pre-queue up to 16 input buffer DMA requests.		They use [[Direct Memory Access\|DMA]] to transfer data to and from [[buffer]]s in [[main memory]]. They have an on-board [[First-In First-Out buffer\|FIFO]] buffer which can hold up to 13.5K bytes of inbound data; the [[host]] can pre-queue up to 16 input buffer DMA requests.

	The NI1010A is a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], including ~~a large~~ a large daughter-board. The NI2010A is a quad board, with the daughter-board stacked above the main ~~[[printed circuit board\|PCB]]~~, which is filled with [[integrated circuit\|ICs]]. It therefore takes up two slots, but only the mother card has edge fingers to plug in; a [[grant continuity card]] is supplied, to plug into the second slot, to carry the QBUS' [[bus grant line]]s through the second slot.		The NI1010A is a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], including a large daughter-board laid flush on the main [[printed circuit board\|PCB]]. The NI2010A is a quad board, with the daughter-board stacked above the main PDB, which is filled with [[integrated circuit\|ICs]]. It therefore takes up two slots, but only the mother card has edge fingers to plug in; a [[grant continuity card]] is supplied, to plug into the second slot, to carry the QBUS' [[bus grant line]]s through the second slot.

	Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches on the mother-board; to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. Their defaults are 0764000 and 0340.		Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches on the mother-board; to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. Their defaults are 0764000 and 0340.

Jnc: New cat

2022-08-17T19:07:51Z

New cat

← Older revision		Revision as of 19:07, 17 August 2022
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	[[Category: UNIBUS Network Interfaces]]		[[Category: UNIBUS Network Interfaces]]
	[[Category: QBUS Network Interfaces]]		[[Category: QBUS Network Interfaces]]
			[[Category: Ethernet Interfaces]]

Jnc: Jnc moved page Interlan NI1010A/NI2010A Ethernet interface to Interlan NI1010A/NI2010A Ethernet Communications Controller: Name as given in Interlan docs

2022-06-23T17:55:41Z

Jnc moved page Interlan NI1010A/NI2010A Ethernet interface to Interlan NI1010A/NI2010A Ethernet Communications Controller: Name as given in Interlan docs

← Older revision		Revision as of 17:55, 23 June 2022
(No difference)

Jnc: /* 17764006: Bus Address Extension Register (BER) */ +optionally

2022-06-18T10:51:17Z

17764006: Bus Address Extension Register (BER): +optionally

← Older revision		Revision as of 10:51, 18 June 2022
Line 177:		Line 177:
	Write-only register.		Write-only register.

	'''Note:''' This register is present in the NI2010A ''only''.		'''Note:''' This register is optionally present in the NI2010A ''only''.

	==External links==		==External links==

Jnc: /* External links */ - +manual, docs

2022-06-18T10:50:16Z

External links: - +manual, docs

← Older revision		Revision as of 10:50, 18 June 2022
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	'''Note:''' This register is present in the NI2010A ''only''.		'''Note:''' This register is present in the NI2010A ''only''.

			==External links==

			* [http://www.bitsavers.org/pdf/interlan/brochures/NI1010A_Brochure_Apr1984.pdf NI1010A Unibus Ethernet Communications Controller] - detailed sales brochure
			* [http://www.bitsavers.org/pdf/interlan/brochures/NI2010A_Brochure.pdf NI2010A Qbus Ethernet Communications Controller] - sales brochure
			* [http://www.bitsavers.org/pdf/interlan/NI1010A_Unibus_Ethernet_Controller_Nov82.pdf NI1010A UNIBUS Ethernet Communications Controller User's Manual]

	[[Category: UNIBUS Network Interfaces]]		[[Category: UNIBUS Network Interfaces]]
	[[Category: QBUS Network Interfaces]]		[[Category: QBUS Network Interfaces]]

Jnc: +NI2010 img, details of implementation

2022-06-17T16:12:44Z

+NI2010 img, details of implementation

← Older revision		Revision as of 16:12, 17 June 2022
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	[[Image:NI1010A.jpg\|350px\|right\|thumb\|NI1010A UNIBUS interface]]		[[Image:NI1010A.jpg\|350px\|right\|thumb\|NI1010A UNIBUS interface]]

	The '''Interlan NI1010A''' and '''NI2010A''' are [[Ethernet]] [[network interface]]s for the [[UNIBUS]] and [[QBUS]] respectively. (The two [[device controller]]s are very similar in [[program]]ming terms, so they are covered in this single article.)		The '''Interlan NI1010A''' and '''NI2010A''' are [[Ethernet]] [[network interface]]s for the [[UNIBUS]] and [[QBUS]] respectively. (The two [[device controller]]s are very similar in [[program]]ming terms, in part because they use the same [[daughter-board]] to implement all the [[data network\|networking]] functionality, so they are both covered in this single article.)

	They use [[Direct Memory Access\|DMA]] to transfer data to and from [[buffer]]s in [[main memory]]. They have an on-board [[First-In First-Out buffer\|FIFO]] buffer which can hold up to 13.5K bytes of inbound data; the [[host]] can pre-queue up to 16 input buffer DMA requests.		They use [[Direct Memory Access\|DMA]] to transfer data to and from [[buffer]]s in [[main memory]]. They have an on-board [[First-In First-Out buffer\|FIFO]] buffer which can hold up to 13.5K bytes of inbound data; the [[host]] can pre-queue up to 16 input buffer DMA requests.

	The NI1010A is a single [[DEC card form factor\|hex]] [[printed circuit board\|board]]. The NI2010A is a quad board, with ~~a large~~ [[~~daughter card~~]]~~; they take~~ two slots, but only the mother card has edge fingers to plug in~~. A~~ grant continuity card is supplied, to plug into the second slot, to carry the QBUS' [[bus grant line]]s through the slot.		The NI1010A is a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], including a large a large daughter-board. The NI2010A is a quad board, with the daughter-board stacked above the main [[printed circuit board\|PCB]], which is filled with [[integrated circuit\|ICs]]. It therefore takes up two slots, but only the mother card has edge fingers to plug in; a [[grant continuity card]] is supplied, to plug into the second slot, to carry the QBUS' [[bus grant line]]s through the second slot.

	Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches on the board; to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. Their defaults are 0764000 and 0340.		Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches on the mother-board; to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. Their defaults are 0764000 and 0340.

	There are two interrupt vectors; 0xx0 for 'Receive DMA done' and 0xx4 for 'Command done'.		There are two interrupt vectors; 0xx0 for 'Receive DMA done' and 0xx4 for 'Command done'.

	==Device registers==		==Device registers==

			[[Image:NI2010A.jpg\|300px\|right\|thumb\|NI2010A QBUS interface]]

	The NI1010A controller includes 3 [[register]]s, and the NI2010A 4 (the optional extra register is needed because of the larger [[address space]] on the QBUS):		The NI1010A controller includes 3 [[register]]s, and the NI2010A 4 (the optional extra register is needed because of the larger [[address space]] on the QBUS):

Jnc: +img

2022-06-10T14:28:48Z

+img

← Older revision		Revision as of 14:28, 10 June 2022
Line 1:		Line 1:
			[[Image:NI1010A.jpg\|350px\|right\|thumb\|NI1010A UNIBUS interface]]

	The '''Interlan NI1010A''' and '''NI2010A''' are [[Ethernet]] [[network interface]]s for the [[UNIBUS]] and [[QBUS]] respectively. (The two [[device controller]]s are very similar in [[program]]ming terms, so they are covered in this single article.)		The '''Interlan NI1010A''' and '''NI2010A''' are [[Ethernet]] [[network interface]]s for the [[UNIBUS]] and [[QBUS]] respectively. (The two [[device controller]]s are very similar in [[program]]ming terms, so they are covered in this single article.)

Jnc: clarify and reg addr typo

2021-03-30T10:26:48Z

clarify and reg addr typo

← Older revision		Revision as of 10:26, 30 March 2021
Line 5:		Line 5:
	The NI1010A is a single [[DEC card form factor\|hex]] [[printed circuit board\|board]]. The NI2010A is a quad board, with a large [[daughter card]]; they take two slots, but only the mother card has edge fingers to plug in. A grant continuity card is supplied, to plug into the second slot, to carry the QBUS' [[bus grant line]]s through the slot.		The NI1010A is a single [[DEC card form factor\|hex]] [[printed circuit board\|board]]. The NI2010A is a quad board, with a large [[daughter card]]; they take two slots, but only the mother card has edge fingers to plug in. A grant continuity card is supplied, to plug into the second slot, to carry the QBUS' [[bus grant line]]s through the slot.

	Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches on the board (to 7mnnp0, where m can be 6 or 7, and p 0,2,4 or 6; and 0xx0~~, respectively), but their~~ defaults are 0764000 and 0340.		Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches on the board; to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. Their defaults are 0764000 and 0340.

	There are two interrupt vectors; 0xx0 for 'Receive DMA done' and 0xx4 for 'Command done'.		There are two interrupt vectors; 0xx0 for 'Receive DMA done' and 0xx4 for 'Command done'.
Line 11:		Line 11:
	==Device registers==		==Device registers==

	The NI1010A controller includes 3 ~~registers~~, and the NI2010A 4 (the optional extra register is needed because of the larger [[address space]] on the QBUS):		The NI1010A controller includes 3 [[register]]s, and the NI2010A 4 (the optional extra register is needed because of the larger [[address space]] on the QBUS):

	{\| border=1		{\| border=1
Line 22:		Line 22:
	\|Byte Count Register \|\| BCR \|\| 764004		\|Byte Count Register \|\| BCR \|\| 764004
	\|-		\|-
	\|Bus Address Extension Register<br>''NI2010A only'' \|\| BER \|\| ~~774006~~		\|Bus Address Extension Register<br>''NI2010A only'' \|\| BER \|\| 17764006
	\|}		\|}

Line 165:		Line 165:
	Write-only register.		Write-only register.

	===~~7764006~~: Bus Address Extension Register (BER)===		===17764006: Bus Address Extension Register (BER)===

	{{16bit-header}}		{{16bit-header}}

Jnc: Correct 2010 hardware details, using b rochure

2019-01-18T13:56:39Z

Correct 2010 hardware details, using b rochure

← Older revision		Revision as of 13:56, 18 January 2019
Line 3:		Line 3:
	They use [[Direct Memory Access\|DMA]] to transfer data to and from [[buffer]]s in [[main memory]]. They have an on-board [[First-In First-Out buffer\|FIFO]] buffer which can hold up to 13.5K bytes of inbound data; the [[host]] can pre-queue up to 16 input buffer DMA requests.		They use [[Direct Memory Access\|DMA]] to transfer data to and from [[buffer]]s in [[main memory]]. They have an on-board [[First-In First-Out buffer\|FIFO]] buffer which can hold up to 13.5K bytes of inbound data; the [[host]] can pre-queue up to 16 input buffer DMA requests.

	The NI1010A is a single [[DEC card form factor\|hex]] [[printed circuit board\|board]]~~; the~~ NI2010A is a quad board.		The NI1010A is a single [[DEC card form factor\|hex]] [[printed circuit board\|board]]. The NI2010A is a quad board, with a large [[daughter card]]; they take two slots, but only the mother card has edge fingers to plug in. A grant continuity card is supplied, to plug into the second slot, to carry the QBUS' [[bus grant line]]s through the slot.

	Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches on the board (to 7mnnp0, where m can be 6 or 7, and p 0,2,4 or 6; and 0xx0, respectively), but their defaults are 0764000 and 0340.		Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches on the board (to 7mnnp0, where m can be 6 or 7, and p 0,2,4 or 6; and 0xx0, respectively), but their defaults are 0764000 and 0340.
Line 11:		Line 11:
	==Device registers==		==Device registers==

	The NI1010A controller includes 3 registers, and the NI2010A 4 (the extra register is needed because of the larger [[address space]] on the QBUS):		The NI1010A controller includes 3 registers, and the NI2010A 4 (the optional extra register is needed because of the larger [[address space]] on the QBUS):

	{\| border=1		{\| border=1
Line 22:		Line 22:
	\|Byte Count Register \|\| BCR \|\| 764004		\|Byte Count Register \|\| BCR \|\| 764004
	\|-		\|-
	\|~~Extended~~ Bus Address Register<br>''NI2010A only'' \|\| ~~XBAR~~ \|\| 774006		\|Bus Address Extension Register<br>''NI2010A only'' \|\| BER \|\| 774006
	\|}		\|}

	~~Documentation on the NI2010A is currently scarce, but there are some indications that the Extended~~ Bus Address Register was enabled by a ~~jumper~~; i.e. the NI2010A could be set to be identical, programmatically, to the NI1010A.		The Bus Address Extension Register was enabled by a switch; i.e. the NI2010A could be set to be identical, programmatically, to the NI1010A, at the cost of not being able to use more than 256KB of main memory.

	In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics'', and those which are write-only are shown in '''bold'''.		In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics'', and those which are write-only are shown in '''bold'''.
Line 53:		Line 53:
	\| STAT \|\| Command Status Code		\| STAT \|\| Command Status Code
	\|}		\|}

			Reading the CSR clears the two 'done' bits. The extended address bits are disabled on the NI2010A when the BER is enabled.

	Command function codes are:		Command function codes are:
Line 150:		Line 152:
	===764002: Bus Address Register (BAR)===		===764002: Bus Address Register (BAR)===
	{{16bit-header}}		{{16bit-header}}
	\| colspan=16 \| BA15 <---> BA00		\| colspan=16 \| '''BA15 <---> BA00'''
	{{16bitoctal-bitout}}		{{16bitoctal-bitout}}

Line 158:		Line 160:

	{{16bit-header}}		{{16bit-header}}
	\| colspan=16 \| BC15 <---> BC0		\| colspan=16 \| '''BC15 <---> BC0'''
	{{16bitoctal-bitout}}		{{16bitoctal-bitout}}

	Write-only register.		Write-only register.

	===7764006: ~~Extended~~ Bus Address Register (~~XBAR~~)===		===7764006: Bus Address Extension Register (BER)===

	{{16bit-header}}		{{16bit-header}}
	\| colspan=10 \| Unused \|\| colspan=6 \| BA21 <---> BA16		\| colspan=10 \| Unused \|\| colspan=6 \| '''BA21 <---> BA16'''
	{{16bitoctal-bitout}}		{{16bitoctal-bitout}}

	Write-only register?		Write-only register.

	'''Note:''' This register is present in the NI2010A ''only''.		'''Note:''' This register is present in the NI2010A ''only''.

Jnc: rm dup header, +links

2019-01-17T13:57:29Z

rm dup header, +links

← Older revision		Revision as of 13:57, 17 January 2019
Line 1:		Line 1:
	The '''Interlan NI1010A''' and '''NI2010A''' are [[Ethernet]] [[~~device controller~~]]s for the [[UNIBUS]] and [[QBUS]] respectively. (~~They~~ are very similar, so they are covered in this single article.)		The '''Interlan NI1010A''' and '''NI2010A''' are [[Ethernet]] [[network interface]]s for the [[UNIBUS]] and [[QBUS]] respectively. (The two [[device controller]]s are very similar in [[program]]ming terms, so they are covered in this single article.)

	They use [[Direct Memory Access\|DMA]] to transfer data to and from [[buffer]]s in [[main memory]]. They have an on-board [[First-In First-Out buffer\|FIFO]] buffer which can hold up to 13.5K bytes of inbound data; the [[host]] can pre-queue up to 16 input buffer DMA requests.		They use [[Direct Memory Access\|DMA]] to transfer data to and from [[buffer]]s in [[main memory]]. They have an on-board [[First-In First-Out buffer\|FIFO]] buffer which can hold up to 13.5K bytes of inbound data; the [[host]] can pre-queue up to 16 input buffer DMA requests.
Line 8:		Line 8:

	There are two interrupt vectors; 0xx0 for 'Receive DMA done' and 0xx4 for 'Command done'.		There are two interrupt vectors; 0xx0 for 'Receive DMA done' and 0xx4 for 'Command done'.

	~~==Registers==~~

	==Device registers==		==Device registers==

← Older revision		Revision as of 19:11, 17 August 2022
Line 5:		Line 5:
	They use [[Direct Memory Access\|DMA]] to transfer data to and from [[buffer]]s in [[main memory]]. They have an on-board [[First-In First-Out buffer\|FIFO]] buffer which can hold up to 13.5K bytes of inbound data; the [[host]] can pre-queue up to 16 input buffer DMA requests.		They use [[Direct Memory Access\|DMA]] to transfer data to and from [[buffer]]s in [[main memory]]. They have an on-board [[First-In First-Out buffer\|FIFO]] buffer which can hold up to 13.5K bytes of inbound data; the [[host]] can pre-queue up to 16 input buffer DMA requests.

	The NI1010A is a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], including ~~a large~~ a large daughter-board. The NI2010A is a quad board, with the daughter-board stacked above the main ~~[[printed circuit board\|PCB]]~~, which is filled with [[integrated circuit\|ICs]]. It therefore takes up two slots, but only the mother card has edge fingers to plug in; a [[grant continuity card]] is supplied, to plug into the second slot, to carry the QBUS' [[bus grant line]]s through the second slot.		The NI1010A is a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], including a large daughter-board laid flush on the main [[printed circuit board\|PCB]]. The NI2010A is a quad board, with the daughter-board stacked above the main PDB, which is filled with [[integrated circuit\|ICs]]. It therefore takes up two slots, but only the mother card has edge fingers to plug in; a [[grant continuity card]] is supplied, to plug into the second slot, to carry the QBUS' [[bus grant line]]s through the second slot.

	Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches on the mother-board; to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. Their defaults are 0764000 and 0340.		Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package\|DIP]] switches on the mother-board; to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. Their defaults are 0764000 and 0340.